source: rtems/c/src/exec/score/cpu/a29k/cpu.h @ a4d97d94

4.104.114.84.95
Last change on this file since a4d97d94 was a4d97d94, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 18, 1996 at 8:45:27 PM

new files submitted by Craig Lebakken (lebakken@…) and Derrick Ostertag
(ostertag@…).

  • Property mode set to 100644
File size: 31.3 KB
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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the AMD 29K
4 *  processor.
5 *
6 *  Author:     Craig Lebakken <craigl@transition.com>
7 *
8 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of Transition Networks not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      Transition Networks makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c:
22 *
23 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
24 *  On-Line Applications Research Corporation (OAR).
25 *  All rights assigned to U.S. Government, 1994.
26 *
27 *  This material may be reproduced by or for the U.S. Government pursuant
28 *  to the copyright license under the clause at DFARS 252.227-7013.  This
29 *  notice must appear in all copies of this file and its derivatives.
30 *
31 *  $Id$
32 */
33/* @(#)cpu.h       09/06/96     1.10 */
34
35#ifndef __CPU_h
36#define __CPU_h
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/a29k.h>               /* pick up machine definitions */
43#ifndef ASM
44#include <rtems/score/a29ktypes.h>
45#endif
46
47extern unsigned int a29k_disable( void );
48extern void a29k_enable( unsigned int cookie );
49extern void a29k_disable_sup( void );
50extern void a29k_enable_sup( void );
51extern void a29k_disable_all( void );
52extern void a29k_disable_all_sup( void );
53extern void a29k_enable_all( void );
54extern void a29k_enable_all_sup( void );
55extern void a29k_halt( void );
56extern void a29k_fatal_error( unsigned32 error );
57extern void a29k_as70( void );
58extern void a29k_super_mode( void );
59extern void a29k_context_switch_sup(void);
60extern void a29k_context_restore_sup(void);
61extern void a29k_context_save_sup(void);
62extern void a29k_sigdfl_sup(void);
63
64/* conditional compilation parameters */
65
66/*
67 *  Should the calls to _Thread_Enable_dispatch be inlined?
68 *
69 *  If TRUE, then they are inlined.
70 *  If FALSE, then a subroutine call is made.
71 *
72 *  Basically this is an example of the classic trade-off of size
73 *  versus speed.  Inlining the call (TRUE) typically increases the
74 *  size of RTEMS while speeding up the enabling of dispatching.
75 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
76 *  only be 0 or 1 unless you are in an interrupt handler and that
77 *  interrupt handler invokes the executive.]  When not inlined
78 *  something calls _Thread_Enable_dispatch which in turns calls
79 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
80 *  one subroutine call is avoided entirely.]
81 */
82
83#define CPU_INLINE_ENABLE_DISPATCH       TRUE
84
85/*
86 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
87 *  be unrolled one time?  In unrolled each iteration of the loop examines
88 *  two "nodes" on the chain being searched.  Otherwise, only one node
89 *  is examined per iteration.
90 *
91 *  If TRUE, then the loops are unrolled.
92 *  If FALSE, then the loops are not unrolled.
93 *
94 *  The primary factor in making this decision is the cost of disabling
95 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
96 *  body of the loop.  On some CPUs, the flash is more expensive than
97 *  one iteration of the loop body.  In this case, it might be desirable
98 *  to unroll the loop.  It is important to note that on some CPUs, this
99 *  code is the longest interrupt disable period in RTEMS.  So it is
100 *  necessary to strike a balance when setting this parameter.
101 */
102
103#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
104
105/*
106 *  Does RTEMS manage a dedicated interrupt stack in software?
107 *
108 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
109 *  If FALSE, nothing is done.
110 *
111 *  If the CPU supports a dedicated interrupt stack in hardware,
112 *  then it is generally the responsibility of the BSP to allocate it
113 *  and set it up.
114 *
115 *  If the CPU does not support a dedicated interrupt stack, then
116 *  the porter has two options: (1) execute interrupts on the
117 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
118 *  interrupt stack.
119 *
120 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
121 *
122 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
123 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
124 *  possible that both are FALSE for a particular CPU.  Although it
125 *  is unclear what that would imply about the interrupt processing
126 *  procedure on that CPU.
127 */
128
129#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
130
131/*
132 *  Does this CPU have hardware support for a dedicated interrupt stack?
133 *
134 *  If TRUE, then it must be installed during initialization.
135 *  If FALSE, then no installation is performed.
136 *
137 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
138 *
139 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
140 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
141 *  possible that both are FALSE for a particular CPU.  Although it
142 *  is unclear what that would imply about the interrupt processing
143 *  procedure on that CPU.
144 */
145
146#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
147
148/*
149 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
150 *
151 *  If TRUE, then the memory is allocated during initialization.
152 *  If FALSE, then the memory is allocated during initialization.
153 *
154 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
155 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
156 */
157
158#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
159
160/*
161 *  Does the CPU have hardware floating point?
162 *
163 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
164 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
165 *
166 *  If there is a FP coprocessor such as the i387 or mc68881, then
167 *  the answer is TRUE.
168 *
169 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
170 *  It indicates whether or not this CPU model has FP support.  For
171 *  example, it would be possible to have an i386_nofp CPU model
172 *  which set this to false to indicate that you have an i386 without
173 *  an i387 and wish to leave floating point support out of RTEMS.
174 */
175
176#if ( A29K_HAS_FPU == 1 )
177#define CPU_HARDWARE_FP     TRUE
178#else
179#define CPU_HARDWARE_FP     FALSE
180#endif
181
182/*
183 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
184 *
185 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
186 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
187 *
188 *  So far, the only CPU in which this option has been used is the
189 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
190 *  floating point registers to perform integer multiplies.  If
191 *  a function which you would not think utilize the FP unit DOES,
192 *  then one can not easily predict which tasks will use the FP hardware.
193 *  In this case, this option should be TRUE.
194 *
195 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
196 */
197
198#define CPU_ALL_TASKS_ARE_FP     FALSE
199
200/*
201 *  Should the IDLE task have a floating point context?
202 *
203 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
204 *  and it has a floating point context which is switched in and out.
205 *  If FALSE, then the IDLE task does not have a floating point context.
206 *
207 *  Setting this to TRUE negatively impacts the time required to preempt
208 *  the IDLE task from an interrupt because the floating point context
209 *  must be saved as part of the preemption.
210 */
211
212#define CPU_IDLE_TASK_IS_FP      FALSE
213
214/*
215 *  Should the saving of the floating point registers be deferred
216 *  until a context switch is made to another different floating point
217 *  task?
218 *
219 *  If TRUE, then the floating point context will not be stored until
220 *  necessary.  It will remain in the floating point registers and not
221 *  disturned until another floating point task is switched to.
222 *
223 *  If FALSE, then the floating point context is saved when a floating
224 *  point task is switched out and restored when the next floating point
225 *  task is restored.  The state of the floating point registers between
226 *  those two operations is not specified.
227 *
228 *  If the floating point context does NOT have to be saved as part of
229 *  interrupt dispatching, then it should be safe to set this to TRUE.
230 *
231 *  Setting this flag to TRUE results in using a different algorithm
232 *  for deciding when to save and restore the floating point context.
233 *  The deferred FP switch algorithm minimizes the number of times
234 *  the FP context is saved and restored.  The FP context is not saved
235 *  until a context switch is made to another, different FP task.
236 *  Thus in a system with only one FP task, the FP context will never
237 *  be saved or restored.
238 */
239
240#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
241
242/*
243 *  Does this port provide a CPU dependent IDLE task implementation?
244 *
245 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
246 *  must be provided and is the default IDLE thread body instead of
247 *  _Internal_threads_Idle_thread_body.
248 *
249 *  If FALSE, then use the generic IDLE thread body if the BSP does
250 *  not provide one.
251 *
252 *  This is intended to allow for supporting processors which have
253 *  a low power or idle mode.  When the IDLE thread is executed, then
254 *  the CPU can be powered down.
255 *
256 *  The order of precedence for selecting the IDLE thread body is:
257 *
258 *    1.  BSP provided
259 *    2.  CPU dependent (if provided)
260 *    3.  generic (if no BSP and no CPU dependent)
261 */
262
263#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
264
265/*
266 *  Does the stack grow up (toward higher addresses) or down
267 *  (toward lower addresses)?
268 *
269 *  If TRUE, then the grows upward.
270 *  If FALSE, then the grows toward smaller addresses.
271 */
272
273#define CPU_STACK_GROWS_UP               FALSE
274
275/*
276 *  The following is the variable attribute used to force alignment
277 *  of critical RTEMS structures.  On some processors it may make
278 *  sense to have these aligned on tighter boundaries than
279 *  the minimum requirements of the compiler in order to have as
280 *  much of the critical data area as possible in a cache line.
281 *
282 *  The placement of this macro in the declaration of the variables
283 *  is based on the syntactically requirements of the GNU C
284 *  "__attribute__" extension.  For example with GNU C, use
285 *  the following to force a structures to a 32 byte boundary.
286 *
287 *      __attribute__ ((aligned (32)))
288 *
289 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
290 *         To benefit from using this, the data must be heavily
291 *         used so it will stay in the cache and used frequently enough
292 *         in the executive to justify turning this on.
293 */
294
295#define CPU_STRUCTURE_ALIGNMENT
296
297/*
298 *  The following defines the number of bits actually used in the
299 *  interrupt field of the task mode.  How those bits map to the
300 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
301 */
302
303#define CPU_MODES_INTERRUPT_MASK   0x00000001
304
305/*
306 *  Processor defined structures
307 *
308 *  Examples structures include the descriptor tables from the i386
309 *  and the processor control structure on the i960ca.
310 */
311
312/* may need to put some structures here.  */
313
314/*
315 * Contexts
316 *
317 *  Generally there are 2 types of context to save.
318 *     1. Interrupt registers to save
319 *     2. Task level registers to save
320 *
321 *  This means we have the following 3 context items:
322 *     1. task level context stuff::  Context_Control
323 *     2. floating point task stuff:: Context_Control_fp
324 *     3. special interrupt level context :: Context_Control_interrupt
325 *
326 *  On some processors, it is cost-effective to save only the callee
327 *  preserved registers during a task context switch.  This means
328 *  that the ISR code needs to save those registers which do not
329 *  persist across function calls.  It is not mandatory to make this
330 *  distinctions between the caller/callee saves registers for the
331 *  purpose of minimizing context saved during task switch and on interrupts.
332 *  If the cost of saving extra registers is minimal, simplicity is the
333 *  choice.  Save the same context on interrupt entry as for tasks in
334 *  this case.
335 *
336 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
337 *  care should be used in designing the context area.
338 *
339 *  On some CPUs with hardware floating point support, the Context_Control_fp
340 *  structure will not be used or it simply consist of an array of a
341 *  fixed number of bytes.   This is done when the floating point context
342 *  is dumped by a "FP save context" type instruction and the format
343 *  is not really defined by the CPU.  In this case, there is no need
344 *  to figure out the exact format -- only the size.  Of course, although
345 *  this is enough information for RTEMS, it is probably not enough for
346 *  a debugger such as gdb.  But that is another problem.
347 */
348
349typedef struct {
350    unsigned32 signal;
351    unsigned32 gr1;
352    unsigned32 rab;
353    unsigned32 PC0;
354    unsigned32 PC1;
355    unsigned32 PC2;
356    unsigned32 CHA;
357    unsigned32 CHD;
358    unsigned32 CHC;
359    unsigned32 ALU;
360    unsigned32 OPS;
361    unsigned32 tav;
362    unsigned32 lr1;
363    unsigned32 rfb;
364    unsigned32 msp;
365
366    unsigned32 FPStat0;
367    unsigned32 FPStat1;
368    unsigned32 FPStat2;
369    unsigned32 IPA;
370    unsigned32 IPB;
371    unsigned32 IPC;
372    unsigned32 Q;
373
374    unsigned32 gr96;
375    unsigned32 gr97;
376    unsigned32 gr98;
377    unsigned32 gr99;
378    unsigned32 gr100;
379    unsigned32 gr101;
380    unsigned32 gr102;
381    unsigned32 gr103;
382    unsigned32 gr104;
383    unsigned32 gr105;
384    unsigned32 gr106;
385    unsigned32 gr107;
386    unsigned32 gr108;
387    unsigned32 gr109;
388    unsigned32 gr110;
389    unsigned32 gr111;
390
391    unsigned32 gr112;
392    unsigned32 gr113;
393    unsigned32 gr114;
394    unsigned32 gr115;
395
396    unsigned32 gr116;
397    unsigned32 gr117;
398    unsigned32 gr118;
399    unsigned32 gr119;
400    unsigned32 gr120;
401    unsigned32 gr121;
402    unsigned32 gr122;
403    unsigned32 gr123;
404    unsigned32 gr124;
405
406    unsigned32 local_count;
407
408    unsigned32 locals[128];
409} Context_Control;
410
411typedef struct {
412    double      some_float_register;
413} Context_Control_fp;
414
415typedef struct {
416    unsigned32 special_interrupt_register;
417} CPU_Interrupt_frame;
418
419
420/*
421 *  The following table contains the information required to configure
422 *  the XXX processor specific parameters.
423 *
424 *  NOTE: The interrupt_stack_size field is required if
425 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
426 *
427 *        The pretasking_hook, predriver_hook, and postdriver_hook,
428 *        and the do_zero_of_workspace fields are required on ALL CPUs.
429 */
430
431typedef struct {
432  void       (*pretasking_hook)( void );
433  void       (*predriver_hook)( void );
434  void       (*postdriver_hook)( void );
435  void       (*idle_task)( void );
436  boolean      do_zero_of_workspace;
437  unsigned32   interrupt_stack_size;
438  unsigned32   extra_system_initialization_stack;
439  unsigned32   some_other_cpu_dependent_info;
440}   rtems_cpu_table;
441
442/*
443 *  This variable is optional.  It is used on CPUs on which it is difficult
444 *  to generate an "uninitialized" FP context.  It is filled in by
445 *  _CPU_Initialize and copied into the task's FP context area during
446 *  _CPU_Context_Initialize.
447 */
448
449EXTERN Context_Control_fp  _CPU_Null_fp_context;
450
451/*
452 *  On some CPUs, RTEMS supports a software managed interrupt stack.
453 *  This stack is allocated by the Interrupt Manager and the switch
454 *  is performed in _ISR_Handler.  These variables contain pointers
455 *  to the lowest and highest addresses in the chunk of memory allocated
456 *  for the interrupt stack.  Since it is unknown whether the stack
457 *  grows up or down (in general), this give the CPU dependent
458 *  code the option of picking the version it wants to use.
459 *
460 *  NOTE: These two variables are required if the macro
461 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
462 */
463
464EXTERN void               *_CPU_Interrupt_stack_low;
465EXTERN void               *_CPU_Interrupt_stack_high;
466
467/*
468 *  With some compilation systems, it is difficult if not impossible to
469 *  call a high-level language routine from assembly language.  This
470 *  is especially true of commercial Ada compilers and name mangling
471 *  C++ ones.  This variable can be optionally defined by the CPU porter
472 *  and contains the address of the routine _Thread_Dispatch.  This
473 *  can make it easier to invoke that routine at the end of the interrupt
474 *  sequence (if a dispatch is necessary).
475 */
476
477EXTERN void           (*_CPU_Thread_dispatch_pointer)();
478
479/*
480 *  Nothing prevents the porter from declaring more CPU specific variables.
481 */
482
483/* XXX: if needed, put more variables here */
484
485/*
486 *  The size of the floating point context area.  On some CPUs this
487 *  will not be a "sizeof" because the format of the floating point
488 *  area is not defined -- only the size is.  This is usually on
489 *  CPUs with a "floating point save context" instruction.
490 */
491
492#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
493
494/*
495 *  Amount of extra stack (above minimum stack size) required by
496 *  system initialization thread.  Remember that in a multiprocessor
497 *  system the system intialization thread becomes the MP server thread.
498 */
499
500#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
501
502/*
503 *  This defines the number of entries in the ISR_Vector_table managed
504 *  by RTEMS.
505 */
506
507#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
508#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
509
510/*
511 *  Should be large enough to run all RTEMS tests.  This insures
512 *  that a "reasonable" small application should not have any problems.
513 */
514
515#define CPU_STACK_MINIMUM_SIZE          (8192)
516
517/*
518 *  CPU's worst alignment requirement for data types on a byte boundary.  This
519 *  alignment does not take into account the requirements for the stack.
520 */
521
522#define CPU_ALIGNMENT              4
523
524/*
525 *  This number corresponds to the byte alignment requirement for the
526 *  heap handler.  This alignment requirement may be stricter than that
527 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
528 *  common for the heap to follow the same alignment requirement as
529 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
530 *  then this should be set to CPU_ALIGNMENT.
531 *
532 *  NOTE:  This does not have to be a power of 2.  It does have to
533 *         be greater or equal to than CPU_ALIGNMENT.
534 */
535
536#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
537
538/*
539 *  This number corresponds to the byte alignment requirement for memory
540 *  buffers allocated by the partition manager.  This alignment requirement
541 *  may be stricter than that for the data types alignment specified by
542 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
543 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
544 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
545 *
546 *  NOTE:  This does not have to be a power of 2.  It does have to
547 *         be greater or equal to than CPU_ALIGNMENT.
548 */
549
550#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
551
552/*
553 *  This number corresponds to the byte alignment requirement for the
554 *  stack.  This alignment requirement may be stricter than that for the
555 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
556 *  is strict enough for the stack, then this should be set to 0.
557 *
558 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
559 */
560
561#define CPU_STACK_ALIGNMENT        0
562
563/* ISR handler macros */
564
565/*
566 *  Disable all interrupts for an RTEMS critical section.  The previous
567 *  level is returned in _level.
568 */
569
570#define _CPU_ISR_Disable( _isr_cookie ) \
571    do{ _isr_cookie = a29k_disable(); }while(0)
572
573/*
574 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
575 *  This indicates the end of an RTEMS critical section.  The parameter
576 *  _level is not modified.
577 */
578
579#define _CPU_ISR_Enable( _isr_cookie )  \
580      do{ a29k_enable(_isr_cookie) ; }while(0)
581
582/*
583 *  This temporarily restores the interrupt to _level before immediately
584 *  disabling them again.  This is used to divide long RTEMS critical
585 *  sections into two or more parts.  The parameter _level is not
586 * modified.
587 */
588
589#define _CPU_ISR_Flash( _isr_cookie ) \
590  do{ \
591     _CPU_ISR_Enable( _isr_cookie ); \
592     _CPU_ISR_Disable( _isr_cookie ); \
593  }while(0)
594
595/*
596 *  Map interrupt level in task mode onto the hardware that the CPU
597 *  actually provides.  Currently, interrupt levels which do not
598 *  map onto the CPU in a generic fashion are undefined.  Someday,
599 *  it would be nice if these were "mapped" by the application
600 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
601 *  8 - 255 would be available for bsp/application specific meaning.
602 *  This could be used to manage a programmable interrupt controller
603 *  via the rtems_task_mode directive.
604 */
605
606#define _CPU_ISR_Set_level( new_level ) \
607  do{ \
608    if ( new_level ) a29k_disable_all(); \
609    else a29k_enable_all(); \
610  }while(0);
611
612/* end of ISR handler macros */
613
614/* Context handler macros */
615
616extern void _CPU_Context_save(
617  Context_Control *new_context
618);
619
620/*
621 *  Initialize the context to a state suitable for starting a
622 *  task after a context restore operation.  Generally, this
623 *  involves:
624 *
625 *     - setting a starting address
626 *     - preparing the stack
627 *     - preparing the stack and frame pointers
628 *     - setting the proper interrupt level in the context
629 *     - initializing the floating point context
630 *
631 *  This routine generally does not set any unnecessary register
632 *  in the context.  The state of the "general data" registers is
633 *  undefined at task start time.
634 *
635 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
636 *        point thread.  This is typically only used on CPUs where the
637 *        FPU may be easily disabled by software such as on the SPARC
638 *        where the PSR contains an enable FPU bit.
639 */
640
641#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
642                                 _isr, _entry_point, _is_fp ) \
643  do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */           \
644      unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size);  \
645      unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \
646      _mem_stack_tmp &= ~(CPU_ALIGNMENT-1);                         \
647      _reg_stack_tmp &= ~(CPU_ALIGNMENT-1);                         \
648      _CPU_Context_save(_the_context);                              \
649      (_the_context)->msp = _mem_stack_tmp;           /* gr125 */   \
650      (_the_context)->lr1 =                                         \
651      (_the_context)->locals[1] =                                   \
652      (_the_context)->rfb = _reg_stack_tmp;           /* gr127 */   \
653      (_the_context)->gr1 = _reg_stack_tmp - 4 * 4;                 \
654      (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */   \
655      (_the_context)->local_count = 1-1;                            \
656      (_the_context)->PC1 = _entry_point;                           \
657      (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \
658  }while(0)
659
660/*
661 *  This routine is responsible for somehow restarting the currently
662 *  executing task.  If you are lucky, then all that is necessary
663 *  is restoring the context.  Otherwise, there will need to be
664 *  a special assembly routine which does something special in this
665 *  case.  Context_Restore should work most of the time.  It will
666 *  not work if restarting self conflicts with the stack frame
667 *  assumptions of restoring a context.
668 */
669
670#define _CPU_Context_Restart_self( _the_context ) \
671   _CPU_Context_restore( (_the_context) )
672
673/*
674 *  The purpose of this macro is to allow the initial pointer into
675 *  a floating point context area (used to save the floating point
676 *  context) to be at an arbitrary place in the floating point
677 *  context area.
678 *
679 *  This is necessary because some FP units are designed to have
680 *  their context saved as a stack which grows into lower addresses.
681 *  Other FP units can be saved by simply moving registers into offsets
682 *  from the base of the context area.  Finally some FP units provide
683 *  a "dump context" instruction which could fill in from high to low
684 *  or low to high based on the whim of the CPU designers.
685 */
686
687#define _CPU_Context_Fp_start( _base, _offset ) \
688   ( (char *) (_base) + (_offset) )
689
690/*
691 *  This routine initializes the FP context area passed to it to.
692 *  There are a few standard ways in which to initialize the
693 *  floating point context.  The code included for this macro assumes
694 *  that this is a CPU in which a "initial" FP context was saved into
695 *  _CPU_Null_fp_context and it simply copies it to the destination
696 *  context passed to it.
697 *
698 *  Other models include (1) not doing anything, and (2) putting
699 *  a "null FP status word" in the correct place in the FP context.
700 */
701
702#define _CPU_Context_Initialize_fp( _destination ) \
703  do { \
704   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
705  } while(0)
706
707/* end of Context handler macros */
708
709/* Fatal Error manager macros */
710
711/*
712 *  This routine copies _error into a known place -- typically a stack
713 *  location or a register, optionally disables interrupts, and
714 *  halts/stops the CPU.
715 */
716
717#define _CPU_Fatal_halt( _error ) \
718        a29k_fatal_error(_error)
719
720/* end of Fatal Error manager macros */
721
722/* Bitfield handler macros */
723
724/*
725 *  This routine sets _output to the bit number of the first bit
726 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
727 *  This type may be either 16 or 32 bits wide although only the 16
728 *  least significant bits will be used.
729 *
730 *  There are a number of variables in using a "find first bit" type
731 *  instruction.
732 *
733 *    (1) What happens when run on a value of zero?
734 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
735 *    (3) The numbering may be zero or one based.
736 *    (4) The "find first bit" instruction may search from MSB or LSB.
737 *
738 *  RTEMS guarantees that (1) will never happen so it is not a concern.
739 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
740 *  _CPU_Priority_bits_index().  These three form a set of routines
741 *  which must logically operate together.  Bits in the _value are
742 *  set and cleared based on masks built by _CPU_Priority_mask().
743 *  The basic major and minor values calculated by _Priority_Major()
744 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
745 *  to properly range between the values returned by the "find first bit"
746 *  instruction.  This makes it possible for _Priority_Get_highest() to
747 *  calculate the major and directly index into the minor table.
748 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
749 *  is the first bit found.
750 *
751 *  This entire "find first bit" and mapping process depends heavily
752 *  on the manner in which a priority is broken into a major and minor
753 *  components with the major being the 4 MSB of a priority and minor
754 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
755 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
756 *  to the lowest priority.
757 *
758 *  If your CPU does not have a "find first bit" instruction, then
759 *  there are ways to make do without it.  Here are a handful of ways
760 *  to implement this in software:
761 *
762 *    - a series of 16 bit test instructions
763 *    - a "binary search using if's"
764 *    - _number = 0
765 *      if _value > 0x00ff
766 *        _value >>=8
767 *        _number = 8;
768 *
769 *      if _value > 0x0000f
770 *        _value >=8
771 *        _number += 4
772 *
773 *      _number += bit_set_table[ _value ]
774 *
775 *    where bit_set_table[ 16 ] has values which indicate the first
776 *      bit set
777 */
778
779#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
780#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
781
782#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
783
784#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
785  { \
786    (_output) = 0;   /* do something to prevent warnings */ \
787  }
788
789#endif
790
791/* end of Bitfield handler macros */
792
793/*
794 *  This routine builds the mask which corresponds to the bit fields
795 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
796 *  for that routine.
797 */
798
799#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
800
801#define _CPU_Priority_Mask( _bit_number ) \
802  ( 1 << (_bit_number) )
803
804#endif
805
806/*
807 *  This routine translates the bit numbers returned by
808 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
809 *  a major or minor component of a priority.  See the discussion
810 *  for that routine.
811 */
812
813#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
814
815#define _CPU_Priority_bits_index( _priority ) \
816  (_priority)
817
818#endif
819
820/* end of Priority handler macros */
821
822/* functions */
823
824/*
825 *  _CPU_Initialize
826 *
827 *  This routine performs CPU dependent initialization.
828 */
829
830void _CPU_Initialize(
831  rtems_cpu_table  *cpu_table,
832  void      (*thread_dispatch)()
833);
834
835/*
836 *  _CPU_ISR_install_raw_handler
837 *
838 *  This routine installs a "raw" interrupt handler directly into the
839 *  processor's vector table.
840 */
841 
842void _CPU_ISR_install_raw_handler(
843  unsigned32  vector,
844  proc_ptr    new_handler,
845  proc_ptr   *old_handler
846);
847
848/*
849 *  _CPU_ISR_install_vector
850 *
851 *  This routine installs an interrupt vector.
852 */
853
854void _CPU_ISR_install_vector(
855  unsigned32  vector,
856  proc_ptr    new_handler,
857  proc_ptr   *old_handler
858);
859
860/*
861 *  _CPU_Install_interrupt_stack
862 *
863 *  This routine installs the hardware interrupt stack pointer.
864 *
865 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
866 *         is TRUE.
867 */
868
869void _CPU_Install_interrupt_stack( void );
870
871/*
872 *  _CPU_Internal_threads_Idle_thread_body
873 *
874 *  This routine is the CPU dependent IDLE thread body.
875 *
876 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
877 *         is TRUE.
878 */
879
880void _CPU_Internal_threads_Idle_thread_body( void );
881
882/*
883 *  _CPU_Context_switch
884 *
885 *  This routine switches from the run context to the heir context.
886 */
887
888void _CPU_Context_switch(
889  Context_Control  *run,
890  Context_Control  *heir
891);
892
893/*
894 *  _CPU_Context_restore
895 *
896 *  This routine is generallu used only to restart self in an
897 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
898 *
899 *  NOTE: May be unnecessary to reload some registers.
900 */
901
902void _CPU_Context_restore(
903  Context_Control *new_context
904);
905
906/*
907 *  _CPU_Context_save_fp
908 *
909 *  This routine saves the floating point context passed to it.
910 */
911
912void _CPU_Context_save_fp(
913  void **fp_context_ptr
914);
915
916/*
917 *  _CPU_Context_restore_fp
918 *
919 *  This routine restores the floating point context passed to it.
920 */
921
922void _CPU_Context_restore_fp(
923  void **fp_context_ptr
924);
925
926/*  The following routine swaps the endian format of an unsigned int.
927 *  It must be static because it is referenced indirectly.
928 *
929 *  This version will work on any processor, but if there is a better
930 *  way for your CPU PLEASE use it.  The most common way to do this is to:
931 *
932 *     swap least significant two bytes with 16-bit rotate
933 *     swap upper and lower 16-bits
934 *     swap most significant two bytes with 16-bit rotate
935 *
936 *  Some CPUs have special instructions which swap a 32-bit quantity in
937 *  a single instruction (e.g. i486).  It is probably best to avoid
938 *  an "endian swapping control bit" in the CPU.  One good reason is
939 *  that interrupts would probably have to be disabled to insure that
940 *  an interrupt does not try to access the same "chunk" with the wrong
941 *  endian.  Another good reason is that on some CPUs, the endian bit
942 *  endianness for ALL fetches -- both code and data -- so the code
943 *  will be fetched incorrectly.
944 */
945 
946#define CPU_swap_u32( value ) \
947  ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | (((value >> 16)&0xff) << 8) | ((value>>24)&0xff)
948
949#ifdef __cplusplus
950}
951#endif
952
953#endif
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