source: rtems/c/src/exec/score/cpu/a29k/cpu.h @ 29d8227e

4.104.114.84.95
Last change on this file since 29d8227e was 29d8227e, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 2, 1996 at 7:48:29 PM

Updates from Derrick Ostertag <ostertag@…> to fix bug in
interrupt handling.

  • Property mode set to 100644
File size: 31.6 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the AMD 29K
4 *  processor.
5 *
6 *  Author:     Craig Lebakken <craigl@transition.com>
7 *
8 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of Transition Networks not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      Transition Networks makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c:
22 *
23 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
24 *  On-Line Applications Research Corporation (OAR).
25 *  All rights assigned to U.S. Government, 1994.
26 *
27 *  This material may be reproduced by or for the U.S. Government pursuant
28 *  to the copyright license under the clause at DFARS 252.227-7013.  This
29 *  notice must appear in all copies of this file and its derivatives.
30 *
31 *  $Id$
32 */
33/* @(#)cpu.h    10/21/96        1.11 */
34
35#ifndef __CPU_h
36#define __CPU_h
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/a29k.h>               /* pick up machine definitions */
43#ifndef ASM
44#include <rtems/score/a29ktypes.h>
45#endif
46
47extern unsigned int a29k_disable( void );
48extern void a29k_enable( unsigned int cookie );
49extern unsigned int a29k_getops( void );
50extern void a29k_getops_sup( void );
51extern void a29k_disable_sup( void );
52extern void a29k_enable_sup( void );
53extern void a29k_disable_all( void );
54extern void a29k_disable_all_sup( void );
55extern void a29k_enable_all( void );
56extern void a29k_enable_all_sup( void );
57extern void a29k_halt( void );
58extern void a29k_fatal_error( unsigned32 error );
59extern void a29k_as70( void );
60extern void a29k_super_mode( void );
61extern void a29k_context_switch_sup(void);
62extern void a29k_context_restore_sup(void);
63extern void a29k_context_save_sup(void);
64extern void a29k_sigdfl_sup(void);
65
66/* conditional compilation parameters */
67
68/*
69 *  Should the calls to _Thread_Enable_dispatch be inlined?
70 *
71 *  If TRUE, then they are inlined.
72 *  If FALSE, then a subroutine call is made.
73 *
74 *  Basically this is an example of the classic trade-off of size
75 *  versus speed.  Inlining the call (TRUE) typically increases the
76 *  size of RTEMS while speeding up the enabling of dispatching.
77 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
78 *  only be 0 or 1 unless you are in an interrupt handler and that
79 *  interrupt handler invokes the executive.]  When not inlined
80 *  something calls _Thread_Enable_dispatch which in turns calls
81 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
82 *  one subroutine call is avoided entirely.]
83 */
84
85#define CPU_INLINE_ENABLE_DISPATCH       TRUE
86
87/*
88 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
89 *  be unrolled one time?  In unrolled each iteration of the loop examines
90 *  two "nodes" on the chain being searched.  Otherwise, only one node
91 *  is examined per iteration.
92 *
93 *  If TRUE, then the loops are unrolled.
94 *  If FALSE, then the loops are not unrolled.
95 *
96 *  The primary factor in making this decision is the cost of disabling
97 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
98 *  body of the loop.  On some CPUs, the flash is more expensive than
99 *  one iteration of the loop body.  In this case, it might be desirable
100 *  to unroll the loop.  It is important to note that on some CPUs, this
101 *  code is the longest interrupt disable period in RTEMS.  So it is
102 *  necessary to strike a balance when setting this parameter.
103 */
104
105#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
106
107/*
108 *  Does RTEMS manage a dedicated interrupt stack in software?
109 *
110 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
111 *  If FALSE, nothing is done.
112 *
113 *  If the CPU supports a dedicated interrupt stack in hardware,
114 *  then it is generally the responsibility of the BSP to allocate it
115 *  and set it up.
116 *
117 *  If the CPU does not support a dedicated interrupt stack, then
118 *  the porter has two options: (1) execute interrupts on the
119 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
120 *  interrupt stack.
121 *
122 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
123 *
124 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
125 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
126 *  possible that both are FALSE for a particular CPU.  Although it
127 *  is unclear what that would imply about the interrupt processing
128 *  procedure on that CPU.
129 */
130
131#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
132
133/*
134 *  Does this CPU have hardware support for a dedicated interrupt stack?
135 *
136 *  If TRUE, then it must be installed during initialization.
137 *  If FALSE, then no installation is performed.
138 *
139 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
140 *
141 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
142 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
143 *  possible that both are FALSE for a particular CPU.  Although it
144 *  is unclear what that would imply about the interrupt processing
145 *  procedure on that CPU.
146 */
147
148#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
149
150/*
151 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
152 *
153 *  If TRUE, then the memory is allocated during initialization.
154 *  If FALSE, then the memory is allocated during initialization.
155 *
156 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
157 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
158 */
159
160#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
161
162/*
163 *  Does the CPU have hardware floating point?
164 *
165 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
166 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
167 *
168 *  If there is a FP coprocessor such as the i387 or mc68881, then
169 *  the answer is TRUE.
170 *
171 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
172 *  It indicates whether or not this CPU model has FP support.  For
173 *  example, it would be possible to have an i386_nofp CPU model
174 *  which set this to false to indicate that you have an i386 without
175 *  an i387 and wish to leave floating point support out of RTEMS.
176 */
177
178#if ( A29K_HAS_FPU == 1 )
179#define CPU_HARDWARE_FP     TRUE
180#else
181#define CPU_HARDWARE_FP     FALSE
182#endif
183
184/*
185 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
186 *
187 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
188 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
189 *
190 *  So far, the only CPU in which this option has been used is the
191 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
192 *  floating point registers to perform integer multiplies.  If
193 *  a function which you would not think utilize the FP unit DOES,
194 *  then one can not easily predict which tasks will use the FP hardware.
195 *  In this case, this option should be TRUE.
196 *
197 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
198 */
199
200#define CPU_ALL_TASKS_ARE_FP     FALSE
201
202/*
203 *  Should the IDLE task have a floating point context?
204 *
205 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
206 *  and it has a floating point context which is switched in and out.
207 *  If FALSE, then the IDLE task does not have a floating point context.
208 *
209 *  Setting this to TRUE negatively impacts the time required to preempt
210 *  the IDLE task from an interrupt because the floating point context
211 *  must be saved as part of the preemption.
212 */
213
214#define CPU_IDLE_TASK_IS_FP      FALSE
215
216/*
217 *  Should the saving of the floating point registers be deferred
218 *  until a context switch is made to another different floating point
219 *  task?
220 *
221 *  If TRUE, then the floating point context will not be stored until
222 *  necessary.  It will remain in the floating point registers and not
223 *  disturned until another floating point task is switched to.
224 *
225 *  If FALSE, then the floating point context is saved when a floating
226 *  point task is switched out and restored when the next floating point
227 *  task is restored.  The state of the floating point registers between
228 *  those two operations is not specified.
229 *
230 *  If the floating point context does NOT have to be saved as part of
231 *  interrupt dispatching, then it should be safe to set this to TRUE.
232 *
233 *  Setting this flag to TRUE results in using a different algorithm
234 *  for deciding when to save and restore the floating point context.
235 *  The deferred FP switch algorithm minimizes the number of times
236 *  the FP context is saved and restored.  The FP context is not saved
237 *  until a context switch is made to another, different FP task.
238 *  Thus in a system with only one FP task, the FP context will never
239 *  be saved or restored.
240 */
241
242#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
243
244/*
245 *  Does this port provide a CPU dependent IDLE task implementation?
246 *
247 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
248 *  must be provided and is the default IDLE thread body instead of
249 *  _Internal_threads_Idle_thread_body.
250 *
251 *  If FALSE, then use the generic IDLE thread body if the BSP does
252 *  not provide one.
253 *
254 *  This is intended to allow for supporting processors which have
255 *  a low power or idle mode.  When the IDLE thread is executed, then
256 *  the CPU can be powered down.
257 *
258 *  The order of precedence for selecting the IDLE thread body is:
259 *
260 *    1.  BSP provided
261 *    2.  CPU dependent (if provided)
262 *    3.  generic (if no BSP and no CPU dependent)
263 */
264
265#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
266
267/*
268 *  Does the stack grow up (toward higher addresses) or down
269 *  (toward lower addresses)?
270 *
271 *  If TRUE, then the grows upward.
272 *  If FALSE, then the grows toward smaller addresses.
273 */
274
275#define CPU_STACK_GROWS_UP               FALSE
276
277/*
278 *  The following is the variable attribute used to force alignment
279 *  of critical RTEMS structures.  On some processors it may make
280 *  sense to have these aligned on tighter boundaries than
281 *  the minimum requirements of the compiler in order to have as
282 *  much of the critical data area as possible in a cache line.
283 *
284 *  The placement of this macro in the declaration of the variables
285 *  is based on the syntactically requirements of the GNU C
286 *  "__attribute__" extension.  For example with GNU C, use
287 *  the following to force a structures to a 32 byte boundary.
288 *
289 *      __attribute__ ((aligned (32)))
290 *
291 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
292 *         To benefit from using this, the data must be heavily
293 *         used so it will stay in the cache and used frequently enough
294 *         in the executive to justify turning this on.
295 */
296
297#define CPU_STRUCTURE_ALIGNMENT
298
299/*
300 *  The following defines the number of bits actually used in the
301 *  interrupt field of the task mode.  How those bits map to the
302 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
303 */
304
305#define CPU_MODES_INTERRUPT_MASK   0x00000001
306
307/*
308 *  Processor defined structures
309 *
310 *  Examples structures include the descriptor tables from the i386
311 *  and the processor control structure on the i960ca.
312 */
313
314/* may need to put some structures here.  */
315
316/*
317 * Contexts
318 *
319 *  Generally there are 2 types of context to save.
320 *     1. Interrupt registers to save
321 *     2. Task level registers to save
322 *
323 *  This means we have the following 3 context items:
324 *     1. task level context stuff::  Context_Control
325 *     2. floating point task stuff:: Context_Control_fp
326 *     3. special interrupt level context :: Context_Control_interrupt
327 *
328 *  On some processors, it is cost-effective to save only the callee
329 *  preserved registers during a task context switch.  This means
330 *  that the ISR code needs to save those registers which do not
331 *  persist across function calls.  It is not mandatory to make this
332 *  distinctions between the caller/callee saves registers for the
333 *  purpose of minimizing context saved during task switch and on interrupts.
334 *  If the cost of saving extra registers is minimal, simplicity is the
335 *  choice.  Save the same context on interrupt entry as for tasks in
336 *  this case.
337 *
338 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
339 *  care should be used in designing the context area.
340 *
341 *  On some CPUs with hardware floating point support, the Context_Control_fp
342 *  structure will not be used or it simply consist of an array of a
343 *  fixed number of bytes.   This is done when the floating point context
344 *  is dumped by a "FP save context" type instruction and the format
345 *  is not really defined by the CPU.  In this case, there is no need
346 *  to figure out the exact format -- only the size.  Of course, although
347 *  this is enough information for RTEMS, it is probably not enough for
348 *  a debugger such as gdb.  But that is another problem.
349 */
350
351typedef struct {
352    unsigned32 signal;
353    unsigned32 gr1;
354    unsigned32 rab;
355    unsigned32 PC0;
356    unsigned32 PC1;
357    unsigned32 PC2;
358    unsigned32 CHA;
359    unsigned32 CHD;
360    unsigned32 CHC;
361    unsigned32 ALU;
362    unsigned32 OPS;
363    unsigned32 tav;
364    unsigned32 lr1;
365    unsigned32 rfb;
366    unsigned32 msp;
367
368    unsigned32 FPStat0;
369    unsigned32 FPStat1;
370    unsigned32 FPStat2;
371    unsigned32 IPA;
372    unsigned32 IPB;
373    unsigned32 IPC;
374    unsigned32 Q;
375
376    unsigned32 gr96;
377    unsigned32 gr97;
378    unsigned32 gr98;
379    unsigned32 gr99;
380    unsigned32 gr100;
381    unsigned32 gr101;
382    unsigned32 gr102;
383    unsigned32 gr103;
384    unsigned32 gr104;
385    unsigned32 gr105;
386    unsigned32 gr106;
387    unsigned32 gr107;
388    unsigned32 gr108;
389    unsigned32 gr109;
390    unsigned32 gr110;
391    unsigned32 gr111;
392
393    unsigned32 gr112;
394    unsigned32 gr113;
395    unsigned32 gr114;
396    unsigned32 gr115;
397
398    unsigned32 gr116;
399    unsigned32 gr117;
400    unsigned32 gr118;
401    unsigned32 gr119;
402    unsigned32 gr120;
403    unsigned32 gr121;
404    unsigned32 gr122;
405    unsigned32 gr123;
406    unsigned32 gr124;
407
408    unsigned32 local_count;
409
410    unsigned32 locals[128];
411} Context_Control;
412
413typedef struct {
414    double      some_float_register;
415} Context_Control_fp;
416
417typedef struct {
418    unsigned32 special_interrupt_register;
419} CPU_Interrupt_frame;
420
421
422/*
423 *  The following table contains the information required to configure
424 *  the XXX processor specific parameters.
425 *
426 *  NOTE: The interrupt_stack_size field is required if
427 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
428 *
429 *        The pretasking_hook, predriver_hook, and postdriver_hook,
430 *        and the do_zero_of_workspace fields are required on ALL CPUs.
431 */
432
433typedef struct {
434  void       (*pretasking_hook)( void );
435  void       (*predriver_hook)( void );
436  void       (*postdriver_hook)( void );
437  void       (*idle_task)( void );
438  boolean      do_zero_of_workspace;
439  unsigned32   interrupt_stack_size;
440  unsigned32   extra_system_initialization_stack;
441  unsigned32   some_other_cpu_dependent_info;
442}   rtems_cpu_table;
443
444/*
445 *  This variable is optional.  It is used on CPUs on which it is difficult
446 *  to generate an "uninitialized" FP context.  It is filled in by
447 *  _CPU_Initialize and copied into the task's FP context area during
448 *  _CPU_Context_Initialize.
449 */
450
451EXTERN Context_Control_fp  _CPU_Null_fp_context;
452
453/*
454 *  On some CPUs, RTEMS supports a software managed interrupt stack.
455 *  This stack is allocated by the Interrupt Manager and the switch
456 *  is performed in _ISR_Handler.  These variables contain pointers
457 *  to the lowest and highest addresses in the chunk of memory allocated
458 *  for the interrupt stack.  Since it is unknown whether the stack
459 *  grows up or down (in general), this give the CPU dependent
460 *  code the option of picking the version it wants to use.
461 *
462 *  NOTE: These two variables are required if the macro
463 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
464 */
465
466EXTERN void               *_CPU_Interrupt_stack_low;
467EXTERN void               *_CPU_Interrupt_stack_high;
468
469/*
470 *  With some compilation systems, it is difficult if not impossible to
471 *  call a high-level language routine from assembly language.  This
472 *  is especially true of commercial Ada compilers and name mangling
473 *  C++ ones.  This variable can be optionally defined by the CPU porter
474 *  and contains the address of the routine _Thread_Dispatch.  This
475 *  can make it easier to invoke that routine at the end of the interrupt
476 *  sequence (if a dispatch is necessary).
477 */
478
479EXTERN void           (*_CPU_Thread_dispatch_pointer)();
480
481/*
482 *  Nothing prevents the porter from declaring more CPU specific variables.
483 */
484
485/* XXX: if needed, put more variables here */
486
487/*
488 *  The size of the floating point context area.  On some CPUs this
489 *  will not be a "sizeof" because the format of the floating point
490 *  area is not defined -- only the size is.  This is usually on
491 *  CPUs with a "floating point save context" instruction.
492 */
493
494#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
495
496/*
497 *  Amount of extra stack (above minimum stack size) required by
498 *  system initialization thread.  Remember that in a multiprocessor
499 *  system the system intialization thread becomes the MP server thread.
500 */
501
502#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
503
504/*
505 *  This defines the number of entries in the ISR_Vector_table managed
506 *  by RTEMS.
507 */
508
509#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
510#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
511
512/*
513 *  Should be large enough to run all RTEMS tests.  This insures
514 *  that a "reasonable" small application should not have any problems.
515 */
516
517#define CPU_STACK_MINIMUM_SIZE          (8192)
518
519/*
520 *  CPU's worst alignment requirement for data types on a byte boundary.  This
521 *  alignment does not take into account the requirements for the stack.
522 */
523
524#define CPU_ALIGNMENT              4
525
526/*
527 *  This number corresponds to the byte alignment requirement for the
528 *  heap handler.  This alignment requirement may be stricter than that
529 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
530 *  common for the heap to follow the same alignment requirement as
531 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
532 *  then this should be set to CPU_ALIGNMENT.
533 *
534 *  NOTE:  This does not have to be a power of 2.  It does have to
535 *         be greater or equal to than CPU_ALIGNMENT.
536 */
537
538#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
539
540/*
541 *  This number corresponds to the byte alignment requirement for memory
542 *  buffers allocated by the partition manager.  This alignment requirement
543 *  may be stricter than that for the data types alignment specified by
544 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
545 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
546 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
547 *
548 *  NOTE:  This does not have to be a power of 2.  It does have to
549 *         be greater or equal to than CPU_ALIGNMENT.
550 */
551
552#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
553
554/*
555 *  This number corresponds to the byte alignment requirement for the
556 *  stack.  This alignment requirement may be stricter than that for the
557 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
558 *  is strict enough for the stack, then this should be set to 0.
559 *
560 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
561 */
562
563#define CPU_STACK_ALIGNMENT        0
564
565/* ISR handler macros */
566
567/*
568 *  Disable all interrupts for an RTEMS critical section.  The previous
569 *  level is returned in _level.
570 */
571
572#define _CPU_ISR_Disable( _isr_cookie ) \
573    do{ _isr_cookie = a29k_disable(); }while(0)
574
575/*
576 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
577 *  This indicates the end of an RTEMS critical section.  The parameter
578 *  _level is not modified.
579 */
580
581#define _CPU_ISR_Enable( _isr_cookie )  \
582      do{ a29k_enable(_isr_cookie) ; }while(0)
583
584/*
585 *  This temporarily restores the interrupt to _level before immediately
586 *  disabling them again.  This is used to divide long RTEMS critical
587 *  sections into two or more parts.  The parameter _level is not
588 * modified.
589 */
590
591#define _CPU_ISR_Flash( _isr_cookie ) \
592  do{ \
593     _CPU_ISR_Enable( _isr_cookie ); \
594     _CPU_ISR_Disable( _isr_cookie ); \
595  }while(0)
596
597/*
598 *  Map interrupt level in task mode onto the hardware that the CPU
599 *  actually provides.  Currently, interrupt levels which do not
600 *  map onto the CPU in a generic fashion are undefined.  Someday,
601 *  it would be nice if these were "mapped" by the application
602 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
603 *  8 - 255 would be available for bsp/application specific meaning.
604 *  This could be used to manage a programmable interrupt controller
605 *  via the rtems_task_mode directive.
606 */
607
608#define _CPU_ISR_Set_level( new_level ) \
609  do{ \
610    if ( new_level ) a29k_disable_all(); \
611    else a29k_enable_all(); \
612  }while(0);
613
614/* end of ISR handler macros */
615
616/* Context handler macros */
617
618extern void _CPU_Context_save(
619  Context_Control *new_context
620);
621
622/*
623 *  Initialize the context to a state suitable for starting a
624 *  task after a context restore operation.  Generally, this
625 *  involves:
626 *
627 *     - setting a starting address
628 *     - preparing the stack
629 *     - preparing the stack and frame pointers
630 *     - setting the proper interrupt level in the context
631 *     - initializing the floating point context
632 *
633 *  This routine generally does not set any unnecessary register
634 *  in the context.  The state of the "general data" registers is
635 *  undefined at task start time.
636 *
637 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
638 *        point thread.  This is typically only used on CPUs where the
639 *        FPU may be easily disabled by software such as on the SPARC
640 *        where the PSR contains an enable FPU bit.
641 */
642
643#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
644                                 _isr, _entry_point, _is_fp ) \
645  do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */           \
646      unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size);  \
647      unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \
648      _mem_stack_tmp &= ~(CPU_ALIGNMENT-1);                         \
649      _reg_stack_tmp &= ~(CPU_ALIGNMENT-1);                         \
650      _CPU_Context_save(_the_context);                              \
651      (_the_context)->msp = _mem_stack_tmp;           /* gr125 */   \
652      (_the_context)->lr1 =                                         \
653      (_the_context)->locals[1] =                                   \
654      (_the_context)->rfb = _reg_stack_tmp;           /* gr127 */   \
655      (_the_context)->gr1 = _reg_stack_tmp - 4 * 4;                 \
656      (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */   \
657      (_the_context)->local_count = 1-1;                            \
658      (_the_context)->PC1 = _entry_point;                           \
659      (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \
660      if (_isr) { (_the_context)->OPS |= (TD | DI); }               \
661      else                                                          \
662                { (_the_context)->OPS &= ~(TD | DI); }              \
663  }while(0)
664
665/*
666 *  This routine is responsible for somehow restarting the currently
667 *  executing task.  If you are lucky, then all that is necessary
668 *  is restoring the context.  Otherwise, there will need to be
669 *  a special assembly routine which does something special in this
670 *  case.  Context_Restore should work most of the time.  It will
671 *  not work if restarting self conflicts with the stack frame
672 *  assumptions of restoring a context.
673 */
674
675#define _CPU_Context_Restart_self( _the_context ) \
676   _CPU_Context_restore( (_the_context) )
677
678/*
679 *  The purpose of this macro is to allow the initial pointer into
680 *  a floating point context area (used to save the floating point
681 *  context) to be at an arbitrary place in the floating point
682 *  context area.
683 *
684 *  This is necessary because some FP units are designed to have
685 *  their context saved as a stack which grows into lower addresses.
686 *  Other FP units can be saved by simply moving registers into offsets
687 *  from the base of the context area.  Finally some FP units provide
688 *  a "dump context" instruction which could fill in from high to low
689 *  or low to high based on the whim of the CPU designers.
690 */
691
692#define _CPU_Context_Fp_start( _base, _offset ) \
693   ( (char *) (_base) + (_offset) )
694
695/*
696 *  This routine initializes the FP context area passed to it to.
697 *  There are a few standard ways in which to initialize the
698 *  floating point context.  The code included for this macro assumes
699 *  that this is a CPU in which a "initial" FP context was saved into
700 *  _CPU_Null_fp_context and it simply copies it to the destination
701 *  context passed to it.
702 *
703 *  Other models include (1) not doing anything, and (2) putting
704 *  a "null FP status word" in the correct place in the FP context.
705 */
706
707#define _CPU_Context_Initialize_fp( _destination ) \
708  do { \
709   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
710  } while(0)
711
712/* end of Context handler macros */
713
714/* Fatal Error manager macros */
715
716/*
717 *  This routine copies _error into a known place -- typically a stack
718 *  location or a register, optionally disables interrupts, and
719 *  halts/stops the CPU.
720 */
721
722#define _CPU_Fatal_halt( _error ) \
723        a29k_fatal_error(_error)
724
725/* end of Fatal Error manager macros */
726
727/* Bitfield handler macros */
728
729/*
730 *  This routine sets _output to the bit number of the first bit
731 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
732 *  This type may be either 16 or 32 bits wide although only the 16
733 *  least significant bits will be used.
734 *
735 *  There are a number of variables in using a "find first bit" type
736 *  instruction.
737 *
738 *    (1) What happens when run on a value of zero?
739 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
740 *    (3) The numbering may be zero or one based.
741 *    (4) The "find first bit" instruction may search from MSB or LSB.
742 *
743 *  RTEMS guarantees that (1) will never happen so it is not a concern.
744 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
745 *  _CPU_Priority_bits_index().  These three form a set of routines
746 *  which must logically operate together.  Bits in the _value are
747 *  set and cleared based on masks built by _CPU_Priority_mask().
748 *  The basic major and minor values calculated by _Priority_Major()
749 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
750 *  to properly range between the values returned by the "find first bit"
751 *  instruction.  This makes it possible for _Priority_Get_highest() to
752 *  calculate the major and directly index into the minor table.
753 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
754 *  is the first bit found.
755 *
756 *  This entire "find first bit" and mapping process depends heavily
757 *  on the manner in which a priority is broken into a major and minor
758 *  components with the major being the 4 MSB of a priority and minor
759 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
760 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
761 *  to the lowest priority.
762 *
763 *  If your CPU does not have a "find first bit" instruction, then
764 *  there are ways to make do without it.  Here are a handful of ways
765 *  to implement this in software:
766 *
767 *    - a series of 16 bit test instructions
768 *    - a "binary search using if's"
769 *    - _number = 0
770 *      if _value > 0x00ff
771 *        _value >>=8
772 *        _number = 8;
773 *
774 *      if _value > 0x0000f
775 *        _value >=8
776 *        _number += 4
777 *
778 *      _number += bit_set_table[ _value ]
779 *
780 *    where bit_set_table[ 16 ] has values which indicate the first
781 *      bit set
782 */
783
784#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
785#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
786
787#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
788
789#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
790  { \
791    (_output) = 0;   /* do something to prevent warnings */ \
792  }
793
794#endif
795
796/* end of Bitfield handler macros */
797
798/*
799 *  This routine builds the mask which corresponds to the bit fields
800 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
801 *  for that routine.
802 */
803
804#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
805
806#define _CPU_Priority_Mask( _bit_number ) \
807  ( 1 << (_bit_number) )
808
809#endif
810
811/*
812 *  This routine translates the bit numbers returned by
813 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
814 *  a major or minor component of a priority.  See the discussion
815 *  for that routine.
816 */
817
818#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
819
820#define _CPU_Priority_bits_index( _priority ) \
821  (_priority)
822
823#endif
824
825/* end of Priority handler macros */
826
827/* functions */
828
829/*
830 *  _CPU_Initialize
831 *
832 *  This routine performs CPU dependent initialization.
833 */
834
835void _CPU_Initialize(
836  rtems_cpu_table  *cpu_table,
837  void      (*thread_dispatch)()
838);
839
840/*
841 *  _CPU_ISR_install_raw_handler
842 *
843 *  This routine installs a "raw" interrupt handler directly into the
844 *  processor's vector table.
845 */
846 
847void _CPU_ISR_install_raw_handler(
848  unsigned32  vector,
849  proc_ptr    new_handler,
850  proc_ptr   *old_handler
851);
852
853/*
854 *  _CPU_ISR_install_vector
855 *
856 *  This routine installs an interrupt vector.
857 */
858
859void _CPU_ISR_install_vector(
860  unsigned32  vector,
861  proc_ptr    new_handler,
862  proc_ptr   *old_handler
863);
864
865/*
866 *  _CPU_Install_interrupt_stack
867 *
868 *  This routine installs the hardware interrupt stack pointer.
869 *
870 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
871 *         is TRUE.
872 */
873
874void _CPU_Install_interrupt_stack( void );
875
876/*
877 *  _CPU_Internal_threads_Idle_thread_body
878 *
879 *  This routine is the CPU dependent IDLE thread body.
880 *
881 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
882 *         is TRUE.
883 */
884
885void _CPU_Internal_threads_Idle_thread_body( void );
886
887/*
888 *  _CPU_Context_switch
889 *
890 *  This routine switches from the run context to the heir context.
891 */
892
893void _CPU_Context_switch(
894  Context_Control  *run,
895  Context_Control  *heir
896);
897
898/*
899 *  _CPU_Context_restore
900 *
901 *  This routine is generallu used only to restart self in an
902 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
903 *
904 *  NOTE: May be unnecessary to reload some registers.
905 */
906
907void _CPU_Context_restore(
908  Context_Control *new_context
909);
910
911/*
912 *  _CPU_Context_save_fp
913 *
914 *  This routine saves the floating point context passed to it.
915 */
916
917void _CPU_Context_save_fp(
918  void **fp_context_ptr
919);
920
921/*
922 *  _CPU_Context_restore_fp
923 *
924 *  This routine restores the floating point context passed to it.
925 */
926
927void _CPU_Context_restore_fp(
928  void **fp_context_ptr
929);
930
931/*  The following routine swaps the endian format of an unsigned int.
932 *  It must be static because it is referenced indirectly.
933 *
934 *  This version will work on any processor, but if there is a better
935 *  way for your CPU PLEASE use it.  The most common way to do this is to:
936 *
937 *     swap least significant two bytes with 16-bit rotate
938 *     swap upper and lower 16-bits
939 *     swap most significant two bytes with 16-bit rotate
940 *
941 *  Some CPUs have special instructions which swap a 32-bit quantity in
942 *  a single instruction (e.g. i486).  It is probably best to avoid
943 *  an "endian swapping control bit" in the CPU.  One good reason is
944 *  that interrupts would probably have to be disabled to insure that
945 *  an interrupt does not try to access the same "chunk" with the wrong
946 *  endian.  Another good reason is that on some CPUs, the endian bit
947 *  endianness for ALL fetches -- both code and data -- so the code
948 *  will be fetched incorrectly.
949 */
950 
951#define CPU_swap_u32( value ) \
952  ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | (((value >> 16)&0xff) << 8) | ((value>>24)&0xff)
953
954#ifdef __cplusplus
955}
956#endif
957
958#endif
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