1 | /* |
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2 | * AMD 29K CPU Dependent Source |
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3 | * |
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4 | * Author: Craig Lebakken <craigl@transition.com> |
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5 | * |
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6 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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7 | * |
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8 | * To anyone who acknowledges that this file is provided "AS IS" |
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9 | * without any express or implied warranty: |
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10 | * permission to use, copy, modify, and distribute this file |
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11 | * for any purpose is hereby granted without fee, provided that |
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12 | * the above copyright notice and this notice appears in all |
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13 | * copies, and that the name of Transition Networks not be used in |
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14 | * advertising or publicity pertaining to distribution of the |
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15 | * software without specific, written prior permission. |
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16 | * Transition Networks makes no representations about the suitability |
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17 | * of this software for any purpose. |
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18 | * |
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19 | * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: |
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20 | * |
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21 | * COPYRIGHT (c) 1989-1999. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * |
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24 | * The license and distribution terms for this file may be |
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25 | * found in the file LICENSE in this distribution or at |
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26 | * http://www.OARcorp.com/rtems/license.html. |
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27 | * |
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28 | * $Id$ |
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29 | */ |
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30 | #ifndef lint |
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31 | static char _sccsid[] = "@(#)cpu.c 10/21/96 1.8\n"; |
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32 | #endif |
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33 | |
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34 | #include <rtems/system.h> |
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35 | #include <rtems/score/isr.h> |
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36 | #include <rtems/score/wkspace.h> |
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37 | #include <rtems/score/thread.h> |
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38 | #include <stdio.h> |
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39 | #include <stdlib.h> |
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40 | |
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41 | void a29k_ISR_Handler(unsigned32 vector); |
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42 | |
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43 | /* _CPU_Initialize |
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44 | * |
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45 | * This routine performs processor dependent initialization. |
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46 | * |
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47 | * INPUT PARAMETERS: |
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48 | * cpu_table - CPU table to initialize |
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49 | * thread_dispatch - address of disptaching routine |
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50 | */ |
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51 | |
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52 | |
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53 | void _CPU_Initialize( |
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54 | rtems_cpu_table *cpu_table, |
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55 | void (*thread_dispatch)() /* ignored on this CPU */ |
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56 | ) |
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57 | { |
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58 | unsigned int i; |
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59 | /* |
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60 | * The thread_dispatch argument is the address of the entry point |
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61 | * for the routine called at the end of an ISR once it has been |
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62 | * decided a context switch is necessary. On some compilation |
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63 | * systems it is difficult to call a high-level language routine |
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64 | * from assembly. This allows us to trick these systems. |
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65 | * |
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66 | * If you encounter this problem save the entry point in a CPU |
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67 | * dependent variable. |
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68 | */ |
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69 | |
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70 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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71 | |
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72 | /* |
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73 | * If there is not an easy way to initialize the FP context |
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74 | * during Context_Initialize, then it is usually easier to |
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75 | * save an "uninitialized" FP context here and copy it to |
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76 | * the task's during Context_Initialize. |
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77 | */ |
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78 | |
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79 | /* FP context initialization support goes here */ |
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80 | |
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81 | _CPU_Table = *cpu_table; |
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82 | |
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83 | for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ ) |
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84 | { |
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85 | _ISR_Vector_table[i] = (proc_ptr)NULL; |
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86 | } |
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87 | } |
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88 | |
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89 | /*PAGE |
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90 | * |
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91 | * _CPU_ISR_Get_level |
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92 | */ |
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93 | |
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94 | unsigned32 _CPU_ISR_Get_level( void ) |
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95 | { |
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96 | unsigned32 cps; |
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97 | |
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98 | /* |
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99 | * This routine returns the current interrupt level. |
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100 | */ |
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101 | cps = a29k_getops(); |
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102 | if (cps & (TD|DI)) |
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103 | return 1; |
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104 | else |
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105 | return 0; |
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106 | } |
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107 | |
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108 | /*PAGE |
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109 | * |
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110 | * _CPU_ISR_install_raw_handler |
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111 | */ |
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112 | |
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113 | extern void intr14( void ); |
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114 | extern void intr18( void ); |
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115 | extern void intr19( void ); |
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116 | |
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117 | /* just to link with GNU tools JRS 09/22/2000 */ |
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118 | asm (".global V_SPILL, V_FILL" ); |
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119 | asm (".global V_EPI_OS, V_BSD_OS" ); |
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120 | |
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121 | asm (".equ V_SPILL, 64" ); |
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122 | asm (".equ V_FILL, 65" ); |
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123 | |
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124 | asm (".equ V_BSD_OS, 66" ); |
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125 | asm (".equ V_EPI_OS, 69" ); |
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126 | |
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127 | /* end of just to link with GNU tools */ |
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128 | |
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129 | void _CPU_ISR_install_raw_handler( |
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130 | unsigned32 vector, |
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131 | proc_ptr new_handler, |
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132 | proc_ptr *old_handler |
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133 | ) |
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134 | { |
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135 | /* |
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136 | * This is where we install the interrupt handler into the "raw" interrupt |
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137 | * table used by the CPU to dispatch interrupt handlers. |
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138 | */ |
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139 | switch( vector ) |
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140 | { |
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141 | /* where is this code? JRS */ |
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142 | #if 0 |
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143 | case 14: |
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144 | _settrap( vector, intr14 ); |
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145 | break; |
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146 | case 18: |
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147 | _settrap( vector, intr18 ); |
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148 | break; |
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149 | case 19: |
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150 | _settrap( vector, intr19 ); |
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151 | break; |
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152 | #endif |
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153 | |
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154 | default: |
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155 | break; |
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156 | } |
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157 | } |
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158 | |
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159 | |
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160 | /*PAGE |
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161 | * |
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162 | * _CPU_ISR_install_vector |
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163 | * |
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164 | * This kernel routine installs the RTEMS handler for the |
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165 | * specified vector. |
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166 | * |
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167 | * Input parameters: |
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168 | * vector - interrupt vector number |
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169 | * old_handler - former ISR for this vector number |
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170 | * new_handler - replacement ISR for this vector number |
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171 | * |
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172 | * Output parameters: NONE |
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173 | * |
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174 | */ |
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175 | |
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176 | void _CPU_ISR_install_vector( |
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177 | unsigned32 vector, |
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178 | proc_ptr new_handler, |
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179 | proc_ptr *old_handler |
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180 | ) |
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181 | { |
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182 | *old_handler = _ISR_Vector_table[ vector ]; |
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183 | |
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184 | /* |
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185 | * If the interrupt vector table is a table of pointer to isr entry |
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186 | * points, then we need to install the appropriate RTEMS interrupt |
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187 | * handler for this vector number. |
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188 | */ |
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189 | |
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190 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
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191 | |
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192 | /* |
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193 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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194 | * be used by the _ISR_Handler so the user gets control. |
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195 | */ |
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196 | |
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197 | _ISR_Vector_table[ vector ] = new_handler; |
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198 | } |
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199 | |
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200 | /*PAGE |
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201 | * |
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202 | * _CPU_Install_interrupt_stack |
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203 | */ |
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204 | |
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205 | void _CPU_Install_interrupt_stack( void ) |
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206 | { |
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207 | } |
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208 | |
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209 | /*PAGE |
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210 | * |
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211 | * _CPU_Thread_Idle_body |
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212 | * |
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213 | * NOTES: |
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214 | * |
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215 | * 1. This is the same as the regular CPU independent algorithm. |
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216 | * |
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217 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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218 | * instruction, then don't forget to put it in an infinite loop. |
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219 | * |
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220 | * 3. Be warned. Some processors with onboard DMA have been known |
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221 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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222 | * also be a problem with other on-chip peripherals. So use this |
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223 | * hook with caution. |
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224 | */ |
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225 | |
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226 | void _CPU_Thread_Idle_body( void ) |
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227 | { |
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228 | |
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229 | for( ; ; ) |
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230 | { |
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231 | } |
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232 | /* insert your "halt" instruction here */ ; |
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233 | } |
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234 | |
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235 | void a29k_fatal_error( unsigned32 error ) |
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236 | { |
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237 | printf("\n\nfatal error %d, rebooting!!!\n",error ); |
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238 | exit(error); |
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239 | } |
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240 | |
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241 | /* |
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242 | * This discussion ignores a lot of the ugly details in a real |
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243 | * implementation such as saving enough registers/state to be |
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244 | * able to do something real. Keep in mind that the goal is |
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245 | * to invoke a user's ISR handler which is written in C and |
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246 | * uses a certain set of registers. |
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247 | * |
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248 | * Also note that the exact order is to a large extent flexible. |
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249 | * Hardware will dictate a sequence for a certain subset of |
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250 | * _ISR_Handler while requirements for setting |
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251 | */ |
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252 | |
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253 | /* |
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254 | * At entry to "common" _ISR_Handler, the vector number must be |
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255 | * available. On some CPUs the hardware puts either the vector |
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256 | * number or the offset into the vector table for this ISR in a |
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257 | * known place. If the hardware does not give us this information, |
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258 | * then the assembly portion of RTEMS for this port will contain |
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259 | * a set of distinct interrupt entry points which somehow place |
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260 | * the vector number in a known place (which is safe if another |
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261 | * interrupt nests this one) and branches to _ISR_Handler. |
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262 | * |
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263 | */ |
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264 | |
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265 | void a29k_ISR_Handler(unsigned32 vector) |
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266 | { |
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267 | _ISR_Nest_level++; |
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268 | _Thread_Dispatch_disable_level++; |
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269 | if ( _ISR_Vector_table[ vector ] ) |
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270 | (*_ISR_Vector_table[ vector ])( vector ); |
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271 | --_Thread_Dispatch_disable_level; |
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272 | --_ISR_Nest_level; |
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273 | if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level && |
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274 | (_Context_Switch_necessary || _ISR_Signals_to_thread_executing )) |
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275 | _Thread_Dispatch(); |
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276 | return; |
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277 | } |
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