source: rtems/c/src/exec/score/cpu/a29k/cpu.c @ 29d8227e

4.104.114.84.95
Last change on this file since 29d8227e was 29d8227e, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 2, 1996 at 7:48:29 PM

Updates from Derrick Ostertag <ostertag@…> to fix bug in
interrupt handling.

  • Property mode set to 100644
File size: 6.8 KB
Line 
1/*
2 *  AMD 29K CPU Dependent Source
3 *
4 *  Author:     Craig Lebakken <craigl@transition.com>
5 *
6 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Transition Networks not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      Transition Networks makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
22 *  On-Line Applications Research Corporation (OAR).
23 *  All rights assigned to U.S. Government, 1994.
24 *
25 *  This material may be reproduced by or for the U.S. Government pursuant
26 *  to the copyright license under the clause at DFARS 252.227-7013.  This
27 *  notice must appear in all copies of this file and its derivatives.
28 *
29 *  $Id$
30 */
31#ifndef lint
32static char _sccsid[] = "@(#)cpu.c 10/21/96     1.8\n";
33#endif
34
35#include <rtems/system.h>
36#include <rtems/score/isr.h>
37#include <rtems/score/wkspace.h>
38#include <rtems/score/thread.h>
39#include <stdio.h>
40#include <stdlib.h>
41
42void a29k_ISR_Handler(unsigned32 vector);
43
44/*  _CPU_Initialize
45 *
46 *  This routine performs processor dependent initialization.
47 *
48 *  INPUT PARAMETERS:
49 *    cpu_table       - CPU table to initialize
50 *    thread_dispatch - address of disptaching routine
51 */
52
53
54void _CPU_Initialize(
55  rtems_cpu_table  *cpu_table,
56  void      (*thread_dispatch)()      /* ignored on this CPU */
57)
58{
59  unsigned int i;
60  /*
61   *  The thread_dispatch argument is the address of the entry point
62   *  for the routine called at the end of an ISR once it has been
63   *  decided a context switch is necessary.  On some compilation
64   *  systems it is difficult to call a high-level language routine
65   *  from assembly.  This allows us to trick these systems.
66   *
67   *  If you encounter this problem save the entry point in a CPU
68   *  dependent variable.
69   */
70
71  _CPU_Thread_dispatch_pointer = thread_dispatch;
72
73  /*
74   *  If there is not an easy way to initialize the FP context
75   *  during Context_Initialize, then it is usually easier to
76   *  save an "uninitialized" FP context here and copy it to
77   *  the task's during Context_Initialize.
78   */
79
80  /* FP context initialization support goes here */
81
82  _CPU_Table = *cpu_table;
83
84  for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
85  {
86     _ISR_Vector_table[i] = (proc_ptr)NULL;
87  }
88}
89
90/*PAGE
91 *
92 *  _CPU_ISR_Get_level
93 */
94 
95unsigned32 _CPU_ISR_Get_level( void )
96{
97  unsigned32    cps;
98
99  /*
100   *  This routine returns the current interrupt level.
101   */
102  cps = a29k_getops();
103  if (cps & (TD|DI))
104    return 1;
105  else
106    return 0;
107}
108
109/*PAGE
110 *
111 *  _CPU_ISR_install_raw_handler
112 */
113 
114extern void intr14( void );
115extern void intr18( void );
116extern void intr19( void );
117
118void _CPU_ISR_install_raw_handler(
119  unsigned32  vector,
120  proc_ptr    new_handler,
121  proc_ptr   *old_handler
122)
123{
124  /*
125   *  This is where we install the interrupt handler into the "raw" interrupt
126   *  table used by the CPU to dispatch interrupt handlers.
127   */
128   switch( vector )
129   {
130      case 14:
131         _settrap( vector, intr14 );
132         break;
133      case 18:
134         _settrap( vector, intr18 );
135         break;
136      case 19:
137         _settrap( vector, intr19 );
138         break;
139
140      default:
141         break;
142   }
143}
144
145
146/*PAGE
147 *
148 *  _CPU_ISR_install_vector
149 *
150 *  This kernel routine installs the RTEMS handler for the
151 *  specified vector.
152 *
153 *  Input parameters:
154 *    vector      - interrupt vector number
155 *    old_handler - former ISR for this vector number
156 *    new_handler - replacement ISR for this vector number
157 *
158 *  Output parameters:  NONE
159 *
160 */
161
162void _CPU_ISR_install_vector(
163  unsigned32  vector,
164  proc_ptr    new_handler,
165  proc_ptr   *old_handler
166)
167{
168   *old_handler = _ISR_Vector_table[ vector ];
169
170   /*
171    *  If the interrupt vector table is a table of pointer to isr entry
172    *  points, then we need to install the appropriate RTEMS interrupt
173    *  handler for this vector number.
174    */
175
176   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
177
178   /*
179    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
180    *  be used by the _ISR_Handler so the user gets control.
181    */
182
183    _ISR_Vector_table[ vector ] = new_handler;
184}
185
186/*PAGE
187 *
188 *  _CPU_Install_interrupt_stack
189 */
190
191void _CPU_Install_interrupt_stack( void )
192{
193}
194
195/*PAGE
196 *
197 *  _CPU_Internal_threads_Idle_thread_body
198 *
199 *  NOTES:
200 *
201 *  1. This is the same as the regular CPU independent algorithm.
202 *
203 *  2. If you implement this using a "halt", "idle", or "shutdown"
204 *     instruction, then don't forget to put it in an infinite loop.
205 *
206 *  3. Be warned. Some processors with onboard DMA have been known
207 *     to stop the DMA if the CPU were put in IDLE mode.  This might
208 *     also be a problem with other on-chip peripherals.  So use this
209 *     hook with caution.
210 */
211
212void _CPU_Internal_threads_Idle_thread_body( void )
213{
214
215  for( ; ; )
216  {
217  }
218    /* insert your "halt" instruction here */ ;
219}
220
221void a29k_fatal_error( unsigned32 error )
222{
223   printf("\n\nfatal error %d, rebooting!!!\n",error );
224   exit(error);
225}
226
227   /*
228    *  This discussion ignores a lot of the ugly details in a real
229    *  implementation such as saving enough registers/state to be
230    *  able to do something real.  Keep in mind that the goal is
231    *  to invoke a user's ISR handler which is written in C and
232    *  uses a certain set of registers.
233    *
234    *  Also note that the exact order is to a large extent flexible.
235    *  Hardware will dictate a sequence for a certain subset of
236    *  _ISR_Handler while requirements for setting
237    */
238
239  /*
240   *  At entry to "common" _ISR_Handler, the vector number must be
241   *  available.  On some CPUs the hardware puts either the vector
242   *  number or the offset into the vector table for this ISR in a
243   *  known place.  If the hardware does not give us this information,
244   *  then the assembly portion of RTEMS for this port will contain
245   *  a set of distinct interrupt entry points which somehow place
246   *  the vector number in a known place (which is safe if another
247   *  interrupt nests this one) and branches to _ISR_Handler.
248   *
249   */
250
251void a29k_ISR_Handler(unsigned32 vector)
252{
253   _ISR_Nest_level++;
254   _Thread_Dispatch_disable_level++;
255   if ( _ISR_Vector_table[ vector ] )
256      (*_ISR_Vector_table[ vector ])( vector );
257   --_Thread_Dispatch_disable_level;
258   --_ISR_Nest_level;
259   if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level &&
260    (_Context_Switch_necessary || _ISR_Signals_to_thread_executing ))
261      _Thread_Dispatch();
262   return;
263}
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