source: rtems/c/src/exec/score/cpu/a29k/cpu.c @ 08311cc3

4.104.114.84.95
Last change on this file since 08311cc3 was 08311cc3, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 17, 1999 at 5:51:34 PM

Updated copyright notice.

  • Property mode set to 100644
File size: 6.7 KB
Line 
1/*
2 *  AMD 29K CPU Dependent Source
3 *
4 *  Author:     Craig Lebakken <craigl@transition.com>
5 *
6 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Transition Networks not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      Transition Networks makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1999.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *  $Id$
29 */
30#ifndef lint
31static char _sccsid[] = "@(#)cpu.c 10/21/96     1.8\n";
32#endif
33
34#include <rtems/system.h>
35#include <rtems/score/isr.h>
36#include <rtems/score/wkspace.h>
37#include <rtems/score/thread.h>
38#include <stdio.h>
39#include <stdlib.h>
40
41void a29k_ISR_Handler(unsigned32 vector);
42
43/*  _CPU_Initialize
44 *
45 *  This routine performs processor dependent initialization.
46 *
47 *  INPUT PARAMETERS:
48 *    cpu_table       - CPU table to initialize
49 *    thread_dispatch - address of disptaching routine
50 */
51
52
53void _CPU_Initialize(
54  rtems_cpu_table  *cpu_table,
55  void      (*thread_dispatch)()      /* ignored on this CPU */
56)
57{
58  unsigned int i;
59  /*
60   *  The thread_dispatch argument is the address of the entry point
61   *  for the routine called at the end of an ISR once it has been
62   *  decided a context switch is necessary.  On some compilation
63   *  systems it is difficult to call a high-level language routine
64   *  from assembly.  This allows us to trick these systems.
65   *
66   *  If you encounter this problem save the entry point in a CPU
67   *  dependent variable.
68   */
69
70  _CPU_Thread_dispatch_pointer = thread_dispatch;
71
72  /*
73   *  If there is not an easy way to initialize the FP context
74   *  during Context_Initialize, then it is usually easier to
75   *  save an "uninitialized" FP context here and copy it to
76   *  the task's during Context_Initialize.
77   */
78
79  /* FP context initialization support goes here */
80
81  _CPU_Table = *cpu_table;
82
83  for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
84  {
85     _ISR_Vector_table[i] = (proc_ptr)NULL;
86  }
87}
88
89/*PAGE
90 *
91 *  _CPU_ISR_Get_level
92 */
93 
94unsigned32 _CPU_ISR_Get_level( void )
95{
96  unsigned32    cps;
97
98  /*
99   *  This routine returns the current interrupt level.
100   */
101  cps = a29k_getops();
102  if (cps & (TD|DI))
103    return 1;
104  else
105    return 0;
106}
107
108/*PAGE
109 *
110 *  _CPU_ISR_install_raw_handler
111 */
112 
113extern void intr14( void );
114extern void intr18( void );
115extern void intr19( void );
116
117void _CPU_ISR_install_raw_handler(
118  unsigned32  vector,
119  proc_ptr    new_handler,
120  proc_ptr   *old_handler
121)
122{
123  /*
124   *  This is where we install the interrupt handler into the "raw" interrupt
125   *  table used by the CPU to dispatch interrupt handlers.
126   */
127   switch( vector )
128   {
129      case 14:
130         _settrap( vector, intr14 );
131         break;
132      case 18:
133         _settrap( vector, intr18 );
134         break;
135      case 19:
136         _settrap( vector, intr19 );
137         break;
138
139      default:
140         break;
141   }
142}
143
144
145/*PAGE
146 *
147 *  _CPU_ISR_install_vector
148 *
149 *  This kernel routine installs the RTEMS handler for the
150 *  specified vector.
151 *
152 *  Input parameters:
153 *    vector      - interrupt vector number
154 *    old_handler - former ISR for this vector number
155 *    new_handler - replacement ISR for this vector number
156 *
157 *  Output parameters:  NONE
158 *
159 */
160
161void _CPU_ISR_install_vector(
162  unsigned32  vector,
163  proc_ptr    new_handler,
164  proc_ptr   *old_handler
165)
166{
167   *old_handler = _ISR_Vector_table[ vector ];
168
169   /*
170    *  If the interrupt vector table is a table of pointer to isr entry
171    *  points, then we need to install the appropriate RTEMS interrupt
172    *  handler for this vector number.
173    */
174
175   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
176
177   /*
178    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
179    *  be used by the _ISR_Handler so the user gets control.
180    */
181
182    _ISR_Vector_table[ vector ] = new_handler;
183}
184
185/*PAGE
186 *
187 *  _CPU_Install_interrupt_stack
188 */
189
190void _CPU_Install_interrupt_stack( void )
191{
192}
193
194/*PAGE
195 *
196 *  _CPU_Internal_threads_Idle_thread_body
197 *
198 *  NOTES:
199 *
200 *  1. This is the same as the regular CPU independent algorithm.
201 *
202 *  2. If you implement this using a "halt", "idle", or "shutdown"
203 *     instruction, then don't forget to put it in an infinite loop.
204 *
205 *  3. Be warned. Some processors with onboard DMA have been known
206 *     to stop the DMA if the CPU were put in IDLE mode.  This might
207 *     also be a problem with other on-chip peripherals.  So use this
208 *     hook with caution.
209 */
210
211void _CPU_Internal_threads_Idle_thread_body( void )
212{
213
214  for( ; ; )
215  {
216  }
217    /* insert your "halt" instruction here */ ;
218}
219
220void a29k_fatal_error( unsigned32 error )
221{
222   printf("\n\nfatal error %d, rebooting!!!\n",error );
223   exit(error);
224}
225
226   /*
227    *  This discussion ignores a lot of the ugly details in a real
228    *  implementation such as saving enough registers/state to be
229    *  able to do something real.  Keep in mind that the goal is
230    *  to invoke a user's ISR handler which is written in C and
231    *  uses a certain set of registers.
232    *
233    *  Also note that the exact order is to a large extent flexible.
234    *  Hardware will dictate a sequence for a certain subset of
235    *  _ISR_Handler while requirements for setting
236    */
237
238  /*
239   *  At entry to "common" _ISR_Handler, the vector number must be
240   *  available.  On some CPUs the hardware puts either the vector
241   *  number or the offset into the vector table for this ISR in a
242   *  known place.  If the hardware does not give us this information,
243   *  then the assembly portion of RTEMS for this port will contain
244   *  a set of distinct interrupt entry points which somehow place
245   *  the vector number in a known place (which is safe if another
246   *  interrupt nests this one) and branches to _ISR_Handler.
247   *
248   */
249
250void a29k_ISR_Handler(unsigned32 vector)
251{
252   _ISR_Nest_level++;
253   _Thread_Dispatch_disable_level++;
254   if ( _ISR_Vector_table[ vector ] )
255      (*_ISR_Vector_table[ vector ])( vector );
256   --_Thread_Dispatch_disable_level;
257   --_ISR_Nest_level;
258   if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level &&
259    (_Context_Switch_necessary || _ISR_Signals_to_thread_executing ))
260      _Thread_Dispatch();
261   return;
262}
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