source: rtems/c/src/exec/rtems/src/cache.c @ 8ef3818

4.104.114.84.95
Last change on this file since 8ef3818 was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 12, 2000 at 7:57:02 PM

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

  • Property mode set to 100644
File size: 6.1 KB
Line 
1/*  cache.c
2 *
3 *  Cache Manager
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 * 
13 *  The functions in this file define the API to the RTEMS Cache Manager and
14 *  are divided into data cache and instruction cache functions. Data cache
15 *  functions are only declared if a data cache is supported. Instruction
16 *  cache functions are only declared if an instruction cache is supported.
17 *  Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is
18 *  defined, where x E {DATA, INST}. These definitions are found in the CPU
19 *  dependent source files in the supercore, often
20 * 
21 *  rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h
22 * 
23 *  The functions below are implemented with CPU dependent inline routines
24 *  also found in the above file. In the event that a CPU does not support a
25 *  specific function, the CPU dependent routine does nothing (but does exist).
26 * 
27 *  At this point, the Cache Manager makes no considerations, and provides no
28 *  support for BSP specific issues such as a secondary cache. In such a system,
29 *  the CPU dependent routines would have to be modified, or a BSP layer added
30 *  to this Manager.
31 */
32
33#include <rtems/system.h>
34#include <sys/types.h>
35#include <rtems/rtems/cache.h>
36
37
38/*
39 * THESE FUNCTIONS ONLY EXIST IF WE HAVE A DATA CACHE
40 */
41#if defined(_CPU_DATA_CACHE_ALIGNMENT)
42
43/*
44 * This function is called to flush the data cache by performing cache
45 * copybacks. It must determine how many cache lines need to be copied
46 * back and then perform the copybacks.
47 */
48void
49rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
50{
51    const void * final_address;
52   /*
53    * Set d_addr to the beginning of the cache line; final_address indicates
54    * the last address_t which needs to be pushed. Increment d_addr and push
55    * the resulting line until final_address is passed.
56    */
57    final_address = (void *)((size_t)d_addr + n_bytes - 1);
58    d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
59    while( d_addr <= final_address )  {
60        _CPU_flush_1_data_cache_line( d_addr );
61        d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
62    }
63}
64
65
66/*
67 * This function is responsible for performing a data cache invalidate.
68 * It must determine how many cache lines need to be invalidated and then
69 * perform the invalidations.
70 */
71void
72rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
73{
74    const void * final_address;
75   /*
76    * Set d_addr to the beginning of the cache line; final_address indicates
77    * the last address_t which needs to be invalidated. Increment d_addr and
78    * invalidate the resulting line until final_address is passed.
79    */
80    final_address = (void *)((size_t)d_addr + n_bytes - 1);
81    d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
82    while( final_address > d_addr ) {
83        _CPU_invalidate_1_data_cache_line( d_addr );
84        d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
85    }
86}
87
88
89/*
90 * This function is responsible for performing a data cache flush.
91 * It flushes the entire cache.
92 */
93void
94rtems_flush_entire_data_cache( void )
95{
96   /*
97    * Call the CPU-specific routine
98    */
99   _CPU_flush_entire_data_cache();
100     
101}
102
103
104/*
105 * This function is responsible for performing a data cache
106 * invalidate. It invalidates the entire cache.
107 */
108void
109rtems_invalidate_entire_data_cache( void )
110{
111   /*
112    * Call the CPU-specific routine
113    */
114   _CPU_invalidate_entire_data_cache();
115}
116
117
118/*
119 * This function returns the data cache granularity.
120 */
121int
122rtems_get_data_cache_line_size( void )
123{
124        return _CPU_DATA_CACHE_ALIGNMENT;
125}
126
127
128/*
129 * This function freezes the data cache; cache lines
130 * are not replaced.
131 */
132void
133rtems_freeze_data_cache( void )
134{
135        _CPU_freeze_data_cache();
136}
137
138
139/*
140 * This function unfreezes the instruction cache.
141 */
142void rtems_unfreeze_data_cache( void )
143{
144        _CPU_unfreeze_data_cache();
145}
146
147
148/* Turn on the data cache. */
149void
150rtems_enable_data_cache( void )
151{
152        _CPU_enable_data_cache();
153}
154
155
156/* Turn off the data cache. */
157void
158rtems_disable_data_cache( void )
159{
160        _CPU_disable_data_cache();
161}
162#endif
163
164
165
166/*
167 * THESE FUNCTIONS ONLY EXIST IF WE HAVE AN INSTRUCTION CACHE
168 */
169#if defined(_CPU_INST_CACHE_ALIGNMENT)
170
171/*
172 * This function is responsible for performing an instruction cache
173 * invalidate. It must determine how many cache lines need to be invalidated
174 * and then perform the invalidations.
175 */
176void
177rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes )
178{
179    const void * final_address;
180   /*
181    * Set i_addr to the beginning of the cache line; final_address indicates
182    * the last address_t which needs to be invalidated. Increment i_addr and
183    * invalidate the resulting line until final_address is passed.
184    */
185    final_address = (void *)((size_t)i_addr + n_bytes - 1);
186    i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
187    while( final_address > i_addr ) {
188        _CPU_invalidate_1_inst_cache_line( i_addr );
189        i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
190    }
191}
192
193
194/*
195 * This function is responsible for performing an instruction cache
196 * invalidate. It invalidates the entire cache.
197 */
198void
199rtems_invalidate_entire_inst_cache( void )
200{
201   /*
202    * Call the CPU-specific routine
203    */
204   _CPU_invalidate_entire_inst_cache();
205}
206
207
208/*
209 * This function returns the instruction cache granularity.
210 */
211int
212rtems_get_inst_cache_line_size( void )
213{
214        return _CPU_INST_CACHE_ALIGNMENT;
215}
216
217
218/*
219 * This function freezes the instruction cache; cache lines
220 * are not replaced.
221 */
222void
223rtems_freeze_inst_cache( void )
224{
225        _CPU_freeze_inst_cache();
226}
227
228
229/*
230 * This function unfreezes the instruction cache.
231 */
232void rtems_unfreeze_inst_cache( void )
233{
234        _CPU_unfreeze_inst_cache();
235}
236
237
238/* Turn on the instruction cache. */
239void
240rtems_enable_inst_cache( void )
241{
242        _CPU_enable_inst_cache();
243}
244
245
246/* Turn off the instruction cache. */
247void
248rtems_disable_inst_cache( void )
249{
250        _CPU_disable_inst_cache();
251}
252#endif
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