1 | /* |
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2 | * The license and distribution terms for this file may be |
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3 | * found in the file LICENSE in this distribution or at |
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4 | * http://www.OARcorp.com/rtems/license.html. |
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5 | * |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #ifndef __ITRON_SYSTEM_MANAGEMENT_h_ |
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10 | #define __ITRON_SYSTEM_MANAGEMENT_h_ |
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11 | |
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12 | #ifdef __cplusplus |
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13 | extern "C" { |
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14 | #endif |
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15 | |
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16 | /* |
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17 | * Get Version (get_ver) Structure |
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18 | */ |
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19 | |
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20 | typedef struct t_ver { |
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21 | UH maker; /* vendor */ |
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22 | UH id; /* format number */ |
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23 | UH spver; /* specification version */ |
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24 | UH prver; /* product version */ |
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25 | UH prno[4]; /* product control information */ |
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26 | UH cpu; /* CPU information */ |
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27 | UH var; /* variation descriptor */ |
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28 | } T_VER; |
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29 | |
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30 | /* |
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31 | * Specific MAKER codes established as of March, 1993 are as follows. |
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32 | * Due to restrictions on the assignment of CPU codes described below, it is |
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33 | * necessary to use maker codes in the range 0x000 through 0x00ff for vendors |
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34 | * developing CPUs. |
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35 | */ |
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36 | |
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37 | /* |
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38 | * CPU defines XXX need to name the constants |
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39 | */ |
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40 | |
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41 | #if 0 |
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42 | #define 0x000 /* No version (test systems, etc.) */ |
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43 | #define 0x001 /* University of Tokyo */ |
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44 | #define 0x009 /* FUJITSU LIMITED */ |
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45 | #define 0x00a /* Hitachi, Ltd. */ |
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46 | #define 0x00b /* Matsushita Electric Industrial Co., Ltd. */ |
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47 | #define 0x00c /* Mitsubishi Electric Corporation */ |
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48 | #define 0x00d /* NEC Corporation */ |
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49 | #define 0x00e /* Oki Electric Industry Co., Ltd. */ |
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50 | #define 0x00f /* TOSHIBA CORPORATION */ |
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51 | #endif |
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52 | |
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53 | /* |
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54 | * The above have been assigned in alphabetical order. |
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55 | */ |
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56 | |
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57 | #if 0 |
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58 | #define 0x010 /* ALPS ELECTRIC CO., LTD. */ |
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59 | #define 0x011 /* WACOM Co., Ltd. */ |
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60 | #define 0x012 /* Personal Media Corporation */ |
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61 | #define 0x101 /* OMRON CORPORATION */ |
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62 | #define 0x102 /* SEIKOSHA CO., LTD. */ |
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63 | #define 0x103 /* SYSTEM ALGO CO., LTD. */ |
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64 | #define 0x104 /* Tokyo Computer Service Co., Ltd. */ |
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65 | #define 0x105 /* YAMAHA CORPORATION */ |
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66 | #define 0x106 /* MORSON JAPAN */ |
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67 | #define 0x107 /* TOSHIBA INFORMATION SYSTEMS (JAPAN) CORP. */ |
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68 | #define 0x108 /* Miyazaki System Planning Office */ |
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69 | #define 0x109 /* Three Ace Computer Corporation */ |
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70 | #endif |
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71 | |
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72 | /* |
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73 | * CPU Codes |
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74 | * |
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75 | * Figure 47 shows the format of cpu code. Some processors use the format |
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76 | * given in Figure 47(1). The format given in Figure 47(2) is used for all |
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77 | * other proprietary processors. |
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78 | * |
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79 | * The code assignment of the CPU1 region in the format given in Figure 47(1) |
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80 | * is common to ITRON and BTRON specifications. The same number is used in |
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81 | * the CPU type of the standard object format of BTRON specification |
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82 | * operating systems implemented on a TRON-specification chip. |
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83 | * |
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84 | * When using the format given in Figure 47(2) the code used for MAKER1 is |
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85 | * assigned by using the lower 8 bits of MAKER described in the previous |
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86 | * subsection. The code assignment of CPU2 is left up to each maker. |
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87 | * |
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88 | * |
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89 | * |
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90 | * +---------------+---------------+---------------+---------------+ |
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91 | * (1) | 0 0 0 0 0 0 0 0 | CPU1 | |
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92 | * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |
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93 | * +---------------+---------------+---------------+---------------+ |
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94 | * (2) | MAKER1 | CPU2 | |
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95 | * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |
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96 | * |
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97 | * Figure 47 Format of cpu Returned by get_ver |
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98 | * |
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99 | * |
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100 | * Specific CPU codes established as of March, 1993 are as follows. |
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101 | */ |
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102 | |
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103 | #if 0 |
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104 | /* |
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105 | * XXX CONVERT THESE to #defines |
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106 | */ |
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107 | |
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108 | |
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109 | /* |
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110 | * Contents of the CPU1 field |
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111 | */ |
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112 | |
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113 | #define (0x0) CPU unspecified, no CPU information given |
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114 | #define (0x1) TRONCHIP32 shared |
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115 | #define (0x2) reserved |
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116 | #define (0x3) reserved |
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117 | #define (0x4) reserved |
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118 | #define (0x5) reserved (<<L1R>> TRON-specification chip) |
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119 | #define (0x6) reserved (<<L1>> TRON-specification chip) |
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120 | #define (0x7) reserved (TRON-specification chip supporting the |
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121 | LSID function) |
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122 | /* CPU vendors are unspecified for codes B'00000000 through B'00000111. */ |
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123 | |
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124 | #define (0x8) reserved |
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125 | #define (0x9) GMICRO/100 |
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126 | #define (0xa) GMICRO/200 |
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127 | #define (0xb) GMICRO/300 |
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128 | #define (0xc) reserved |
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129 | #define (0xd) TX1 |
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130 | #define (0xe) TX2 |
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131 | #define (0xf) reserved |
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132 | |
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133 | #define (0x10) reserved |
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134 | #define (0x11) reserved |
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135 | #define (0x12) reserved |
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136 | #define (0x13) O32 |
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137 | #define (0x14) reserved |
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138 | #define (0x15) MN10400 |
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139 | #define (0x16) reserved |
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140 | #define (0x17) reserved |
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141 | |
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142 | #define (0x18) GMICRO/400 |
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143 | #define (0x19) GMICRO/500 |
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144 | #define (0x1a) reserved |
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145 | #define (0x1b-0x3f) |
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146 | reserved |
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147 | * For GMICRO extended, TX series extended, and TRONCHIP64 chips. |
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148 | |
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149 | #define (0x40) Motorola 68000 |
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150 | #define (0x41) Motorola 68010 |
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151 | #define (0x42) Motorola 68020 |
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152 | #define (0x43) Motorola 68030 |
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153 | #define (0x44) Motorola 68040 |
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154 | #define -(0x40-0x4f) |
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155 | #define Motorola 68000 family |
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156 | #define (0x50) National Semiconductor NS32032 |
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157 | #define (0x50-0x5f) |
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158 | National Semiconductor NS32000 family |
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159 | #define (0x60) Intel 8086, 8088 |
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160 | #define (0x61) Intel 80186 |
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161 | #define (0x62) Intel 80286 |
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162 | #define (0x63) Intel 80386 |
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163 | #define (0x64) Intel 80486 |
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164 | #define (0x60-0x6f) |
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165 | Intel iAPX86 family |
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166 | |
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167 | #define (0x70-0x7f) |
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168 | NEC V Series |
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169 | |
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170 | #define (0x80-0xff) |
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171 | reserved |
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172 | #endif |
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173 | |
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174 | /* |
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175 | * Assigning Version Numbers |
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176 | * |
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177 | * The version numbers of ITRON and uITRON specifications take the following |
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178 | * form. |
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179 | * |
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180 | * Ver X.YY.ZZ[.WW] |
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181 | * |
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182 | * where "X" represents major version number of the ITRON specification to |
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183 | * distinguish ITRON1, ITRON2 and uITRON 3.0 specifications. Specific |
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184 | * assignment is as follows. |
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185 | * |
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186 | * "X" = 1 ITRON1 specification |
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187 | * = 2 ITRON2 or uITRON 2.0 specification |
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188 | * = 3 uITRON 3.0 specification |
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189 | * |
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190 | * "YY" is a number used to distinguish versions according to changes and |
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191 | * additions made to the specification. After the specification is published, |
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192 | * this number is incremented in order "YY" = 00, 01, 02... according to |
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193 | * version upgrades. The first digit of "YY" is 'A', 'B' or 'C' for draft |
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194 | * standard versions and test versions within the TRON Association before the |
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195 | * specification have been published. |
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196 | * |
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197 | * The "X.YY" part of the specification version numbers is returned by spver |
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198 | * to get_ver system call. The corresponding hexadecimal value is used when |
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199 | * "YY" includes 'A', 'B' or 'C'. |
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200 | * |
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201 | * "ZZ" represents a number used to distinguish versions related to the written |
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202 | * style of a specification. This number is incremented in order |
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203 | * "ZZ" = 00, 01, 02... when there have been changes in specification |
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204 | * configuration, reordering of chapters or corrections of misprints. |
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205 | * When a further distinction of the written style of specifications is |
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206 | * desired, ".WW" may be added optionally after "ZZ". WW will be assumed |
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207 | * to be zero if ".WW" is omitted. |
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208 | */ |
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209 | |
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210 | /* |
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211 | * Reference System (ref_sys) Structure |
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212 | */ |
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213 | |
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214 | typedef struct t_rsys { |
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215 | INT sysstat; /* system state */ |
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216 | /* additional information may be included depending on the implementation */ |
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217 | } T_RSYS; |
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218 | |
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219 | /* |
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220 | * sysstat |
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221 | */ |
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222 | |
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223 | #define TSS_TSK 0 /* normal state in which dispatching is enabled during |
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224 | task portion execution */ |
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225 | #define TSS_DDSP 1 /* state after dis_dsp has been executed during task |
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226 | portion execution (dispatch disabled) */ |
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227 | #define TSS_LOC 3 /* state after loc_cpu has been executed during task |
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228 | portion execution (interrupt and dispatch disabled) |
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229 | */ |
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230 | #define TSS_INDP 4 /* state during execution of task-independent portions |
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231 | (interrupt and timer handlers) */ |
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232 | |
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233 | /* |
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234 | * Reference Configuration (ref_cfg) Structure |
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235 | */ |
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236 | |
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237 | typedef struct t_rcfg { |
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238 | /* details concerning members are implementation dependent */ |
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239 | } T_RCFG; |
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240 | |
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241 | /* |
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242 | * Define Service (def_svc) Structure |
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243 | */ |
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244 | |
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245 | typedef struct t_dsvc { |
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246 | ATR svcatr; /* extended SVC handler attributes */ |
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247 | FP svchdr; /* extended SVC handler address */ |
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248 | /* additional information may be included depending on the implementation */ |
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249 | } T_DSVC; |
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250 | |
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251 | /* |
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252 | * Define Exception (def_exc) Structure |
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253 | */ |
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254 | |
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255 | typedef struct t_dexc { |
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256 | ATR excatr; /* exception handler attributes */ |
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257 | FP exchdr; /* exception handler address */ |
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258 | /* additional information may be included depending on the implementation */ |
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259 | } T_DEXC; |
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260 | |
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261 | /* |
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262 | * System Management Functions |
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263 | */ |
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264 | |
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265 | /* |
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266 | * get_ver - Get Version Information |
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267 | */ |
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268 | |
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269 | ER get_ver( |
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270 | T_VER *pk_ver |
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271 | ); |
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272 | |
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273 | /* |
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274 | * ref_sys - Reference Semaphore Status |
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275 | */ |
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276 | |
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277 | ER ref_sys( |
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278 | T_RSYS *pk_rsys |
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279 | ); |
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280 | |
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281 | /* |
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282 | * ref_cfg - Reference Configuration Information |
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283 | */ |
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284 | |
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285 | ER ref_cfg( |
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286 | T_RCFG *pk_rcfg |
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287 | ); |
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288 | |
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289 | /* |
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290 | * def_svc - Define Extended SVC Handler |
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291 | */ |
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292 | |
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293 | ER def_svc( |
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294 | FN s_fncd, |
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295 | T_DSVC *pk_dsvc |
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296 | ); |
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297 | |
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298 | /* |
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299 | * def_exc - Define Exception Handler |
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300 | */ |
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301 | |
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302 | ER def_exc( |
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303 | UINT exckind, |
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304 | T_DEXC *pk_dexc |
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305 | ); |
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306 | |
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307 | |
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308 | |
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309 | |
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310 | #ifdef __cplusplus |
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311 | } |
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312 | #endif |
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313 | |
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314 | #endif |
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315 | /* end of include file */ |
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316 | |
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