1 | /* |
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2 | * This file sets up page sizes to 1GiB (i.e. huge pages, using only the PML4 |
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3 | * and PDPT, skipping the PDT, and PT). |
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4 | * We set up identity-page mapping for the 512 GiBs addressable by using static |
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5 | * PML4 and PDPT tables. |
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6 | * |
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7 | * Section 4.5 "4-Level Paging" of Volume 3 of the Intel Software Developer |
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8 | * Manual guides a lot of the code used in this file. |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (c) 2018. |
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13 | * Amaan Cheval <amaan.cheval@gmail.com> |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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34 | * SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #include <stdio.h> |
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38 | #include <assert.h> |
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39 | #include <bsp.h> |
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40 | #include <rtems.h> |
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41 | #include <libcpu/page.h> |
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42 | #include <rtems/score/cpu.h> |
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43 | |
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44 | uint64_t amd64_pml4[NUM_PAGE_TABLE_ENTRIES] RTEMS_ALIGNED(4096); |
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45 | uint64_t amd64_pdpt[NUM_PAGE_TABLE_ENTRIES] RTEMS_ALIGNED(4096); |
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46 | |
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47 | bool paging_1gib_pages_supported(void) |
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48 | { |
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49 | /* |
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50 | * If CPUID.80000001H:EDX.Page1GB [bit 26] = 1, 1-GByte pages are supported |
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51 | * with 4-level paging. |
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52 | */ |
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53 | uint32_t a, b, c, d; |
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54 | cpuid(0x80000001, &a, &b, &c, &d); |
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55 | return (d >> 26) & 1; |
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56 | } |
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57 | |
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58 | uint8_t get_maxphysaddr(void) |
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59 | { |
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60 | /* |
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61 | * CPUID.80000008H:EAX[15:8] reports the linear-address width supported by the |
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62 | * processor. Generally, this value is 48 if CPUID.80000001H:EDX.LM [bit 29] = |
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63 | * 1 and 32 otherwise. |
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64 | */ |
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65 | uint32_t a, b, c, d; |
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66 | cpuid(0x80000008, &a, &b, &c, &d); |
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67 | |
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68 | uint8_t maxphysaddr = (a >> 8) & 0xff; |
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69 | /* This width is referred to as MAXPHYADDR. MAXPHYADDR is at most 52. */ |
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70 | assert(maxphysaddr <= 52); |
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71 | |
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72 | return maxphysaddr; |
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73 | } |
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74 | |
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75 | uint64_t get_mask_for_bits(uint8_t start, uint8_t end) |
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76 | { |
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77 | /* |
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78 | * Create a mask that lets you select bits start:end when logically ANDed with |
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79 | * a value. For eg. |
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80 | * get_mask_for_bits(48, 64) = 0xffff000000000000 |
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81 | */ |
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82 | uint64_t mask = (((uint64_t) 1 << (end - start)) - 1) << start; |
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83 | return mask; |
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84 | } |
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85 | |
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86 | RTEMS_INLINE_ROUTINE void assert_0s_from_bit(uint64_t entry, uint8_t bit_pos) |
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87 | { |
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88 | /* Confirm that bit_pos:64 are all 0s */ |
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89 | assert((entry & get_mask_for_bits(bit_pos, 64)) == 0); |
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90 | } |
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91 | |
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92 | uint64_t create_cr3_entry( |
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93 | uint64_t phys_addr, uint8_t maxphysaddr, uint64_t flags |
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94 | ) |
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95 | { |
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96 | /* Confirm PML4 address is aligned on a 4KiB boundary */ |
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97 | assert((phys_addr & 0xfff) == 0); |
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98 | uint64_t entry = (phys_addr & get_mask_for_bits(12, maxphysaddr)) | flags; |
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99 | |
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100 | /* Confirm that bits maxphysaddr:64 are 0s */ |
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101 | assert_0s_from_bit(entry, maxphysaddr); |
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102 | return entry; |
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103 | } |
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104 | |
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105 | uint64_t create_pml4_entry( |
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106 | uint64_t phys_addr, uint8_t maxphysaddr, uint64_t flags |
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107 | ) |
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108 | { |
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109 | /* Confirm address we're writing is aligned on a 4KiB boundary */ |
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110 | assert((phys_addr & 0xfff) == 0); |
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111 | uint64_t entry = (phys_addr & get_mask_for_bits(12, maxphysaddr)) | flags; |
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112 | |
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113 | /* |
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114 | * Confirm that bits maxphysaddr:64 are 0s; there are other usable bits there |
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115 | * such as PAGE_FLAGS_NO_EXECUTE, but we're asserting that those aren't set |
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116 | * either. |
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117 | */ |
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118 | assert_0s_from_bit(entry, maxphysaddr); |
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119 | return entry; |
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120 | } |
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121 | |
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122 | uint64_t create_pdpt_entry( |
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123 | uint64_t phys_addr, uint8_t maxphysaddr, uint64_t flags |
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124 | ) |
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125 | { |
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126 | /* Confirm physical address is a 1GiB aligned page address */ |
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127 | assert((phys_addr & 0x3fffffff) == 0); |
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128 | uint64_t entry = (phys_addr & get_mask_for_bits(30, maxphysaddr)) | flags; |
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129 | |
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130 | /* |
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131 | * Confirm that bits maxphysaddr:64 are 0s; there are other usable bits there |
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132 | * such as the protection key and PAGE_FLAGS_NO_EXECUTE, but we're asserting |
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133 | * that those aren't set either. |
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134 | */ |
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135 | assert_0s_from_bit(entry, maxphysaddr); |
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136 | return entry; |
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137 | } |
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138 | |
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139 | void paging_init(void) |
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140 | { |
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141 | if ( !paging_1gib_pages_supported() ) { |
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142 | printf("warning: 1 GiB pages aren't supported - trying anyway.\n"); |
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143 | } |
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144 | const uint8_t maxphysaddr = get_maxphysaddr(); |
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145 | DBG_PRINTF("maxphysaddr = %d\n", maxphysaddr); |
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146 | |
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147 | const uint64_t gib = (1 << 30); |
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148 | |
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149 | for (uint32_t i = 0; i < NUM_PAGE_TABLE_ENTRIES; i++) { |
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150 | amd64_pdpt[i] = create_pdpt_entry( |
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151 | /* This is the i-th GiB for identity-mapping */ |
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152 | (uint64_t) i * gib, |
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153 | maxphysaddr, |
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154 | /* Setting huge page in the PDPTE gives us 1 GiB pages */ |
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155 | PAGE_FLAGS_DEFAULTS | PAGE_FLAGS_HUGE_PAGE |
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156 | ); |
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157 | |
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158 | amd64_pml4[i] = create_pml4_entry( |
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159 | (uint64_t) amd64_pdpt, |
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160 | maxphysaddr, |
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161 | PAGE_FLAGS_DEFAULTS |
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162 | ); |
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163 | } |
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164 | |
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165 | amd64_set_cr3( |
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166 | create_cr3_entry( |
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167 | (uint64_t) &amd64_pml4, |
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168 | maxphysaddr, |
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169 | PAGE_FLAGS_WRITE_THROUGH |
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170 | ) |
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171 | ); |
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172 | } |
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