1 | /* |
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2 | * Copyright (c) 2018. |
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3 | * Amaan Cheval <amaan.cheval@gmail.com> |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | #include <stdint.h> |
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28 | #include <rtems.h> |
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29 | #include <rtems/score/idt.h> |
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30 | #include <rtems/score/basedefs.h> |
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31 | #include <rtems/score/x86_64.h> |
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32 | #include <rtems/score/cpuimpl.h> |
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33 | #include <bsp/irq-generic.h> |
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34 | |
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35 | /* |
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36 | * The IDT maps every interrupt vector to an interrupt_descriptor based on the |
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37 | * vector number. |
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38 | */ |
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39 | interrupt_descriptor amd64_idt[IDT_SIZE] RTEMS_ALIGNED(8) = { { 0 } }; |
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40 | |
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41 | struct idt_record idtr = { |
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42 | .limit = (IDT_SIZE * 16) - 1, |
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43 | .base = (uintptr_t) amd64_idt |
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44 | }; |
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45 | |
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46 | /** |
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47 | * IRQs that the RTEMS Interrupt Manager will manage |
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48 | * @see DISTINCT_INTERRUPT_ENTRY |
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49 | */ |
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50 | static uintptr_t rtemsIRQs[BSP_IRQ_VECTOR_NUMBER] = { |
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51 | (uintptr_t) rtems_irq_prologue_0, |
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52 | (uintptr_t) rtems_irq_prologue_1, |
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53 | (uintptr_t) rtems_irq_prologue_2, |
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54 | (uintptr_t) rtems_irq_prologue_3, |
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55 | (uintptr_t) rtems_irq_prologue_4, |
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56 | (uintptr_t) rtems_irq_prologue_5, |
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57 | (uintptr_t) rtems_irq_prologue_6, |
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58 | (uintptr_t) rtems_irq_prologue_7, |
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59 | (uintptr_t) rtems_irq_prologue_8, |
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60 | (uintptr_t) rtems_irq_prologue_9, |
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61 | (uintptr_t) rtems_irq_prologue_10, |
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62 | (uintptr_t) rtems_irq_prologue_11, |
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63 | (uintptr_t) rtems_irq_prologue_12, |
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64 | (uintptr_t) rtems_irq_prologue_13, |
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65 | (uintptr_t) rtems_irq_prologue_14, |
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66 | (uintptr_t) rtems_irq_prologue_15, |
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67 | (uintptr_t) rtems_irq_prologue_16, |
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68 | (uintptr_t) rtems_irq_prologue_17, |
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69 | (uintptr_t) rtems_irq_prologue_18, |
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70 | (uintptr_t) rtems_irq_prologue_19, |
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71 | (uintptr_t) rtems_irq_prologue_20, |
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72 | (uintptr_t) rtems_irq_prologue_21, |
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73 | (uintptr_t) rtems_irq_prologue_22, |
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74 | (uintptr_t) rtems_irq_prologue_23, |
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75 | (uintptr_t) rtems_irq_prologue_24, |
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76 | (uintptr_t) rtems_irq_prologue_25, |
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77 | (uintptr_t) rtems_irq_prologue_26, |
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78 | (uintptr_t) rtems_irq_prologue_27, |
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79 | (uintptr_t) rtems_irq_prologue_28, |
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80 | (uintptr_t) rtems_irq_prologue_29, |
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81 | (uintptr_t) rtems_irq_prologue_30, |
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82 | (uintptr_t) rtems_irq_prologue_31, |
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83 | (uintptr_t) rtems_irq_prologue_32 |
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84 | }; |
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85 | |
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86 | void lidt(struct idt_record *ptr) |
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87 | { |
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88 | __asm__ volatile ("lidt %0" :: "m"(*ptr)); |
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89 | } |
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90 | |
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91 | interrupt_descriptor amd64_create_interrupt_descriptor( |
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92 | uintptr_t handler, uint8_t types_and_attributes |
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93 | ) |
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94 | { |
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95 | interrupt_descriptor entry = { |
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96 | .offset_0 = handler & 0xffff, |
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97 | .segment_selector = amd64_get_cs(), |
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98 | .interrupt_stack_table = 0, |
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99 | .type_and_attributes = types_and_attributes, |
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100 | .offset_1 = (handler >> 16) & 0xffff, |
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101 | .offset_2 = handler >> 32, |
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102 | .reserved_zero = 0, |
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103 | }; |
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104 | return entry; |
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105 | } |
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106 | |
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107 | uintptr_t amd64_get_handler_from_idt(uint32_t vector) |
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108 | { |
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109 | interrupt_descriptor entry = amd64_idt[vector]; |
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110 | uintptr_t handler = entry.offset_0 | (entry.offset_1 << 16) | |
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111 | ((uint64_t) entry.offset_2 << 32); |
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112 | return handler; |
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113 | } |
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114 | |
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115 | void amd64_install_raw_interrupt( |
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116 | uint32_t vector, uintptr_t new_handler, uintptr_t *old_handler |
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117 | ) |
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118 | { |
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119 | *old_handler = amd64_get_handler_from_idt(vector); |
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120 | interrupt_descriptor new_desc = amd64_create_interrupt_descriptor( |
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121 | new_handler, |
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122 | IDT_INTERRUPT_GATE | IDT_PRESENT |
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123 | ); |
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124 | amd64_idt[vector] = new_desc; |
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125 | } |
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126 | |
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127 | void amd64_dispatch_isr(rtems_vector_number vector) |
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128 | { |
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129 | bsp_interrupt_handler_dispatch(vector); |
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130 | } |
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131 | |
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132 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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133 | { |
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134 | uintptr_t old; |
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135 | for (uint32_t i = 0; i < BSP_IRQ_VECTOR_NUMBER; i++) { |
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136 | amd64_install_raw_interrupt(i, rtemsIRQs[i], &old); |
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137 | } |
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138 | |
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139 | lidt(&idtr); |
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140 | |
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141 | return RTEMS_SUCCESSFUL; |
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142 | } |
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143 | |
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144 | void bsp_interrupt_vector_disable(rtems_vector_number vector) |
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145 | { |
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146 | /* XXX */ |
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147 | } |
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148 | void bsp_interrupt_vector_enable(rtems_vector_number vector) |
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149 | { |
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150 | /* XXX */ |
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151 | } |
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