| 1 | /* |
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| 2 | * Copyright (c) 2018. |
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| 3 | * Amaan Cheval <amaan.cheval@gmail.com> |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice, this list of conditions and the following disclaimer. |
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| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer in the |
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| 12 | * documentation and/or other materials provided with the distribution. |
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| 13 | * |
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| 14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 24 | * SUCH DAMAGE. |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef _AMD64_PIC_H |
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| 28 | #define _AMD64_PIC_H |
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| 29 | |
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| 30 | #ifdef __cplusplus |
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| 31 | extern "C" { |
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| 32 | #endif |
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| 33 | |
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| 34 | #define PIC1 0x20 /* IO base address for master PIC */ |
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| 35 | #define PIC2 0xA0 /* IO base address for slave PIC */ |
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| 36 | #define PIC1_COMMAND PIC1 |
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| 37 | #define PIC1_DATA (PIC1+1) |
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| 38 | #define PIC2_COMMAND PIC2 |
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| 39 | #define PIC2_DATA (PIC2+1) |
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| 40 | |
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| 41 | /* reinitialize the PIC controllers, giving them specified vector offsets |
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| 42 | rather than 8h and 70h, as configured by default */ |
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| 43 | |
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| 44 | #define PIC_ICW1_ICW4 0x01 /* ICW4 (not) needed */ |
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| 45 | #define PIC_ICW1_SINGLE 0x02 /* Single (cascade) mode */ |
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| 46 | #define PIC_ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */ |
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| 47 | #define PIC_ICW1_LEVEL 0x08 /* Level triggered (edge) mode */ |
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| 48 | #define PIC_ICW1_INIT 0x10 /* Initialization - required! */ |
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| 49 | |
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| 50 | #define PIC_ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */ |
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| 51 | #define PIC_ICW4_AUTO 0x02 /* Auto (normal) EOI */ |
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| 52 | #define PIC_ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */ |
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| 53 | #define PIC_ICW4_BUF_MASTER 0x0C /* Buffered mode/master */ |
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| 54 | #define PIC_ICW4_SFNM 0x10 /* Special fully nested (not) */ |
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| 55 | |
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| 56 | /* This remaps IRQ0 to vector number 0x20 and so on (i.e. IDT[32]) */ |
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| 57 | #define PIC1_REMAP_DEST 0x20 |
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| 58 | #define PIC2_REMAP_DEST 0x28 |
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| 59 | |
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| 60 | /* Remap PIC1's interrupts to offset1 and PIC2's to offset2 */ |
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| 61 | void pic_remap(uint8_t offset1, uint8_t offset2); |
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| 62 | |
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| 63 | /** |
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| 64 | * Mask all interrupt requests on PIC. |
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| 65 | * |
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| 66 | * @note Even with all interrupts masked, the PIC may still send spurious |
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| 67 | * interrupts (IRQ7), so we should handle them still. |
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| 68 | */ |
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| 69 | void pic_disable(void); |
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| 70 | |
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| 71 | #ifdef __cplusplus |
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| 72 | } |
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| 73 | #endif |
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| 74 | |
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| 75 | #endif /* _AMD64_PIC_H */ |
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