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README @ b82a4b4

Last change on this file since b82a4b4 was eb36d11, checked in by Sebastian Huber <sebastian.huber@…>, on 04/25/18 at 13:06:08

bsps: Move documentation, etc. files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

File size: 1.4 KB

Line
1	BSP NAME: niagara
2	BOARD:
3	BUS: n/a
4	CPU FAMILY: SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v)
5	CPU: UltraSPARC T1 (OpenSPARC T1)
6	COPROCESSORS:
7	MODE: n/a
8
9	DEBUG MONITOR:
10
11	PERIPHERALS
12	===========
13	TIMERS: TICK and STICK registers (ASRs 4 and 24)
14	RESOLUTION: CPU clock resolution
15	SERIAL PORTS:
16	REAL-TIME CLOCK:
17	DMA: none
18	VIDEO: none
19	SCSI: none
20	NETWORKING: none
21
22	DRIVER INFORMATION
23	==================
24	CLOCK DRIVER:
25	IOSUPP DRIVER:
26	SHMSUPP:
27	TIMER DRIVER:
28	TTY DRIVER:
29
30	STDIO
31	=====
32	PORT:
33	ELECTRICAL:
34	BAUD:
35	BITS PER CHARACTER:
36	PARITY:
37	STOP BITS:
38
39	NOTES
40	=====
41
42	Board description
43	-----------------
44	clock rate:
45	bus width:
46	ROM:
47	RAM:
48
49	This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64
50	and similar processors.
51
52	This BSP has been run on the Simics simulator with the niagara target, which
53	simulates the OpenSPARC T1 Niagara implementation.
54
55	This BSP has been run on the M5 simulator with the SPARC_FS target, which
56	simulates the OpenSPARC T1 Niagara implementation.
57
58	Simics:
59	A commercially available simulator licensed by Virtutech.
60	https://www.simics.net/
61
62	M5:
63	An open-source simulator.
64	http://www.m5sim.org/wiki/index.php/Main_Page
65

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