source: rtems/bsps/sparc64/niagara/README

Last change on this file was eb36d11, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 25, 2018 at 1:06:08 PM

bsps: Move documentation, etc. files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 1.4 KB
Line 
1BSP NAME:           niagara
2BOARD:             
3BUS:                n/a
4CPU FAMILY:         SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v)
5CPU:                UltraSPARC T1 (OpenSPARC T1)
6COPROCESSORS:       
7MODE:               n/a
8
9DEBUG MONITOR:     
10
11PERIPHERALS
12===========
13TIMERS:             TICK and STICK registers (ASRs 4 and 24)
14  RESOLUTION:         CPU clock resolution
15SERIAL PORTS:       
16REAL-TIME CLOCK:   
17DMA:                none
18VIDEO:              none
19SCSI:               none
20NETWORKING:         none
21
22DRIVER INFORMATION
23==================
24CLOCK DRIVER:       
25IOSUPP DRIVER:     
26SHMSUPP:           
27TIMER DRIVER:       
28TTY DRIVER:         
29
30STDIO
31=====
32PORT:               
33ELECTRICAL:         
34BAUD:               
35BITS PER CHARACTER:
36PARITY:             
37STOP BITS:         
38
39NOTES
40=====
41
42Board description
43-----------------
44clock rate:     
45bus width:     
46ROM:           
47RAM:           
48
49This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64
50and similar processors.
51
52This BSP has been run on the Simics simulator with the niagara target, which
53simulates the OpenSPARC T1 Niagara implementation.
54
55This BSP has been run on the M5 simulator with the SPARC_FS target, which
56simulates the OpenSPARC T1 Niagara implementation.
57
58Simics:
59A commercially available simulator licensed by Virtutech.
60https://www.simics.net/
61
62M5:
63An open-source simulator.
64http://www.m5sim.org/wiki/index.php/Main_Page
65
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