Last change
on this file was
eb36d11,
checked in by Sebastian Huber <sebastian.huber@…>, on 04/25/18 at 13:06:08
|
bsps: Move documentation, etc. files to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
|
-
Property mode set to
100644
|
File size:
1.4 KB
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Rev | Line | |
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[4d6f5f5] | 1 | BSP NAME: niagara |
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| 2 | BOARD: |
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| 3 | BUS: n/a |
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| 4 | CPU FAMILY: SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v) |
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| 5 | CPU: UltraSPARC T1 (OpenSPARC T1) |
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| 6 | COPROCESSORS: |
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| 7 | MODE: n/a |
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| 8 | |
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| 9 | DEBUG MONITOR: |
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| 10 | |
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| 11 | PERIPHERALS |
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| 12 | =========== |
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| 13 | TIMERS: TICK and STICK registers (ASRs 4 and 24) |
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| 14 | RESOLUTION: CPU clock resolution |
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| 15 | SERIAL PORTS: |
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| 16 | REAL-TIME CLOCK: |
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| 17 | DMA: none |
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| 18 | VIDEO: none |
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| 19 | SCSI: none |
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| 20 | NETWORKING: none |
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| 21 | |
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| 22 | DRIVER INFORMATION |
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| 23 | ================== |
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| 24 | CLOCK DRIVER: |
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| 25 | IOSUPP DRIVER: |
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| 26 | SHMSUPP: |
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| 27 | TIMER DRIVER: |
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| 28 | TTY DRIVER: |
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| 29 | |
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| 30 | STDIO |
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| 31 | ===== |
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| 32 | PORT: |
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| 33 | ELECTRICAL: |
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| 34 | BAUD: |
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| 35 | BITS PER CHARACTER: |
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| 36 | PARITY: |
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| 37 | STOP BITS: |
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| 38 | |
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| 39 | NOTES |
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| 40 | ===== |
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| 41 | |
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| 42 | Board description |
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| 43 | ----------------- |
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| 44 | clock rate: |
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| 45 | bus width: |
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| 46 | ROM: |
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| 47 | RAM: |
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| 48 | |
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| 49 | This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64 |
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| 50 | and similar processors. |
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| 51 | |
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| 52 | This BSP has been run on the Simics simulator with the niagara target, which |
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| 53 | simulates the OpenSPARC T1 Niagara implementation. |
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| 54 | |
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| 55 | This BSP has been run on the M5 simulator with the SPARC_FS target, which |
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| 56 | simulates the OpenSPARC T1 Niagara implementation. |
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| 57 | |
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| 58 | Simics: |
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| 59 | A commercially available simulator licensed by Virtutech. |
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| 60 | https://www.simics.net/ |
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| 61 | |
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| 62 | M5: |
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| 63 | An open-source simulator. |
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| 64 | http://www.m5sim.org/wiki/index.php/Main_Page |
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| 65 | |
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