1 | /* |
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2 | * Copyright (c) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | /** @addtogroup sparc64mm |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |
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35 | #ifndef KERN_sparc64_TLB_sun4u_H_ |
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36 | #define KERN_sparc64_TLB_sun4u_H_ |
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37 | |
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38 | #if defined (US) |
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39 | #define ITLB_ENTRY_COUNT 64 |
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40 | #define DTLB_ENTRY_COUNT 64 |
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41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
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42 | #endif |
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43 | |
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44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
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45 | #if defined (US3) |
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46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
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47 | #endif |
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48 | |
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49 | #define MEM_CONTEXT_KERNEL 0 |
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50 | #define MEM_CONTEXT_TEMP 1 |
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51 | |
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52 | /** Page sizes. */ |
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53 | #define PAGESIZE_8K 0 |
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54 | #define PAGESIZE_64K 1 |
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55 | #define PAGESIZE_512K 2 |
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56 | #define PAGESIZE_4M 3 |
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57 | |
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58 | /** Bit width of the TLB-locked portion of kernel address space. */ |
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59 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
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60 | |
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61 | /* TLB Demap Operation types. */ |
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62 | #define TLB_DEMAP_PAGE 0 |
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63 | #define TLB_DEMAP_CONTEXT 1 |
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64 | #if defined (US3) |
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65 | #define TLB_DEMAP_ALL 2 |
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66 | #endif |
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67 | |
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68 | #define TLB_DEMAP_TYPE_SHIFT 6 |
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69 | |
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70 | /* TLB Demap Operation Context register encodings. */ |
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71 | #define TLB_DEMAP_PRIMARY 0 |
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72 | #define TLB_DEMAP_SECONDARY 1 |
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73 | #define TLB_DEMAP_NUCLEUS 2 |
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74 | |
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75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
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76 | #if defined (US3) |
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77 | /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ |
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78 | #define TLB_DSMALL 0 |
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79 | #define TLB_DBIG_0 2 |
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80 | #define TLB_DBIG_1 3 |
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81 | |
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82 | /* I-MMU: one small (16-entry) TLB and one big TLB */ |
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83 | #define TLB_ISMALL 0 |
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84 | #define TLB_IBIG 2 |
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85 | #endif |
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86 | |
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87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
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88 | |
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89 | /* TLB Tag Access shifts */ |
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90 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
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91 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
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92 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
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93 | |
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94 | #ifndef __ASM__ |
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95 | |
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96 | #include <arch/mm/tte.h> |
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97 | #include <arch/mm/mmu.h> |
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98 | #include <arch/mm/page.h> |
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99 | #include <arch/asm.h> |
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100 | #include <arch/barrier.h> |
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101 | #include <arch/types.h> |
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102 | #include <arch/register.h> |
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103 | #include <arch/cpu.h> |
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104 | |
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105 | union tlb_context_reg { |
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106 | uint64_t v; |
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107 | struct { |
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108 | unsigned long : 51; |
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109 | unsigned context : 13; /**< Context/ASID. */ |
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110 | } __attribute__ ((packed)); |
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111 | }; |
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112 | typedef union tlb_context_reg tlb_context_reg_t; |
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113 | |
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114 | /** I-/D-TLB Data In/Access Register type. */ |
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115 | typedef tte_data_t tlb_data_t; |
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116 | |
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117 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
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118 | |
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119 | #if defined (US) |
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120 | |
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121 | union tlb_data_access_addr { |
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122 | uint64_t value; |
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123 | struct { |
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124 | uint64_t : 55; |
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125 | unsigned tlb_entry : 6; |
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126 | unsigned : 3; |
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127 | } __attribute__ ((packed)); |
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128 | }; |
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129 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
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130 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
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131 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
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132 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
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133 | |
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134 | #elif defined (US3) |
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135 | |
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136 | /* |
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137 | * In US3, I-MMU and D-MMU have different formats of the data |
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138 | * access register virtual address. In the corresponding |
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139 | * structures the member variable for the entry number is |
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140 | * called "local_tlb_entry" - it contrasts with the "tlb_entry" |
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141 | * for the US data access register VA structure. The rationale |
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142 | * behind this is to prevent careless mistakes in the code |
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143 | * caused by setting only the entry number and not the TLB |
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144 | * number in the US3 code (when taking the code from US). |
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145 | */ |
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146 | |
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147 | union dtlb_data_access_addr { |
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148 | uint64_t value; |
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149 | struct { |
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150 | uint64_t : 45; |
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151 | unsigned : 1; |
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152 | unsigned tlb_number : 2; |
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153 | unsigned : 4; |
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154 | unsigned local_tlb_entry : 9; |
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155 | unsigned : 3; |
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156 | } __attribute__ ((packed)); |
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157 | }; |
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158 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
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159 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
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160 | |
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161 | union itlb_data_access_addr { |
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162 | uint64_t value; |
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163 | struct { |
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164 | uint64_t : 45; |
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165 | unsigned : 1; |
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166 | unsigned tlb_number : 2; |
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167 | unsigned : 6; |
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168 | unsigned local_tlb_entry : 7; |
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169 | unsigned : 3; |
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170 | } __attribute__ ((packed)); |
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171 | }; |
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172 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
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173 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
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174 | |
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175 | #endif |
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176 | |
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177 | /** I-/D-TLB Tag Read Register. */ |
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178 | union tlb_tag_read_reg { |
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179 | uint64_t value; |
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180 | struct { |
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181 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
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182 | unsigned context : 13; /**< Context identifier. */ |
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183 | } __attribute__ ((packed)); |
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184 | }; |
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185 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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186 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
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187 | |
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188 | |
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189 | /** TLB Demap Operation Address. */ |
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190 | union tlb_demap_addr { |
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191 | uint64_t value; |
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192 | struct { |
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193 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
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194 | #if defined (US) |
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195 | unsigned : 6; /**< Ignored. */ |
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196 | unsigned type : 1; /**< The type of demap operation. */ |
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197 | #elif defined (US3) |
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198 | unsigned : 5; /**< Ignored. */ |
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199 | unsigned type: 2; /**< The type of demap operation. */ |
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200 | #endif |
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201 | unsigned context : 2; /**< Context register selection. */ |
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202 | unsigned : 4; /**< Zero. */ |
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203 | } __attribute__ ((packed)); |
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204 | }; |
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205 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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206 | |
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207 | /** TLB Synchronous Fault Status Register. */ |
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208 | union tlb_sfsr_reg { |
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209 | uint64_t value; |
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210 | struct { |
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211 | #if defined (US) |
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212 | unsigned long : 40; /**< Implementation dependent. */ |
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213 | unsigned asi : 8; /**< ASI. */ |
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214 | unsigned : 2; |
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215 | unsigned ft : 7; /**< Fault type. */ |
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216 | #elif defined (US3) |
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217 | unsigned long : 39; /**< Implementation dependent. */ |
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218 | unsigned nf : 1; /**< Non-faulting load. */ |
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219 | unsigned asi : 8; /**< ASI. */ |
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220 | unsigned tm : 1; /**< I-TLB miss. */ |
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221 | unsigned : 3; /**< Reserved. */ |
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222 | unsigned ft : 5; /**< Fault type. */ |
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223 | #endif |
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224 | unsigned e : 1; /**< Side-effect bit. */ |
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225 | unsigned ct : 2; /**< Context Register selection. */ |
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226 | unsigned pr : 1; /**< Privilege bit. */ |
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227 | unsigned w : 1; /**< Write bit. */ |
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228 | unsigned ow : 1; /**< Overwrite bit. */ |
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229 | unsigned fv : 1; /**< Fault Valid bit. */ |
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230 | } __attribute__ ((packed)); |
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231 | }; |
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232 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
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233 | |
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234 | #if defined (US3) |
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235 | |
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236 | /* |
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237 | * Functions for determining the number of entries in TLBs. They either return |
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238 | * a constant value or a value based on the CPU autodetection. |
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239 | */ |
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240 | |
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241 | /** |
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242 | * Determine the number of entries in the DMMU's small TLB. |
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243 | */ |
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244 | static inline uint16_t tlb_dsmall_size(void) |
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245 | { |
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246 | return 16; |
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247 | } |
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248 | |
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249 | /** |
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250 | * Determine the number of entries in each DMMU's big TLB. |
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251 | */ |
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252 | static inline uint16_t tlb_dbig_size(void) |
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253 | { |
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254 | return 512; |
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255 | } |
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256 | |
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257 | /** |
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258 | * Determine the number of entries in the IMMU's small TLB. |
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259 | */ |
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260 | static inline uint16_t tlb_ismall_size(void) |
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261 | { |
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262 | return 16; |
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263 | } |
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264 | |
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265 | /** |
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266 | * Determine the number of entries in the IMMU's big TLB. |
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267 | */ |
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268 | static inline uint16_t tlb_ibig_size(void) |
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269 | { |
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270 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
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271 | return 512; |
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272 | else |
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273 | return 128; |
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274 | } |
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275 | |
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276 | #endif |
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277 | |
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278 | /** Read MMU Primary Context Register. |
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279 | * |
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280 | * @return Current value of Primary Context Register. |
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281 | */ |
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282 | static inline uint64_t mmu_primary_context_read(void) |
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283 | { |
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284 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
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285 | } |
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286 | |
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287 | /** Write MMU Primary Context Register. |
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288 | * |
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289 | * @param v New value of Primary Context Register. |
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290 | */ |
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291 | static inline void mmu_primary_context_write(uint64_t v) |
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292 | { |
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293 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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294 | flush_pipeline(); |
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295 | } |
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296 | |
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297 | /** Read MMU Secondary Context Register. |
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298 | * |
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299 | * @return Current value of Secondary Context Register. |
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300 | */ |
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301 | static inline uint64_t mmu_secondary_context_read(void) |
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302 | { |
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303 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
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304 | } |
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305 | |
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306 | /** Write MMU Primary Context Register. |
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307 | * |
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308 | * @param v New value of Primary Context Register. |
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309 | */ |
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310 | static inline void mmu_secondary_context_write(uint64_t v) |
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311 | { |
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312 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
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313 | flush_pipeline(); |
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314 | } |
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315 | |
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316 | #if defined (US) |
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317 | |
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318 | /** Read IMMU TLB Data Access Register. |
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319 | * |
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320 | * @param entry TLB Entry index. |
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321 | * |
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322 | * @return Current value of specified IMMU TLB Data Access |
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323 | * Register. |
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324 | */ |
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325 | static inline uint64_t itlb_data_access_read(size_t entry) |
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326 | { |
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327 | itlb_data_access_addr_t reg; |
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328 | |
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329 | reg.value = 0; |
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330 | reg.tlb_entry = entry; |
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331 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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332 | } |
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333 | |
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334 | /** Write IMMU TLB Data Access Register. |
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335 | * |
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336 | * @param entry TLB Entry index. |
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337 | * @param value Value to be written. |
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338 | */ |
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339 | static inline void itlb_data_access_write(size_t entry, uint64_t value) |
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340 | { |
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341 | itlb_data_access_addr_t reg; |
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342 | |
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343 | reg.value = 0; |
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344 | reg.tlb_entry = entry; |
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345 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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346 | flush_pipeline(); |
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347 | } |
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348 | |
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349 | /** Read DMMU TLB Data Access Register. |
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350 | * |
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351 | * @param entry TLB Entry index. |
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352 | * |
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353 | * @return Current value of specified DMMU TLB Data Access |
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354 | * Register. |
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355 | */ |
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356 | static inline uint64_t dtlb_data_access_read(size_t entry) |
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357 | { |
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358 | dtlb_data_access_addr_t reg; |
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359 | |
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360 | reg.value = 0; |
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361 | reg.tlb_entry = entry; |
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362 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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363 | } |
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364 | |
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365 | /** Write DMMU TLB Data Access Register. |
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366 | * |
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367 | * @param entry TLB Entry index. |
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368 | * @param value Value to be written. |
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369 | */ |
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370 | static inline void dtlb_data_access_write(size_t entry, uint64_t value) |
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371 | { |
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372 | dtlb_data_access_addr_t reg; |
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373 | |
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374 | reg.value = 0; |
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375 | reg.tlb_entry = entry; |
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376 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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377 | membar(); |
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378 | } |
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379 | |
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380 | /** Read IMMU TLB Tag Read Register. |
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381 | * |
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382 | * @param entry TLB Entry index. |
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383 | * |
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384 | * @return Current value of specified IMMU TLB Tag Read Register. |
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385 | */ |
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386 | static inline uint64_t itlb_tag_read_read(size_t entry) |
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387 | { |
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388 | itlb_tag_read_addr_t tag; |
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389 | |
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390 | tag.value = 0; |
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391 | tag.tlb_entry = entry; |
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392 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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393 | } |
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394 | |
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395 | /** Read DMMU TLB Tag Read Register. |
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396 | * |
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397 | * @param entry TLB Entry index. |
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398 | * |
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399 | * @return Current value of specified DMMU TLB Tag Read Register. |
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400 | */ |
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401 | static inline uint64_t dtlb_tag_read_read(size_t entry) |
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402 | { |
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403 | dtlb_tag_read_addr_t tag; |
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404 | |
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405 | tag.value = 0; |
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406 | tag.tlb_entry = entry; |
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407 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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408 | } |
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409 | |
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410 | #elif defined (US3) |
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411 | |
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412 | |
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413 | /** Read IMMU TLB Data Access Register. |
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414 | * |
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415 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
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416 | * @param entry TLB Entry index. |
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417 | * |
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418 | * @return Current value of specified IMMU TLB Data Access |
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419 | * Register. |
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420 | */ |
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421 | static inline uint64_t itlb_data_access_read(int tlb, size_t entry) |
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422 | { |
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423 | itlb_data_access_addr_t reg; |
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424 | |
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425 | reg.value = 0; |
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426 | reg.tlb_number = tlb; |
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427 | reg.local_tlb_entry = entry; |
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428 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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429 | } |
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430 | |
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431 | /** Write IMMU TLB Data Access Register. |
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432 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
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433 | * @param entry TLB Entry index. |
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434 | * @param value Value to be written. |
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435 | */ |
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436 | static inline void itlb_data_access_write(int tlb, size_t entry, |
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437 | uint64_t value) |
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438 | { |
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439 | itlb_data_access_addr_t reg; |
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440 | |
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441 | reg.value = 0; |
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442 | reg.tlb_number = tlb; |
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443 | reg.local_tlb_entry = entry; |
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444 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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445 | flush_pipeline(); |
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446 | } |
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447 | |
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448 | /** Read DMMU TLB Data Access Register. |
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449 | * |
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450 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
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451 | * @param entry TLB Entry index. |
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452 | * |
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453 | * @return Current value of specified DMMU TLB Data Access |
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454 | * Register. |
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455 | */ |
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456 | static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) |
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457 | { |
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458 | dtlb_data_access_addr_t reg; |
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459 | |
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460 | reg.value = 0; |
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461 | reg.tlb_number = tlb; |
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462 | reg.local_tlb_entry = entry; |
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463 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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464 | } |
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465 | |
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466 | /** Write DMMU TLB Data Access Register. |
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467 | * |
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468 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
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469 | * @param entry TLB Entry index. |
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470 | * @param value Value to be written. |
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471 | */ |
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472 | static inline void dtlb_data_access_write(int tlb, size_t entry, |
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473 | uint64_t value) |
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474 | { |
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475 | dtlb_data_access_addr_t reg; |
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476 | |
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477 | reg.value = 0; |
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478 | reg.tlb_number = tlb; |
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479 | reg.local_tlb_entry = entry; |
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480 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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481 | membar(); |
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482 | } |
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483 | |
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484 | /** Read IMMU TLB Tag Read Register. |
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485 | * |
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486 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
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487 | * @param entry TLB Entry index. |
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488 | * |
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489 | * @return Current value of specified IMMU TLB Tag Read Register. |
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490 | */ |
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491 | static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) |
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492 | { |
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493 | itlb_tag_read_addr_t tag; |
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494 | |
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495 | tag.value = 0; |
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496 | tag.tlb_number = tlb; |
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497 | tag.local_tlb_entry = entry; |
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498 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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499 | } |
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500 | |
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501 | /** Read DMMU TLB Tag Read Register. |
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502 | * |
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503 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
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504 | * @param entry TLB Entry index. |
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505 | * |
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506 | * @return Current value of specified DMMU TLB Tag Read Register. |
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507 | */ |
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508 | static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) |
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509 | { |
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510 | dtlb_tag_read_addr_t tag; |
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511 | |
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512 | tag.value = 0; |
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513 | tag.tlb_number = tlb; |
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514 | tag.local_tlb_entry = entry; |
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515 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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516 | } |
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517 | |
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518 | #endif |
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519 | |
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520 | |
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521 | /** Write IMMU TLB Tag Access Register. |
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522 | * |
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523 | * @param v Value to be written. |
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524 | */ |
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525 | static inline void itlb_tag_access_write(uint64_t v) |
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526 | { |
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527 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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528 | flush_pipeline(); |
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529 | } |
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530 | |
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531 | /** Read IMMU TLB Tag Access Register. |
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532 | * |
---|
533 | * @return Current value of IMMU TLB Tag Access Register. |
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534 | */ |
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535 | static inline uint64_t itlb_tag_access_read(void) |
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536 | { |
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537 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
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538 | } |
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539 | |
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540 | /** Write DMMU TLB Tag Access Register. |
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541 | * |
---|
542 | * @param v Value to be written. |
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543 | */ |
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544 | static inline void dtlb_tag_access_write(uint64_t v) |
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545 | { |
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546 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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547 | membar(); |
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548 | } |
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549 | |
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550 | /** Read DMMU TLB Tag Access Register. |
---|
551 | * |
---|
552 | * @return Current value of DMMU TLB Tag Access Register. |
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553 | */ |
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554 | static inline uint64_t dtlb_tag_access_read(void) |
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555 | { |
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556 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
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557 | } |
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558 | |
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559 | |
---|
560 | /** Write IMMU TLB Data in Register. |
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561 | * |
---|
562 | * @param v Value to be written. |
---|
563 | */ |
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564 | static inline void itlb_data_in_write(uint64_t v) |
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565 | { |
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566 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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567 | flush_pipeline(); |
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568 | } |
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569 | |
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570 | /** Write DMMU TLB Data in Register. |
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571 | * |
---|
572 | * @param v Value to be written. |
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573 | */ |
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574 | static inline void dtlb_data_in_write(uint64_t v) |
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575 | { |
---|
576 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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577 | membar(); |
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578 | } |
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579 | |
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580 | /** Read ITLB Synchronous Fault Status Register. |
---|
581 | * |
---|
582 | * @return Current content of I-SFSR register. |
---|
583 | */ |
---|
584 | static inline uint64_t itlb_sfsr_read(void) |
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585 | { |
---|
586 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
---|
587 | } |
---|
588 | |
---|
589 | /** Write ITLB Synchronous Fault Status Register. |
---|
590 | * |
---|
591 | * @param v New value of I-SFSR register. |
---|
592 | */ |
---|
593 | static inline void itlb_sfsr_write(uint64_t v) |
---|
594 | { |
---|
595 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
---|
596 | flush_pipeline(); |
---|
597 | } |
---|
598 | |
---|
599 | /** Read DTLB Synchronous Fault Status Register. |
---|
600 | * |
---|
601 | * @return Current content of D-SFSR register. |
---|
602 | */ |
---|
603 | static inline uint64_t dtlb_sfsr_read(void) |
---|
604 | { |
---|
605 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
---|
606 | } |
---|
607 | |
---|
608 | /** Write DTLB Synchronous Fault Status Register. |
---|
609 | * |
---|
610 | * @param v New value of D-SFSR register. |
---|
611 | */ |
---|
612 | static inline void dtlb_sfsr_write(uint64_t v) |
---|
613 | { |
---|
614 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
---|
615 | membar(); |
---|
616 | } |
---|
617 | |
---|
618 | /** Read DTLB Synchronous Fault Address Register. |
---|
619 | * |
---|
620 | * @return Current content of D-SFAR register. |
---|
621 | */ |
---|
622 | static inline uint64_t dtlb_sfar_read(void) |
---|
623 | { |
---|
624 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
---|
625 | } |
---|
626 | |
---|
627 | /** Perform IMMU TLB Demap Operation. |
---|
628 | * |
---|
629 | * @param type Selects between context and page demap (and entire MMU |
---|
630 | * demap on US3). |
---|
631 | * @param context_encoding Specifies which Context register has Context ID for |
---|
632 | * demap. |
---|
633 | * @param page Address which is on the page to be demapped. |
---|
634 | */ |
---|
635 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
---|
636 | { |
---|
637 | tlb_demap_addr_t da; |
---|
638 | page_address_t pg; |
---|
639 | |
---|
640 | da.value = 0; |
---|
641 | pg.address = page; |
---|
642 | |
---|
643 | da.type = type; |
---|
644 | da.context = context_encoding; |
---|
645 | da.vpn = pg.vpn; |
---|
646 | |
---|
647 | /* da.value is the address within the ASI */ |
---|
648 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
---|
649 | |
---|
650 | flush_pipeline(); |
---|
651 | } |
---|
652 | |
---|
653 | /** Perform DMMU TLB Demap Operation. |
---|
654 | * |
---|
655 | * @param type Selects between context and page demap (and entire MMU |
---|
656 | * demap on US3). |
---|
657 | * @param context_encoding Specifies which Context register has Context ID for |
---|
658 | * demap. |
---|
659 | * @param page Address which is on the page to be demapped. |
---|
660 | */ |
---|
661 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
---|
662 | { |
---|
663 | tlb_demap_addr_t da; |
---|
664 | page_address_t pg; |
---|
665 | |
---|
666 | da.value = 0; |
---|
667 | pg.address = page; |
---|
668 | |
---|
669 | da.type = type; |
---|
670 | da.context = context_encoding; |
---|
671 | da.vpn = pg.vpn; |
---|
672 | |
---|
673 | /* da.value is the address within the ASI */ |
---|
674 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
---|
675 | |
---|
676 | membar(); |
---|
677 | } |
---|
678 | |
---|
679 | extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
---|
680 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); |
---|
681 | extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); |
---|
682 | |
---|
683 | extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
---|
684 | |
---|
685 | extern void dump_sfsr_and_sfar(void); |
---|
686 | extern void describe_dmmu_fault(void); |
---|
687 | |
---|
688 | #endif /* !def __ASM__ */ |
---|
689 | |
---|
690 | #endif |
---|
691 | |
---|
692 | /** @} |
---|
693 | */ |
---|