source: rtems/bsps/sparc64/include/arch/mm/sun4u/mmu.h @ a2aec0b7

5
Last change on this file since a2aec0b7 was 0a9b4513, checked in by Andreas Dachsberger <andreas.dachsberger@…>, on 04/01/19 at 10:22:37

doxygen: bsps: Added remaining Sparc64 groups
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1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 *   notice, this list of conditions and the following disclaimer in the
13 *   documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 *   derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup RTEMSBSPsSPARC64mm     
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_sparc64_sun4u_MMU_H_
36#define KERN_sparc64_sun4u_MMU_H_
37
38#if defined(US)
39/* LSU Control Register ASI. */
40#define ASI_LSU_CONTROL_REG             0x45    /**< Load/Store Unit Control Register. */
41#endif
42
43/* I-MMU ASIs. */
44#define ASI_IMMU                        0x50
45#define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
46#define ASI_IMMU_TSB_64KB_PTR_REG       0x52
47#define ASI_ITLB_DATA_IN_REG            0x54
48#define ASI_ITLB_DATA_ACCESS_REG        0x55
49#define ASI_ITLB_TAG_READ_REG           0x56
50#define ASI_IMMU_DEMAP                  0x57
51
52/* Virtual Addresses within ASI_IMMU. */
53#define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
54#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
55#define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
56#define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
57#if defined (US3)
58#define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
59#define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
60#endif
61
62
63/* D-MMU ASIs. */
64#define ASI_DMMU                        0x58
65#define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
66#define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
67#define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
68#define ASI_DTLB_DATA_IN_REG            0x5c
69#define ASI_DTLB_DATA_ACCESS_REG        0x5d
70#define ASI_DTLB_TAG_READ_REG           0x5e
71#define ASI_DMMU_DEMAP                  0x5f
72
73/* Virtual Addresses within ASI_DMMU. */
74#define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
75#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
76#define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
77#define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
78#define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
79#define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
80#define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
81#define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
82#define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
83#if defined (US3)
84#define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
85#define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
86#define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
87#endif
88
89#ifndef __ASM__
90
91#include <arch/asm.h>
92#include <arch/barrier.h>
93#include <arch/types.h>
94
95#if defined(US)
96/** LSU Control Register. */
97typedef union {
98        uint64_t value;
99        struct {
100                unsigned : 23;
101                unsigned pm : 8;
102                unsigned vm : 8;
103                unsigned pr : 1;
104                unsigned pw : 1;
105                unsigned vr : 1;
106                unsigned vw : 1;
107                unsigned : 1;
108                unsigned fm : 16;       
109                unsigned dm : 1;        /**< D-MMU enable. */
110                unsigned im : 1;        /**< I-MMU enable. */
111                unsigned dc : 1;        /**< D-Cache enable. */
112                unsigned ic : 1;        /**< I-Cache enable. */
113               
114        } __attribute__ ((packed));
115} lsu_cr_reg_t;
116#endif /* US */
117
118#endif /* !def __ASM__ */
119
120#endif
121
122/** @}
123 */
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