1 | /* L4STAT APB-Register Driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2017. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #include <rtems.h> |
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12 | #include <rtems/libio.h> |
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13 | #include <stdio.h> |
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14 | #include <bsp.h> |
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15 | #include <rtems/bspIo.h> /* printk */ |
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16 | |
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17 | #include <drvmgr/drvmgr.h> |
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18 | #include <grlib/ambapp_bus.h> |
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19 | #include <grlib/l4stat.h> |
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20 | |
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21 | /*#define STATIC*/ |
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22 | #define STATIC static |
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23 | |
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24 | /*#define DEBUG 1*/ |
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25 | |
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26 | #ifdef DEBUG |
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27 | #define DBG(x...) printf(x) |
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28 | #else |
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29 | #define DBG(x...) |
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30 | #endif |
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31 | |
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32 | #define REG_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (unsigned int)(val)) |
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33 | #define REG_READ(addr) (*(volatile unsigned int *)(addr)) |
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34 | |
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35 | |
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36 | /* |
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37 | * L4STAT CCTRL register fields |
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38 | * DEFINED IN HEADER file |
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39 | */ |
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40 | |
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41 | struct l4stat_regs { |
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42 | unsigned int cval[32]; /* 0x000 */ |
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43 | unsigned int cctrl[32]; /* 0x080 */ |
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44 | unsigned int cmax[32]; /* 0x100 */ |
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45 | unsigned int timestamp; /* 0x180 */ |
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46 | }; |
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47 | |
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48 | struct l4stat_priv { |
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49 | struct drvmgr_dev *dev; |
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50 | |
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51 | /* L4STAT control registers */ |
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52 | struct l4stat_regs *regs; |
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53 | |
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54 | /* L4STAT driver register */ |
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55 | char devname[9]; |
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56 | |
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57 | int ncpu; |
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58 | int ncnt; |
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59 | |
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60 | /* L4stat capabilities */ |
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61 | int max_count_support; |
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62 | int internalahb_event_support; |
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63 | int dsu_event_support; |
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64 | int external_event_support; |
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65 | int ahbtrace_event_support; |
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66 | }; |
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67 | |
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68 | STATIC struct l4stat_priv *l4statpriv = NULL; |
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69 | |
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70 | /* Event names */ |
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71 | #ifdef DEBUG |
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72 | #define L4STAT_BAD_CMD "N/A. Wrong event" |
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73 | STATIC const char *l4stat_event_names[] = { |
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74 | "Instruction cache miss", /* 0x00 */ |
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75 | "Instruction MMU TLB miss", /* 0x01 */ |
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76 | "Instruction cache hold", /* 0x02 */ |
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77 | "Instruction MMU hold", /* 0x03 */ |
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78 | L4STAT_BAD_CMD, /* 0x04 */ |
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79 | L4STAT_BAD_CMD, /* 0x05 */ |
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80 | L4STAT_BAD_CMD, /* 0x06 */ |
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81 | L4STAT_BAD_CMD, /* 0x07 */ |
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82 | "Data cache (read) miss", /* 0x08 */ |
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83 | "Data MMU TLB miss", /* 0x09 */ |
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84 | "Data cache hold", /* 0x0a */ |
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85 | "Data MMU hold", /* 0x0b */ |
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86 | L4STAT_BAD_CMD, /* 0x0c */ |
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87 | L4STAT_BAD_CMD, /* 0x0d */ |
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88 | L4STAT_BAD_CMD, /* 0x0e */ |
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89 | L4STAT_BAD_CMD, /* 0x0f */ |
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90 | "Data write buffer hold", /* 0x10 */ |
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91 | "Total instruction count", /* 0x11 */ |
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92 | "Integer instruction count", /* 0x12 */ |
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93 | "Floating-point unit instruction count", /* 0x13 */ |
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94 | "Branch prediction miss", /* 0x14 */ |
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95 | "Execution time, exluding debug mode", /* 0x15 */ |
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96 | L4STAT_BAD_CMD, /* 0x16 */ |
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97 | "AHB utilization (per AHB master)", /* 0x17 */ |
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98 | "AHB utilization (total)", /* 0x18 */ |
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99 | L4STAT_BAD_CMD, /* 0x19 */ |
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100 | L4STAT_BAD_CMD, /* 0x1a */ |
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101 | L4STAT_BAD_CMD, /* 0x1b */ |
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102 | L4STAT_BAD_CMD, /* 0x1c */ |
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103 | L4STAT_BAD_CMD, /* 0x1d */ |
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104 | L4STAT_BAD_CMD, /* 0x1e */ |
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105 | L4STAT_BAD_CMD, /* 0x1f */ |
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106 | L4STAT_BAD_CMD, /* 0x20 */ |
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107 | L4STAT_BAD_CMD, /* 0x21 */ |
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108 | "Integer branches", /* 0x22 */ |
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109 | L4STAT_BAD_CMD, /* 0x23 */ |
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110 | L4STAT_BAD_CMD, /* 0x24 */ |
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111 | L4STAT_BAD_CMD, /* 0x25 */ |
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112 | L4STAT_BAD_CMD, /* 0x26 */ |
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113 | L4STAT_BAD_CMD, /* 0x27 */ |
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114 | "CALL instructions", /* 0x28 */ |
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115 | L4STAT_BAD_CMD, /* 0x29 */ |
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116 | L4STAT_BAD_CMD, /* 0x2a */ |
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117 | L4STAT_BAD_CMD, /* 0x2b */ |
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118 | L4STAT_BAD_CMD, /* 0x2c */ |
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119 | L4STAT_BAD_CMD, /* 0x2d */ |
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120 | L4STAT_BAD_CMD, /* 0x2e */ |
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121 | L4STAT_BAD_CMD, /* 0x2f */ |
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122 | "Regular type 2 instructions", /* 0x30 */ |
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123 | L4STAT_BAD_CMD, /* 0x31 */ |
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124 | L4STAT_BAD_CMD, /* 0x32 */ |
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125 | L4STAT_BAD_CMD, /* 0x33 */ |
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126 | L4STAT_BAD_CMD, /* 0x34 */ |
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127 | L4STAT_BAD_CMD, /* 0x35 */ |
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128 | L4STAT_BAD_CMD, /* 0x36 */ |
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129 | L4STAT_BAD_CMD, /* 0x37 */ |
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130 | "LOAD and STORE instructions", /* 0x38 */ |
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131 | "LOAD instructions", /* 0x39 */ |
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132 | "STORE instructions", /* 0x3a */ |
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133 | L4STAT_BAD_CMD, /* 0x3b */ |
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134 | L4STAT_BAD_CMD, /* 0x3c */ |
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135 | L4STAT_BAD_CMD, /* 0x3d */ |
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136 | L4STAT_BAD_CMD, /* 0x3e */ |
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137 | L4STAT_BAD_CMD, /* 0x3f */ |
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138 | "AHB IDLE cycles", /* 0x40 */ |
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139 | "AHB BUSY cycles", /* 0x41 */ |
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140 | "AHB Non-Seq. transfers", /* 0x42 */ |
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141 | "AHB Seq. transfers", /* 0x43 */ |
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142 | "AHB read accesses", /* 0x44 */ |
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143 | "AHB write accesses", /* 0x45 */ |
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144 | "AHB byte accesses", /* 0x46 */ |
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145 | "AHB half-word accesses", /* 0x47 */ |
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146 | "AHB word accesses", /* 0x48 */ |
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147 | "AHB double word accesses", /* 0x49 */ |
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148 | "AHB quad word accesses", /* 0x4A */ |
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149 | "AHB eight word accesses", /* 0x4B */ |
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150 | "AHB waitstates", /* 0x4C */ |
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151 | "AHB RETRY responses", /* 0x4D */ |
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152 | "AHB SPLIT responses", /* 0x4E */ |
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153 | "AHB SPLIT delay", /* 0x4F */ |
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154 | "AHB bus locked", /* 0x50 */ |
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155 | L4STAT_BAD_CMD, /* 0x51 */ |
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156 | L4STAT_BAD_CMD, /* 0x52 */ |
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157 | L4STAT_BAD_CMD, /* 0x53 */ |
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158 | L4STAT_BAD_CMD, /* 0x54 */ |
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159 | L4STAT_BAD_CMD, /* 0x55 */ |
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160 | L4STAT_BAD_CMD, /* 0x56 */ |
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161 | L4STAT_BAD_CMD, /* 0x57 */ |
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162 | L4STAT_BAD_CMD, /* 0x58 */ |
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163 | L4STAT_BAD_CMD, /* 0x59 */ |
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164 | L4STAT_BAD_CMD, /* 0x5a */ |
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165 | L4STAT_BAD_CMD, /* 0x5b */ |
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166 | L4STAT_BAD_CMD, /* 0x5c */ |
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167 | L4STAT_BAD_CMD, /* 0x5d */ |
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168 | L4STAT_BAD_CMD, /* 0x5e */ |
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169 | L4STAT_BAD_CMD, /* 0x5f */ |
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170 | "external event 0", /* 0x60 */ |
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171 | "external event 1", /* 0x61 */ |
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172 | "external event 2", /* 0x62 */ |
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173 | "external event 3", /* 0x63 */ |
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174 | "external event 4", /* 0x64 */ |
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175 | "external event 5", /* 0x65 */ |
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176 | "external event 6", /* 0x66 */ |
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177 | "external event 7", /* 0x67 */ |
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178 | "external event 8", /* 0x68 */ |
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179 | "external event 9", /* 0x69 */ |
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180 | "external event 10", /* 0x6A */ |
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181 | "external event 11", /* 0x6B */ |
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182 | "external event 12", /* 0x6C */ |
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183 | "external event 13", /* 0x6D */ |
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184 | "external event 14", /* 0x6E */ |
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185 | "external event 15", /* 0x6F */ |
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186 | "AHB IDLE cycles (2)", /* 0x70 */ |
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187 | "AHB BUSY cycles (2)", /* 0x71 */ |
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188 | "AHB Non-Seq. transfers (2)", /* 0x72 */ |
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189 | "AHB Seq. transfers (2)", /* 0x73 */ |
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190 | "AHB read accesses (2)", /* 0x74 */ |
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191 | "AHB write accesses (2)", /* 0x75 */ |
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192 | "AHB byte accesses (2)", /* 0x76 */ |
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193 | "AHB half-word accesses (2)", /* 0x77 */ |
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194 | "AHB word accesses (2)", /* 0x78 */ |
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195 | "AHB double word accesses (2)", /* 0x79 */ |
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196 | "AHB quad word accesses (2)", /* 0x7A */ |
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197 | "AHB eight word accesses (2)", /* 0x7B */ |
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198 | "AHB waitstates (2)", /* 0x7C */ |
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199 | "AHB RETRY responses (2)", /* 0x7D */ |
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200 | "AHB SPLIT responses (2)", /* 0x7E */ |
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201 | "AHB SPLIT delay (2)", /* 0x7F */ |
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202 | "PMC: master 0 has grant", /* 0x80 */ |
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203 | "PMC: master 1 has grant", /* 0x81 */ |
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204 | "PMC: master 2 has grant", /* 0x82 */ |
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205 | "PMC: master 3 has grant", /* 0x83 */ |
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206 | "PMC: master 4 has grant", /* 0x84 */ |
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207 | "PMC: master 5 has grant", /* 0x85 */ |
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208 | "PMC: master 6 has grant", /* 0x86 */ |
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209 | "PMC: master 7 has grant", /* 0x87 */ |
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210 | "PMC: master 8 has grant", /* 0x88 */ |
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211 | "PMC: master 9 has grant", /* 0x89 */ |
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212 | "PMC: master 10 has grant", /* 0x8A */ |
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213 | "PMC: master 11 has grant", /* 0x8B */ |
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214 | "PMC: master 12 has grant", /* 0x8C */ |
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215 | "PMC: master 13 has grant", /* 0x8D */ |
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216 | "PMC: master 14 has grant", /* 0x8E */ |
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217 | "PMC: master 15 has grant", /* 0x8F */ |
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218 | "PMC: master 0 lacks grant", /* 0x90 */ |
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219 | "PMC: master 1 lacks grant", /* 0x91 */ |
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220 | "PMC: master 2 lacks grant", /* 0x92 */ |
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221 | "PMC: master 3 lacks grant", /* 0x93 */ |
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222 | "PMC: master 4 lacks grant", /* 0x94 */ |
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223 | "PMC: master 5 lacks grant", /* 0x95 */ |
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224 | "PMC: master 6 lacks grant", /* 0x96 */ |
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225 | "PMC: master 7 lacks grant", /* 0x97 */ |
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226 | "PMC: master 8 lacks grant", /* 0x98 */ |
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227 | "PMC: master 9 lacks grant", /* 0x99 */ |
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228 | "PMC: master 10 lacks grant", /* 0x9A */ |
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229 | "PMC: master 11 lacks grant", /* 0x9B */ |
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230 | "PMC: master 12 lacks grant", /* 0x9C */ |
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231 | "PMC: master 13 lacks grant", /* 0x9D */ |
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232 | "PMC: master 14 lacks grant", /* 0x9E */ |
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233 | "PMC: master 15 lacks grant", /* 0x9F */ |
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234 | "" |
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235 | }; |
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236 | #endif /* DEBUG */ |
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237 | |
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238 | /* Driver prototypes */ |
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239 | |
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240 | STATIC int l4stat_init(struct l4stat_priv *priv); |
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241 | |
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242 | int l4stat_init1(struct drvmgr_dev *dev); |
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243 | |
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244 | struct drvmgr_drv_ops l4stat_ops = |
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245 | { |
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246 | .init = {l4stat_init1, NULL, NULL, NULL}, |
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247 | .remove = NULL, |
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248 | .info = NULL |
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249 | }; |
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250 | |
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251 | struct amba_dev_id l4stat_ids[] = |
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252 | { |
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253 | {VENDOR_GAISLER, GAISLER_L4STAT}, |
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254 | {VENDOR_GAISLER, GAISLER_L3STAT}, |
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255 | {0, 0} /* Mark end of table */ |
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256 | }; |
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257 | |
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258 | struct amba_drv_info l4stat_drv_info = |
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259 | { |
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260 | { |
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261 | DRVMGR_OBJ_DRV, /* Driver */ |
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262 | NULL, /* Next driver */ |
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263 | NULL, /* Device list */ |
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264 | DRIVER_AMBAPP_GAISLER_L4STAT_ID,/* Driver ID */ |
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265 | "L4STAT_DRV", /* Driver Name */ |
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266 | DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */ |
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267 | &l4stat_ops, |
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268 | NULL, /* Funcs */ |
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269 | 0, /* No devices yet */ |
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270 | sizeof(struct l4stat_priv), /* Let DRVMGR allocate for us */ |
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271 | }, |
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272 | &l4stat_ids[0], |
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273 | }; |
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274 | |
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275 | void l4stat_register_drv (void) |
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276 | { |
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277 | DBG("Registering L4STAT driver\n"); |
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278 | drvmgr_drv_register(&l4stat_drv_info.general); |
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279 | } |
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280 | |
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281 | STATIC int l4stat_init(struct l4stat_priv *priv) |
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282 | { |
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283 | struct ambapp_apb_info *apb; |
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284 | struct amba_dev_info *ainfo = priv->dev->businfo; |
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285 | unsigned int tmp; |
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286 | unsigned short dev_id; |
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287 | |
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288 | /* Find L4STAT core from Plug&Play information */ |
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289 | apb = ainfo->info.apb_slv; |
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290 | |
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291 | /* Check if L4STAT or L3STAT core from Plug&Play information */ |
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292 | dev_id = ainfo->id.device; |
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293 | |
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294 | /* Check if rev 1 of core (only rev 0 supported) */ |
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295 | if (apb->ver != 0) { |
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296 | DBG("L4STAT rev 0 only supported.\n"); |
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297 | return L4STAT_ERR_ERROR; |
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298 | } |
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299 | |
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300 | /* Found L4STAT core, init private structure */ |
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301 | priv->regs = (struct l4stat_regs *)apb->start; |
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302 | |
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303 | DBG("L4STAT regs 0x%08x\n", (unsigned int) priv->regs); |
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304 | |
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305 | /* Find L4STAT capabilities */ |
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306 | tmp = REG_READ(&priv->regs->cctrl[0]); |
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307 | /* The CPU field in the register is just information of the |
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308 | * cpus that are connected to the stat unit, but it is not |
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309 | * really used for anything else. I can still have more masters |
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310 | * on the bus (e.g. IOMMU) that I can collect stats from, |
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311 | * so it makes no sense to limit the cpus to the actual cpus. |
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312 | * Therefore, I will take the maximum number as 16. */ |
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313 | /*priv->ncpu = ((tmp & CCTRL_NCPU) >> CCTRL_NCPU_BIT) + 1;*/ |
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314 | priv->ncpu = 16; |
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315 | if (dev_id == GAISLER_L3STAT) { |
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316 | priv->ncnt = ((tmp & CCTRL_NCNT_L3STAT) >> CCTRL_NCNT_BIT) + 1; |
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317 | }else{ |
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318 | priv->ncnt = ((tmp & CCTRL_NCNT) >> CCTRL_NCNT_BIT) + 1; |
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319 | } |
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320 | priv->max_count_support = (tmp & CCTRL_MC) >> CCTRL_MC_BIT; |
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321 | priv->internalahb_event_support = (tmp & CCTRL_IA) >> CCTRL_IA_BIT; |
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322 | priv->dsu_event_support = (tmp & CCTRL_DS) >> CCTRL_DS_BIT; |
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323 | priv->external_event_support = (tmp & CCTRL_EE) >> CCTRL_EE_BIT; |
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324 | priv->ahbtrace_event_support = (tmp & CCTRL_AE) >> CCTRL_AE_BIT; |
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325 | |
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326 | /* DEBUG print */ |
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327 | DBG("L4STAT with following capabilities:\n"); |
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328 | DBG(" -NCPU: %d, NCNT: %d, MaxCNT: %s\n", priv->ncpu, priv->ncnt, |
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329 | (priv->max_count_support?"Available":"N/A")); |
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330 | DBG(" -Events= InternalAHB: %s, DSU: %s, External: %s, AHBTRACE: %s\n", |
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331 | (priv->internalahb_event_support?"Available":"N/A"), |
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332 | (priv->dsu_event_support?"Available":"N/A"), |
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333 | (priv->external_event_support?"Available":"N/A"), |
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334 | (priv->ahbtrace_event_support?"Available":"N/A")); |
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335 | |
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336 | return L4STAT_ERR_OK; |
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337 | } |
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338 | |
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339 | int l4stat_init1(struct drvmgr_dev *dev) |
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340 | { |
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341 | struct l4stat_priv *priv = dev->priv; |
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342 | |
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343 | DBG("L4STAT[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name); |
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344 | |
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345 | if (l4statpriv) { |
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346 | DBG("Driver only supports one L4STAT core\n"); |
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347 | return DRVMGR_FAIL; |
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348 | } |
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349 | |
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350 | if (priv == NULL) { |
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351 | return DRVMGR_NOMEM; |
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352 | } |
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353 | priv->dev = dev; |
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354 | l4statpriv = priv; |
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355 | |
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356 | /* Initilize driver struct */ |
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357 | if (l4stat_init(priv) != L4STAT_ERR_OK) { |
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358 | return DRVMGR_FAIL; |
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359 | } |
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360 | |
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361 | /* Startup Action: |
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362 | * - None |
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363 | */ |
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364 | |
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365 | /* Device name */ |
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366 | sprintf(priv->devname, "l4stat0"); |
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367 | |
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368 | return DRVMGR_OK; |
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369 | } |
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370 | |
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371 | int l4stat_counter_enable(unsigned int counter, int event, int cpu, int options) |
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372 | { |
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373 | struct l4stat_priv *priv = l4statpriv; |
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374 | unsigned int ctrl; |
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375 | |
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376 | if (priv == NULL) { |
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377 | DBG("L4STAT Device not initialized\n"); |
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378 | return L4STAT_ERR_EINVAL; |
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379 | } |
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380 | |
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381 | if (counter >= priv->ncnt) { |
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382 | DBG("L4STAT Wrong counter\n"); |
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383 | return L4STAT_ERR_EINVAL; |
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384 | } |
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385 | |
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386 | if ((cpu < 0) || (cpu >= priv->ncpu)) { |
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387 | DBG("L4STAT Wrong cpu\n"); |
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388 | return L4STAT_ERR_EINVAL; |
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389 | } |
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390 | |
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391 | if ((options & L4STAT_OPTIONS_MAXIMUM_DURATION) || |
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392 | (options & L4STAT_OPTIONS_EVENT_LEVEL_ENABLE)) { |
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393 | if (priv->max_count_support == 0) { |
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394 | DBG("L4STAT maximum duration count not supported\n"); |
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395 | return L4STAT_ERR_IMPLEMENTED; |
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396 | } |
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397 | } |
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398 | |
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399 | /* Check event is supported */ |
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400 | if ((event < 0) || (event >= 0x80)) { |
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401 | DBG("L4STAT Wrong event\n"); |
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402 | return L4STAT_ERR_EINVAL; |
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403 | } |
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404 | if ((event == 0x18) || (event == 0x17)) { |
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405 | if (priv->internalahb_event_support == 0) { |
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406 | DBG("L4STAT internal ahb event not supported\n"); |
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407 | return L4STAT_ERR_IMPLEMENTED; |
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408 | } |
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409 | } |
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410 | if ((event >= 0x40) && (event < 0x60)) { |
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411 | if (priv->dsu_event_support == 0) { |
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412 | DBG("L4STAT dsu event not supported\n"); |
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413 | return L4STAT_ERR_IMPLEMENTED; |
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414 | } |
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415 | } |
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416 | if ((event >= 0x60) && (event < 0x70)) { |
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417 | if (priv->external_event_support == 0) { |
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418 | DBG("L4STAT external event not supported\n"); |
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419 | return L4STAT_ERR_IMPLEMENTED; |
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420 | } |
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421 | } |
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422 | if ((event >= 0x70) && (event < 0x80)) { |
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423 | if (priv->ahbtrace_event_support == 0) { |
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424 | DBG("L4STAT ahbtrace event not supported\n"); |
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425 | return L4STAT_ERR_IMPLEMENTED; |
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426 | } |
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427 | } |
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428 | |
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429 | /* Prepare counter control */ |
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430 | ctrl = (options & ~(CCTRL_EVENTID | CCTRL_CPUAHBM)); |
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431 | /* Put event id */ |
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432 | ctrl = (ctrl | ((event << CCTRL_EVENTID_BIT) & CCTRL_EVENTID)); |
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433 | /* Put cpu id */ |
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434 | ctrl = (ctrl | ((cpu << CCTRL_CPUAHBM_BIT) & CCTRL_CPUAHBM)); |
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435 | /* Enable counter */ |
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436 | ctrl = (ctrl | CCTRL_EN); |
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437 | |
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438 | REG_WRITE(&priv->regs->cctrl[counter], ctrl); |
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439 | |
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440 | /* DEBUG print */ |
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441 | DBG("L4STAT COUNTER[%d] enabled with event: %s, cpu: %d\n", counter, |
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442 | l4stat_event_names[event],cpu); |
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443 | |
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444 | return L4STAT_ERR_OK; |
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445 | } |
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446 | |
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447 | int l4stat_counter_disable(unsigned int counter) |
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448 | { |
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449 | struct l4stat_priv *priv = l4statpriv; |
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450 | |
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451 | if (priv == NULL) { |
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452 | DBG("L4STAT Device not initialized\n"); |
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453 | return L4STAT_ERR_EINVAL; |
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454 | } |
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455 | |
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456 | if (counter >= priv->ncnt) { |
---|
457 | DBG("L4STAT Wrong counter\n"); |
---|
458 | return L4STAT_ERR_EINVAL; |
---|
459 | } |
---|
460 | |
---|
461 | /* Disable counter */ |
---|
462 | REG_WRITE(&priv->regs->cctrl[counter], 0); |
---|
463 | |
---|
464 | /* DEBUG print */ |
---|
465 | DBG("L4STAT COUNTER[%d] disabled\n", counter); |
---|
466 | |
---|
467 | return L4STAT_ERR_OK; |
---|
468 | } |
---|
469 | |
---|
470 | int l4stat_counter_get(unsigned int counter, uint32_t * val) |
---|
471 | { |
---|
472 | struct l4stat_priv *priv = l4statpriv; |
---|
473 | |
---|
474 | if (priv == NULL) { |
---|
475 | DBG("L4STAT Device not initialized\n"); |
---|
476 | return L4STAT_ERR_EINVAL; |
---|
477 | } |
---|
478 | |
---|
479 | if (counter >= priv->ncnt) { |
---|
480 | DBG("L4STAT Wrong counter\n"); |
---|
481 | return L4STAT_ERR_EINVAL; |
---|
482 | } |
---|
483 | |
---|
484 | if (val == NULL) { |
---|
485 | DBG("L4STAT Wrong pointer\n"); |
---|
486 | return L4STAT_ERR_EINVAL; |
---|
487 | } |
---|
488 | |
---|
489 | *val = REG_READ(&priv->regs->cval[counter]); |
---|
490 | |
---|
491 | return L4STAT_ERR_OK; |
---|
492 | } |
---|
493 | |
---|
494 | int l4stat_counter_set(unsigned int counter, uint32_t val) |
---|
495 | { |
---|
496 | struct l4stat_priv *priv = l4statpriv; |
---|
497 | |
---|
498 | if (priv == NULL) { |
---|
499 | DBG("L4STAT Device not initialized\n"); |
---|
500 | return L4STAT_ERR_EINVAL; |
---|
501 | } |
---|
502 | |
---|
503 | if (counter >= priv->ncnt) { |
---|
504 | DBG("L4STAT Wrong counter\n"); |
---|
505 | return L4STAT_ERR_EINVAL; |
---|
506 | } |
---|
507 | |
---|
508 | REG_WRITE(&priv->regs->cval[counter],val); |
---|
509 | |
---|
510 | return L4STAT_ERR_OK; |
---|
511 | } |
---|
512 | |
---|
513 | int l4stat_counter_max_get(unsigned int counter, uint32_t * val) |
---|
514 | { |
---|
515 | struct l4stat_priv *priv = l4statpriv; |
---|
516 | |
---|
517 | if (priv == NULL) { |
---|
518 | DBG("L4STAT Device not initialized\n"); |
---|
519 | return L4STAT_ERR_EINVAL; |
---|
520 | } |
---|
521 | |
---|
522 | if (counter >= priv->ncnt) { |
---|
523 | DBG("L4STAT Wrong counter\n"); |
---|
524 | return L4STAT_ERR_EINVAL; |
---|
525 | } |
---|
526 | |
---|
527 | if (val == NULL) { |
---|
528 | DBG("L4STAT Wrong pointer\n"); |
---|
529 | return L4STAT_ERR_EINVAL; |
---|
530 | } |
---|
531 | |
---|
532 | *val = REG_READ(&priv->regs->cmax[counter]); |
---|
533 | |
---|
534 | return L4STAT_ERR_OK; |
---|
535 | } |
---|
536 | |
---|
537 | int l4stat_counter_max_set(unsigned int counter, uint32_t val) |
---|
538 | { |
---|
539 | struct l4stat_priv *priv = l4statpriv; |
---|
540 | |
---|
541 | if (priv == NULL) { |
---|
542 | DBG("L4STAT Device not initialized\n"); |
---|
543 | return L4STAT_ERR_EINVAL; |
---|
544 | } |
---|
545 | |
---|
546 | if (counter >= priv->ncnt) { |
---|
547 | DBG("L4STAT Wrong counter\n"); |
---|
548 | return L4STAT_ERR_EINVAL; |
---|
549 | } |
---|
550 | |
---|
551 | REG_WRITE(&priv->regs->cmax[counter],val); |
---|
552 | |
---|
553 | return L4STAT_ERR_OK; |
---|
554 | } |
---|
555 | |
---|
556 | int l4stat_tstamp_get(uint32_t * val) |
---|
557 | { |
---|
558 | struct l4stat_priv *priv = l4statpriv; |
---|
559 | |
---|
560 | if (priv == NULL) { |
---|
561 | DBG("L4STAT Device not initialized\n"); |
---|
562 | return L4STAT_ERR_EINVAL; |
---|
563 | } |
---|
564 | |
---|
565 | if (val == NULL) { |
---|
566 | DBG("L4STAT Wrong pointer\n"); |
---|
567 | return L4STAT_ERR_EINVAL; |
---|
568 | } |
---|
569 | |
---|
570 | *val = REG_READ(&priv->regs->timestamp); |
---|
571 | |
---|
572 | return L4STAT_ERR_OK; |
---|
573 | } |
---|
574 | |
---|
575 | int l4stat_tstamp_set(uint32_t val) |
---|
576 | { |
---|
577 | struct l4stat_priv *priv = l4statpriv; |
---|
578 | |
---|
579 | if (priv == NULL) { |
---|
580 | DBG("L4STAT Device not initialized\n"); |
---|
581 | return L4STAT_ERR_EINVAL; |
---|
582 | } |
---|
583 | |
---|
584 | REG_WRITE(&priv->regs->timestamp,val); |
---|
585 | |
---|
586 | return L4STAT_ERR_OK; |
---|
587 | } |
---|
588 | |
---|
589 | int l4stat_counter_print(unsigned int counter) |
---|
590 | { |
---|
591 | #ifdef DEBUG |
---|
592 | struct l4stat_priv *priv = l4statpriv; |
---|
593 | unsigned int val; |
---|
594 | unsigned int ctrl; |
---|
595 | unsigned int event; |
---|
596 | |
---|
597 | if (priv == NULL) { |
---|
598 | DBG("L4STAT Device not initialized\n"); |
---|
599 | return L4STAT_ERR_EINVAL; |
---|
600 | } |
---|
601 | |
---|
602 | if (counter >= priv->ncnt) { |
---|
603 | DBG("L4STAT Wrong counter\n"); |
---|
604 | return L4STAT_ERR_EINVAL; |
---|
605 | } |
---|
606 | |
---|
607 | /* Get counter val*/ |
---|
608 | val = REG_READ(&priv->regs->cval[counter]); |
---|
609 | |
---|
610 | /* Get counter info*/ |
---|
611 | ctrl = REG_READ(&priv->regs->cctrl[counter]); |
---|
612 | if ((ctrl & CCTRL_EN) == 0) { |
---|
613 | DBG("L4STAT COUNTER[%d] disabled\n", counter); |
---|
614 | return L4STAT_ERR_OK; |
---|
615 | } |
---|
616 | |
---|
617 | event = (ctrl & CCTRL_EVENTID) >> CCTRL_EVENTID_BIT; |
---|
618 | |
---|
619 | /* DEBUG print */ |
---|
620 | DBG("L4STAT COUNTER[%d], Event: %s, Count: %d [0x%08x]\n", |
---|
621 | counter, l4stat_event_names[event],val,val); |
---|
622 | #endif /* DEBUG */ |
---|
623 | |
---|
624 | return L4STAT_ERR_OK; |
---|
625 | } |
---|
626 | |
---|