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grspw_router.c @ d60d303c

Last change on this file since d60d303c was d60d303c, checked in by Sebastian Huber <sebastian.huber@…>, on 04/20/18 at 11:33:24

bsps/sparc: Move shared files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

Property mode set to 100644

File size: 43.5 KB

Line
1	/* GRSPW ROUTER APB-Register Driver.
2	*
3	* COPYRIGHT (c) 2010-2017.
4	* Cobham Gaisler AB.
5	*
6	* The license and distribution terms for this file may be
7	* found in the file LICENSE in this distribution or at
8	* http://www.rtems.org/license/LICENSE.
9	*/
10
11	#include <rtems.h>
12	#include <rtems/libio.h>
13	#include <rtems/bspIo.h>
14	#include <stdio.h>
15	#include <bsp.h>
16	#include <rtems/bspIo.h> /* printk */
17
18	#include <drvmgr/drvmgr.h>
19	#include <drvmgr/ambapp_bus.h>
20	#include <bsp/grspw_router.h>
21
22	//#define STATIC
23	#define STATIC static
24
25	#define UNUSED __attribute__((unused))
26
27	//#define DEBUG 1
28
29	#ifdef DEBUG
30	#define DBG(x...) printf(x)
31	#else
32	#define DBG(x...)
33	#endif
34
35	#define THREAD_SAFE 1
36
37	/* Use interrupt lock privmitives compatible with SMP defined in
38	* RTEMS 4.11.99 and higher.
39	*/
40	#if (((__RTEMS_MAJOR__ << 16) \| (__RTEMS_MINOR__ << 8) \| __RTEMS_REVISION__) >= 0x040b63)
41
42	#ifdef THREAD_SAFE
43	/* map via rtems_interrupt_lock_* API: */
44	#define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock)
45	#define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name)
46	#define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level)
47	#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level)
48	#define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level)
49	#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level)
50	#define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k
51	#define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k)
52	#define SPIN_FREE(lock) rtems_interrupt_lock_destroy(lock)
53	#else
54	#define SPIN_DECLARE(lock)
55	#define SPIN_INIT(lock, name)
56	#define SPIN_LOCK(lock, level)
57	#define SPIN_LOCK_IRQ(lock, level)
58	#define SPIN_UNLOCK(lock, level)
59	#define SPIN_UNLOCK_IRQ(lock, level)
60	#define SPIN_IRQFLAGS(k)
61	#define SPIN_ISR_IRQFLAGS(k)
62	#define SPIN_FREE(lock)
63	#endif
64
65	#else
66
67	#ifdef THREAD_SAFE
68	#error THREAD SAFE operation not supported on this RTEMS version
69	#else
70	#define SPIN_DECLARE(lock)
71	#define SPIN_INIT(lock, name)
72	#define SPIN_LOCK(lock, level)
73	#define SPIN_LOCK_IRQ(lock, level)
74	#define SPIN_UNLOCK(lock, level)
75	#define SPIN_UNLOCK_IRQ(lock, level)
76	#define SPIN_IRQFLAGS(k)
77	#define SPIN_ISR_IRQFLAGS(k)
78	#define SPIN_FREE(lock)
79	#endif
80
81	#ifdef RTEMS_SMP
82	#error SMP mode not compatible with these interrupt lock primitives
83	#endif
84
85	#endif
86
87	#define REG_WRITE(addr, val) ((volatile unsigned int )(addr) = (unsigned int)(val))
88	#define REG_READ(addr) ((volatile unsigned int )(addr))
89
90
91	/*
92	* ROUTER RTPMAP register fields
93	*/
94	#define RTPMAP_PE (0x7fffffff << RTPMAP_PE_BIT)
95	#define RTPMAP_PD (0x1 << RTPMAP_PD_BIT)
96
97	#define RTPMAP_PE_BIT 1
98	#define RTPMAP_PD_BIT 0
99
100	/*
101	* ROUTER RTACTRL register fields
102	* DEFINED IN HEADER
103	*/
104
105	/*
106	* ROUTER PCTRL register fields
107	* DEFINED IN HEADER
108	*/
109
110	/*
111	* ROUTER PSTSCFG register fields
112	* DEFINED IN HEADER
113	*/
114
115	/*
116	* ROUTER PSTS register fields
117	* DEFINED IN HEADER
118	*/
119
120	/*
121	* ROUTER PTIMER register fields
122	*/
123	#define PTIMER_RL (0xffff << PTIMER_RL_BIT)
124
125	#define PTIMER_RL_BIT 0
126
127	/*
128	* ROUTER PCTRL2 register fields
129	* DEFINED IN HEADER
130	*/
131
132	/*
133	* ROUTER RTRCFG register fields
134	*/
135	#define RTRCFG_SP (0x1f << RTRCFG_SP_BIT)
136	#define RTRCFG_AP (0x1f << RTRCFG_AP_BIT)
137	#define RTRCFG_FP (0x1f << RTRCFG_FP_BIT)
138	#define RTRCFG_SR (0x1 << RTRCFG_SR_BIT)
139	#define RTRCFG_PE (0x1 << RTRCFG_PE_BIT)
140	#define RTRCFG_IC (0x1 << RTRCFG_IC_BIT)
141	#define RTRCFG_IS (0x1 << RTRCFG_IS_BIT)
142	#define RTRCFG_IP (0x1 << RTRCFG_IP_BIT)
143	#define RTRCFG_AI (0x1 << RTRCFG_AI_BIT)
144	#define RTRCFG_AT (0x1 << RTRCFG_AT_BIT)
145	#define RTRCFG_IE (0x1 << RTRCFG_IE_BIT)
146	#define RTRCFG_RE (0x1 << RTRCFG_RE_BIT)
147	#define RTRCFG_EE (0x1 << RTRCFG_EE_BIT)
148	#define RTRCFG_LS (0x1 << RTRCFG_LS_BIT)
149	#define RTRCFG_SA (0x1 << RTRCFG_SA_BIT)
150	#define RTRCFG_TF (0x1 << RTRCFG_TF_BIT)
151	#define RTRCFG_ME (0x1 << RTRCFG_ME_BIT)
152	#define RTRCFG_TA (0x1 << RTRCFG_TA_BIT)
153	#define RTRCFG_PP (0x1 << RTRCFG_PP_BIT)
154	#define RTRCFG_WCLEAR (RTRCFG_ME)
155
156	#define RTRCFG_SP_BIT 27
157	#define RTRCFG_AP_BIT 22
158	#define RTRCFG_FP_BIT 17
159	#define RTRCFG_SR_BIT 15
160	#define RTRCFG_PE_BIT 14
161	#define RTRCFG_IC_BIT 13
162	#define RTRCFG_IS_BIT 12
163	#define RTRCFG_IP_BIT 11
164	#define RTRCFG_AI_BIT 10
165	#define RTRCFG_AT_BIT 9
166	#define RTRCFG_IE_BIT 8
167	#define RTRCFG_RE_BIT 7
168	#define RTRCFG_EE_BIT 6
169	#define RTRCFG_LS_BIT 5
170	#define RTRCFG_SA_BIT 4
171	#define RTRCFG_TF_BIT 3
172	#define RTRCFG_ME_BIT 2
173	#define RTRCFG_TA_BIT 1
174	#define RTRCFG_PP_BIT 0
175
176	/*
177	* ROUTER TC register fields
178	*/
179	#define TC_RE (0x3f << TC_RE_BIT)
180	#define TC_EN (0x3f << TC_EN_BIT)
181	#define TC_CF (0x3f << TC_CF_BIT)
182	#define TC_TC (0x3f << TC_TC_BIT)
183
184	#define TC_RE_BIT 9
185	#define TC_EN_BIT 8
186	#define TC_CF_BIT 6
187	#define TC_TC_BIT 0
188
189	/*
190	* ROUTER VER register fields
191	*/
192	#define VER_MA (0xff << VER_MA_BIT)
193	#define VER_MI (0xff << VER_MI_BIT)
194	#define VER_PA (0xff << VER_PA_BIT)
195	#define VER_ID (0xff << VER_ID_BIT)
196
197	#define VER_MA_BIT 24
198	#define VER_MI_BIT 16
199	#define VER_PA_BIT 8
200	#define VER_ID_BIT 0
201
202	/*
203	* ROUTER IDIV register fields
204	*/
205	#define IDIV_ID (0xff << IDIV_ID_BIT)
206
207	#define IDIV_ID_BIT 0
208
209	/*
210	* ROUTER CFGWE register fields
211	*/
212	#define CFGWE_WE (0x1 << CFGWE_WE_BIT)
213
214	#define CFGWE_WE_BIT 0
215
216	/*
217	* ROUTER PRESCALER register fields
218	*/
219	#define PRESCALER_RL (0xffff << PRESCALER_RL_BIT)
220
221	#define PRESCALER_RL_BIT 0
222
223	/*
224	* ROUTER IMASK register fields
225	* DEFINED IN HEADER
226	*/
227
228	/*
229	* ROUTER ICODEGEN register fields
230	* DEFINED IN HEADER
231	*/
232
233	/*
234	* ROUTER ISRTIMER register fields
235	*/
236	#define ISRTIMER_RL (0xffff << ISRTIMER_RL_BIT)
237
238	#define ISRTIMER_RL_BIT 0
239
240	/*
241	* ROUTER AITIMER register fields
242	*/
243	#define AITIMER_RL (0xffff << AITIMER_RL_BIT)
244
245	#define AITIMER_RL_BIT 0
246
247	/*
248	* ROUTER ISRCTIMER register fields
249	*/
250	#define ISRCTIMER_RL (0x1f << ISRCTIMER_RL_BIT)
251
252	#define ISRCTIMER_RL_BIT 0
253
254	/*
255	* ROUTER CAP register fields
256	*/
257	#define CAP_AF (0x3 << CAP_AF_BIT)
258	#define CAP_PF (0x7 << CAP_PF_BIT)
259	#define CAP_RM (0x7 << CAP_RM_BIT)
260	#define CAP_AS (0x1 << CAP_AS_BIT)
261	#define CAP_AX (0x1 << CAP_AX_BIT)
262	#define CAP_DP (0x1 << CAP_DP_BIT)
263	#define CAP_ID (0x1 << CAP_ID_BIT)
264	#define CAP_SD (0x1 << CAP_SD_BIT)
265	#define CAP_PC (0x1f << CAP_PC_BIT)
266	#define CAP_CC (0x1f << CAP_CC_BIT)
267
268	#define CAP_AF_BIT 24
269	#define CAP_PF_BIT 29
270	#define CAP_RM_BIT 16
271	#define CAP_AS_BIT 14
272	#define CAP_AX_BIT 13
273	#define CAP_DP_BIT 12
274	#define CAP_ID_BIT 11
275	#define CAP_SD_BIT 10
276	#define CAP_PC_BIT 4
277	#define CAP_CC_BIT 0
278
279	/*
280	* ROUTER PNPVEND register fields
281	*/
282	#define PNPVEND_VI (0xffff << PNPVEND_VI_BIT)
283	#define PNPVEND_PI (0xffff << PNPVEND_PI_BIT)
284
285	#define PNPVEND_VI_BIT 16
286	#define PNPVEND_PI_BIT 0
287
288	/*
289	* ROUTER PNPUVEND register fields
290	*/
291	#define PNPUVEND_VI (0xffff << PNPUVEND_VI_BIT)
292	#define PNPUVEND_PI (0xffff << PNPUVEND_PI_BIT)
293
294	#define PNPUVEND_VI_BIT 16
295	#define PNPUVEND_PI_BIT 0
296
297	/*
298	* ROUTER MAXPLEN register fields
299	*/
300	#define MAXPLEN_ML (0xffffff << MAXPLEN_ML_BIT)
301
302	#define MAXPLEN_ML_BIT 0
303
304	/*
305	* ROUTER CHARO register fields
306	*/
307	#define CHARO_OR (0x1 << CHARO_OR_BIT)
308	#define CHARO_CC (0x7fffffff << CHARO_CC_BIT)
309
310	#define CHARO_OR_BIT 31
311	#define CHARO_CC_BIT 0
312
313	/*
314	* ROUTER CHARI register fields
315	*/
316	#define CHARI_OR (0x1 << CHARI_OR_BIT)
317	#define CHARI_CC (0x7fffffff << CHARI_CC_BIT)
318
319	#define CHARI_OR_BIT 31
320	#define CHARI_CC_BIT 0
321
322	/*
323	* ROUTER PKTO register fields
324	*/
325	#define PKTO_OR (0x1 << PKTO_OR_BIT)
326	#define PKTO_CC (0x7fffffff << PKTO_CC_BIT)
327
328	#define PKTO_OR_BIT 31
329	#define PKTO_CC_BIT 0
330
331	/*
332	* ROUTER PKTI register fields
333	*/
334	#define PKTI_OR (0x1 << PKTI_OR_BIT)
335	#define PKTI_CC (0x7fffffff << PKTI_CC_BIT)
336
337	#define PKTI_OR_BIT 31
338	#define PKTI_CC_BIT 0
339
340	/*
341	* ROUTER CRED register fields
342	*/
343	#define CRED_OC (0x3f << CRED_OC_BIT)
344	#define CRED_IC (0x3f << CRED_IC_BIT)
345
346	#define CRED_OC_BIT 6
347	#define CRED_IC_BIT 0
348
349	/*
350	* ROUTER RTRCOMB register fields
351	*/
352	#define RTRCOMB_SR (0x1 << RTRCOMB_SR_BIT)
353	#define RTRCOMB_EN (0x1 << RTRCOMB_EN_BIT)
354	#define RTRCOMB_PR (0x1 << RTRCOMB_PR_BIT)
355	#define RTRCOMB_HD (0x1 << RTRCOMB_HD_BIT)
356	#define RTRCOMB_PE (0x7ffff << RTRCOMB_PE_BIT)
357	#define RTRCOMB_PD (0x1 << RTRCOMB_PD_BIT)
358
359	#define RTRCOMB_SR_BIT 31
360	#define RTRCOMB_EN_BIT 30
361	#define RTRCOMB_PR_BIT 29
362	#define RTRCOMB_HD_BIT 28
363	#define RTRCOMB_PE_BIT 1
364	#define RTRCOMB_PD_BIT 0
365
366	struct router_regs {
367	unsigned int resv1; /* 0x000 */
368	unsigned int psetup[255]; /* 0x004 */
369	unsigned int resv2; /* 0x400 */
370	unsigned int routes[255]; /* 0x404 */
371	unsigned int pctrl[32]; /* 0x800 */
372	unsigned int psts[32]; /* 0x880 */
373	unsigned int treload[32]; /* 0x900 */
374	unsigned int pctrl2[32]; /* 0x980 */
375	unsigned int cfgsts; /* 0xA00 */
376	unsigned int timecode; /* 0xA04 */
377	unsigned int ver; /* 0xA08 */
378	unsigned int idiv; /* 0xA0C */
379	unsigned int cfgwe; /* 0xA10 */
380	unsigned int tprescaler; /* 0xA14 */
381	unsigned int imask; /* 0xA18 */
382	unsigned int ipmask; /* 0xA1C */
383	unsigned int pip; /* 0xA20 */
384	unsigned int icodegen; /* 0xA24 */
385	unsigned int isr0; /* 0xA28 */
386	unsigned int isr1; /* 0xA2C */
387	unsigned int isrtimer; /* 0xA30 */
388	unsigned int aitimer; /* 0xA34 */
389	unsigned int isrctimer; /* 0xA38 */
390	unsigned int resv4; /* 0xA3C */
391	unsigned int lrunsts; /* 0xA40 */
392	unsigned int cap; /* 0xA44 */
393	unsigned int resv5[111]; /* 0xA48 */
394	unsigned int charo[31]; /* 0xC04 / / TODO check GR718 */
395	unsigned int resv6; /* 0xC80 */
396	unsigned int chari[31]; /* 0xC84 */
397	unsigned int resv7; /* 0xD00 */
398	unsigned int pkto[31]; /* 0xD04 */
399	unsigned int resv8; /* 0xD80 */
400	unsigned int pkti[31]; /* 0xD84 */
401	unsigned int maxplen[32]; /* 0xE00 */
402	unsigned int resv9; /* 0xE80 */
403	unsigned int credcnt[31]; /* 0xE84 */
404	unsigned int resv10[64]; /* 0xF00 */
405	unsigned int resv11; /* 0x1000 */
406	unsigned int rtcomb[255]; /* 0x1004 */
407	};
408
409	struct router_priv {
410	struct drvmgr_dev *dev;
411
412	/* ROUTER control registers */
413	struct router_regs *regs;
414
415	#ifdef THREAD_SAFE
416	/* ROUTER semaphore */
417	rtems_id sem;
418	#endif
419
420	/* ROUTER driver register */
421	char devname[9];
422	int index; /* Index in order it was probed */
423
424	int minor;
425	int open;
426	struct router_hw_info hwinfo;
427	int nports;
428	int irq_init;
429
430	SPIN_DECLARE(plock[32])
431
432	};
433
434	int router_count = 0;
435	static struct router_priv *priv_tab[ROUTER_MAX];
436
437	/* Driver prototypes */
438
439	STATIC int router_init(struct router_priv *priv);
440	STATIC void router_hwinfo(struct router_priv *priv,
441	struct router_hw_info *hwinfo);
442	STATIC int router_acontrol_set(struct router_priv *priv,
443	struct router_route_acontrol *control);
444	STATIC int router_acontrol_get(struct router_priv *priv,
445	struct router_route_acontrol *control);
446	STATIC int router_portmap_set(struct router_priv *priv,
447	struct router_route_portmap *pmap);
448	STATIC int router_portmap_get(struct router_priv *priv,
449	struct router_route_portmap *pmap);
450
451	/* -IRQ handler */
452	void router_isr(void *arg);
453
454	int router_init2(struct drvmgr_dev *dev);
455
456	struct drvmgr_drv_ops router_ops =
457	{
458	.init = {NULL, router_init2, NULL, NULL},
459	.remove = NULL,
460	.info = NULL
461	};
462
463	struct amba_dev_id router_ids[] =
464	{
465	{VENDOR_GAISLER, GAISLER_SPW_ROUTER},
466	{0, 0} /* Mark end of table */
467	};
468
469	struct amba_drv_info router_drv_info =
470	{
471	{
472	DRVMGR_OBJ_DRV, /* Driver */
473	NULL, /* Next driver */
474	NULL, /* Device list */
475	DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID,/* Driver ID */
476	"ROUTER_DRV", /* Driver Name */
477	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
478	&router_ops,
479	NULL, /* Funcs */
480	0, /* No devices yet */
481	sizeof(struct router_priv), /* Let DRVMGR allocate for us */
482	},
483	&router_ids[0],
484	};
485
486	void router_register_drv (void)
487	{
488	DBG("Registering SPW ROUTER driver\n");
489	drvmgr_drv_register(&router_drv_info.general);
490	}
491
492	STATIC void router_hwinfo(struct router_priv *priv,
493	struct router_hw_info *hwinfo)
494	{
495	unsigned int tmp;
496
497	/* Find router info */
498	tmp = REG_READ(&priv->regs->cfgsts);
499	hwinfo->nports_spw = (tmp & RTRCFG_SP) >> RTRCFG_SP_BIT;
500	hwinfo->nports_amba = (tmp & RTRCFG_AP) >> RTRCFG_AP_BIT;
501	hwinfo->nports_fifo = (tmp & RTRCFG_FP) >> RTRCFG_FP_BIT;
502	hwinfo->srouting = (tmp & RTRCFG_SR) >> RTRCFG_SR_BIT;
503	hwinfo->pnp_enable = (tmp & RTRCFG_PE) >> RTRCFG_PE_BIT;
504	hwinfo->timers_avail = (tmp & RTRCFG_TA) >> RTRCFG_TA_BIT;
505	hwinfo->pnp_avail = (tmp & RTRCFG_PP) >> RTRCFG_PP_BIT;
506
507	tmp = REG_READ(&priv->regs->ver);
508	hwinfo->ver_major = (tmp & VER_MA) >> VER_MA_BIT;
509	hwinfo->ver_minor = (tmp & VER_MI) >> VER_MI_BIT;
510	hwinfo->ver_patch = (tmp & VER_PA) >> VER_PA_BIT;
511	hwinfo->iid = (tmp & VER_ID) >> VER_ID_BIT;
512
513	/* Find router capabilities */
514	tmp = REG_READ(&priv->regs->cap);
515	hwinfo->amba_port_fifo_size = 4 << ((tmp & CAP_AF) >> CAP_AF_BIT);
516	hwinfo->spw_port_fifo_size = 16 << ((tmp & CAP_PF) >> CAP_PF_BIT);
517	hwinfo->rmap_maxdlen = 4 << ((tmp & CAP_RM) >> CAP_RM_BIT);
518	hwinfo->aux_async = (tmp & CAP_AS) >> CAP_AS_BIT;
519	hwinfo->aux_dist_int_support = (tmp & CAP_AX) >> CAP_AX_BIT;
520	hwinfo->dual_port_support = (tmp & CAP_ID) >> CAP_ID_BIT;
521	hwinfo->dist_int_support = (tmp & CAP_DP) >> CAP_DP_BIT;
522	hwinfo->spwd_support = (tmp & CAP_SD) >> CAP_SD_BIT;
523	hwinfo->pktcnt_support = (tmp & CAP_PC) >> CAP_PC_BIT;
524	hwinfo->charcnt_support = (tmp & CAP_CC) >> CAP_CC_BIT;
525	}
526
527	STATIC void router_hwinfo_print(struct router_hw_info *hwinfo)
528	{
529	DBG(" -PORTS= SPW: %d, AMBA: %d, FIFO: %d\n", hwinfo->nports_spw,
530	hwinfo->nports_amba, hwinfo->nports_fifo);
531	DBG(" -Static routing: %s, Timers: %s\n",
532	(hwinfo->srouting?"Enabled":"Disabled"),
533	(hwinfo->timers_avail?"Available":"N/A"));
534	DBG(" -PnP: %s, %s\n",
535	(hwinfo->pnp_avail?"Available":"N/A"),
536	(hwinfo->pnp_enable?"Enabled":"Disabled"));
537	DBG(" -Version= Major: 0x%02x, Minor: 0x%02x, Patch: 0x%02x, ID: 0x%02x\n",
538	hwinfo->ver_major, hwinfo->ver_minor,
539	hwinfo->ver_patch, hwinfo->iid);
540	DBG(" -Aux: %s, AuxDistInt: %s, DistInt: %s, SPWD: %s, PKTCNT: %s, "
541	"CHARCNT: %s\n",
542	(hwinfo->aux_async?"Async":"Sync"),
543	(hwinfo->aux_dist_int_support?"Supported":"N/A"),
544	(hwinfo->dist_int_support?"Supported":"N/A"),
545	(hwinfo->spwd_support?"Supported":"N/A"),
546	(hwinfo->pktcnt_support?"Supported":"N/A"),
547	(hwinfo->charcnt_support?"Supported":"N/A"));
548	}
549
550	STATIC int router_acontrol_set(struct router_priv *priv,
551	struct router_route_acontrol *control)
552	{
553	int i;
554	for (i=0; i<31; i++) {
555	REG_WRITE(&priv->regs->routes[i], control->control[i]);
556	}
557	for (i=0; i<224; i++) {
558	REG_WRITE(&priv->regs->routes[i+31], control->control_logical[i]);
559	}
560	return ROUTER_ERR_OK;
561	}
562
563	STATIC int router_acontrol_get(struct router_priv *priv,
564	struct router_route_acontrol *control)
565	{
566	int i;
567	for (i=0; i<31; i++) {
568	control->control[i] = REG_READ(&priv->regs->routes[i]);
569	}
570	for (i=0; i<224; i++) {
571	control->control_logical[i] = REG_READ(&priv->regs->routes[i+31]);
572	}
573	return ROUTER_ERR_OK;
574	}
575
576	STATIC int router_portmap_set(struct router_priv *priv,
577	struct router_route_portmap *pmap)
578	{
579	int i;
580	for (i=0; i<31; i++) {
581	REG_WRITE(&priv->regs->psetup[i], pmap->pmap[i]);
582	}
583	for (i=0; i<224; i++) {
584	REG_WRITE(&priv->regs->psetup[i+31], pmap->pmap_logical[i]);
585	}
586	return ROUTER_ERR_OK;
587	}
588
589	STATIC int router_portmap_get(struct router_priv *priv,
590	struct router_route_portmap *pmap)
591	{
592	int i;
593	for (i=0; i<31; i++) {
594	pmap->pmap[i] = REG_READ(&priv->regs->psetup[i]);
595	}
596	for (i=0; i<224; i++) {
597	pmap->pmap_logical[i] = REG_READ(&priv->regs->psetup[i+31]);
598	}
599	return ROUTER_ERR_OK;
600	}
601
602	STATIC int router_init(struct router_priv *priv)
603	{
604	#ifdef THREAD_SAFE
605	int i;
606
607	/* Device Semaphore created with count = 1 */
608	if (rtems_semaphore_create(
609	rtems_build_name('S', 'R', 'O', '0' + priv->index), 1,
610	RTEMS_FIFO \| RTEMS_SIMPLE_BINARY_SEMAPHORE \| \
611	RTEMS_NO_INHERIT_PRIORITY \| RTEMS_LOCAL \| \
612	RTEMS_NO_PRIORITY_CEILING, 0, &priv->sem) != RTEMS_SUCCESSFUL) {
613	return DRVMGR_FAIL;
614	}
615	#endif
616
617	/* Find router info */
618	router_hwinfo(priv, &priv->hwinfo);
619
620	priv->open = 0;
621	/* Number of ports has to consider the configuration port (1 + SPW + AMBA + FIFO) */
622	priv->nports = 1 + priv->hwinfo.nports_spw + priv->hwinfo.nports_amba +
623	priv->hwinfo.nports_fifo;
624	if ((priv->nports < 2) \|\| (priv->nports > 32)) {
625	return DRVMGR_EIO;
626	}
627
628	#ifdef THREAD_SAFE
629	/* Init port spin-lock memory structures */
630	for (i=0; i<priv->nports; i++) {
631	SPIN_INIT(&priv->plock[i],"portlock");
632	}
633	#endif
634
635	/* DEBUG print */
636	DBG("SPW ROUTER[%d] with following capabilities:\n", priv->index);
637	router_hwinfo_print(&priv->hwinfo);
638
639	return DRVMGR_OK;
640	}
641
642	int router_init2(struct drvmgr_dev *dev)
643	{
644	struct router_priv *priv = dev->priv;
645	struct amba_dev_info *ambadev;
646	struct ambapp_core *pnpinfo;
647	unsigned int tmp;
648	int i;
649	int status;
650
651	DBG("SPW ROUTER[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
652
653	if (router_count >= ROUTER_MAX) {
654	return DRVMGR_ENORES;
655	}
656
657	if (priv == NULL) {
658	return DRVMGR_NOMEM;
659	}
660	priv->dev = dev;
661
662	/* Get device information from AMBA PnP information */
663	ambadev = (struct amba_dev_info *)priv->dev->businfo;
664	if (ambadev == NULL) {
665	return DRVMGR_FAIL;
666	}
667	pnpinfo = &ambadev->info;
668	priv->regs = (struct router_regs *)pnpinfo->ahb_slv->start[0];
669	priv->minor = dev->minor_drv;
670
671	/* Initilize driver struct */
672	status = router_init(priv);
673	if (status != DRVMGR_OK) {
674	return status;
675	}
676
677	/* Startup Action:
678	* - Clear interrupts
679	* - Mask interrupts
680	*/
681
682	/* Mask interrupts in ROTUER */
683	REG_WRITE(&priv->regs->imask,0);
684	REG_WRITE(&priv->regs->ipmask,0);
685
686	/* Clear interrupts in ROTUER */
687	REG_WRITE(&priv->regs->pip,0xffffffff);
688
689	/* Clear errors in router and ports */
690	tmp = REG_READ(&priv->regs->cfgsts);
691	REG_WRITE(&priv->regs->cfgsts, tmp \| RTRCFG_WCLEAR);
692	tmp = REG_READ(&priv->regs->psts[0]);
693	REG_WRITE(&priv->regs->psts[0], (tmp & PSTSCFG_WCLEAR) \| PSTSCFG_WCLEAR2);
694	for (i=1; i<priv->nports; i++) {
695	tmp = REG_READ(&priv->regs->psts[i]);
696	REG_WRITE(&priv->regs->psts[i], tmp & PSTS_WCLEAR);
697	}
698
699	/* Register driver internally */
700	priv->index = router_count;
701	priv_tab[priv->index] = priv;
702	router_count++;
703
704	/* Device name */
705	sprintf(priv->devname, "router%d", priv->index);
706
707	return DRVMGR_OK;
708	}
709
710	void *router_open(unsigned int dev_no)
711	{
712	struct router_priv priv, ret;
713
714	if (dev_no >= router_count) {
715	DBG("ROUTER Wrong index %u\n", dev_no);
716	return NULL;
717	}
718
719	priv = priv_tab[dev_no];
720
721	if (priv == NULL) {
722	DBG("ROUTER Device not initialized\n");
723	return NULL;
724	}
725
726	#ifdef THREAD_SAFE
727	/* Take device lock - Wait until we get semaphore */
728	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
729	!= RTEMS_SUCCESSFUL) {
730	DBG("ROUTER Sempahore failed\n");
731	return NULL;
732	}
733	#endif
734
735	if (priv->open) {
736	DBG("ROUTER Device already opened\n");
737	ret = NULL;
738	} else {
739	/* Take the device */
740	priv->open = 1;
741	ret = priv;
742	}
743	#ifdef THREAD_SAFE
744	/* Unlock dev */
745	rtems_semaphore_release(priv->sem);
746	#endif
747
748	return ret;
749	}
750
751	int router_close(void *d)
752	{
753	struct router_priv *priv = d;
754	int ret;
755
756	if (priv == NULL) {
757	DBG("ROUTER Device not initialized\n");
758	return ROUTER_ERR_EINVAL;
759	}
760
761	#ifdef THREAD_SAFE
762	/* Take device lock - Wait until we get semaphore */
763	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
764	!= RTEMS_SUCCESSFUL) {
765	DBG("ROUTER Sempahore failed\n");
766	return ROUTER_ERR_ERROR;
767	}
768	#endif
769
770	if (priv->open == 0) {
771	DBG("ROUTER Device already closed\n");
772	ret = ROUTER_ERR_ERROR;
773	} else {
774	/* Mark not open */
775	priv->open = 0;
776	ret = ROUTER_ERR_OK;
777	}
778
779	#ifdef THREAD_SAFE
780	/* Unlock dev */
781	rtems_semaphore_release(priv->sem);
782	#endif
783
784	return ret;
785	}
786
787	STATIC int router_check_open(void *d)
788	{
789	struct router_priv *priv = d;
790
791	if (priv == NULL) {
792	DBG("ROUTER Device not initialized\n");
793	return ROUTER_ERR_EINVAL;
794	}
795
796	if (priv->open == 0) {
797	DBG("ROUTER Device closed\n");
798	return ROUTER_ERR_ERROR;
799	}
800
801	return 0;
802	}
803
804	STATIC int router_check_port(void *d, int port)
805	{
806	int ret = router_check_open(d);
807
808	if (ret == 0) {
809	struct router_priv *priv = d;
810	if((port < 0) \|\| (port >= priv->nports)) {
811	DBG("ROUTER wrong port\n");
812	ret = ROUTER_ERR_EINVAL;
813	}
814	}
815
816	return ret;
817	}
818
819	STATIC int router_check_distint_support(void *d)
820	{
821	int ret = router_check_open(d);
822
823	if (ret == 0) {
824	struct router_priv *priv = d;
825	if (priv->hwinfo.dist_int_support == 0) {
826	DBG("ROUTER Dist interrupts not supported\n");
827	ret = ROUTER_ERR_IMPLEMENTED;
828	}
829	}
830
831	return ret;
832	}
833
834	int router_hwinfo_get(void d, struct router_hw_info hwinfo)
835	{
836	struct router_priv *priv = d;
837	int error = router_check_open(d);
838
839	if (error)
840	return error;
841
842	if (hwinfo == NULL) {
843	DBG("ROUTER Wrong pointer\n");
844	return ROUTER_ERR_EINVAL;
845	}
846
847	/* Get hwinfo */
848	router_hwinfo(priv, hwinfo);
849
850	return ROUTER_ERR_OK;
851	}
852
853	int router_print(void *d)
854	{
855	struct router_priv *priv = d;
856	int error = router_check_open(d);
857
858	if (error)
859	return error;
860
861	/* DEBUG print */
862	DBG("Number of routers: %d\n", router_count);
863	DBG("SPW ROUTER[%d] with following capabilities:\n", priv->index);
864	router_hwinfo_print(&priv->hwinfo);
865
866	return ROUTER_ERR_OK;
867	}
868
869	/* Configure Router. Leave field NULL in order to skip configuration
870	*/
871	int router_config_set(void d, struct router_config cfg)
872	{
873	struct router_priv *priv = d;
874	int error = router_check_open(d);
875
876	if (error)
877	return error;
878
879	if (cfg == NULL) {
880	DBG("ROUTER CFG wrong\n");
881	return ROUTER_ERR_EINVAL;
882	}
883
884	if ((cfg->flags & (ROUTER_FLG_TPRES\|ROUTER_FLG_TRLD)) &&
885	!priv->hwinfo.timers_avail) {
886	return ROUTER_ERR_IMPLEMENTED;
887	}
888
889	#ifdef THREAD_SAFE
890	/* Take device lock - Wait until we get semaphore */
891	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
892	!= RTEMS_SUCCESSFUL) {
893	DBG("ROUTER Sempahore failed\n");
894	return ROUTER_ERR_ERROR;
895	}
896	#endif
897
898	/* Write only configuration bits in Config register */
899	if (cfg->flags & ROUTER_FLG_CFG) {
900	REG_WRITE(&priv->regs->cfgsts, cfg->config & ~(RTRCFG_WCLEAR));
901	}
902
903	/* Write Instance ID to Version Register */
904	if (cfg->flags & ROUTER_FLG_IID) {
905	REG_WRITE(&priv->regs->ver, (cfg->iid << VER_ID_BIT) & VER_ID);
906	}
907
908	/* Write startup-clock-divisor Register */
909	if (cfg->flags & ROUTER_FLG_IDIV) {
910	REG_WRITE(&priv->regs->idiv, (cfg->idiv << IDIV_ID_BIT) & IDIV_ID);
911	}
912
913	/* Write Timer Prescaler Register */
914	if (cfg->flags & ROUTER_FLG_TPRES) {
915	REG_WRITE(&priv->regs->tprescaler,
916	(cfg->timer_prescaler << PRESCALER_RL_BIT) & PRESCALER_RL);
917	}
918
919	#ifdef THREAD_SAFE
920	/* Unlock dev */
921	rtems_semaphore_release(priv->sem);
922	#endif
923
924	return ROUTER_ERR_OK;
925	}
926
927	int router_config_get(void d, struct router_config cfg)
928	{
929	struct router_priv *priv = d;
930	int error = router_check_open(d);
931
932	if (error)
933	return error;
934
935	if (cfg == NULL) {
936	DBG("ROUTER CFG wrong\n");
937	return ROUTER_ERR_EINVAL;
938	}
939
940	#ifdef THREAD_SAFE
941	/* Take device lock - Wait until we get semaphore */
942	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
943	!= RTEMS_SUCCESSFUL) {
944	DBG("ROUTER Sempahore failed\n");
945	return ROUTER_ERR_ERROR;
946	}
947	#endif
948
949	cfg->config = REG_READ(&priv->regs->cfgsts) &
950	~(RTRCFG_SP\|RTRCFG_AP\|RTRCFG_FP\|RTRCFG_SR\|RTRCFG_PE\|RTRCFG_ME\|
951	RTRCFG_TA\|RTRCFG_PP);
952	cfg->iid = (REG_READ(&priv->regs->ver) & VER_ID) >> VER_ID_BIT;
953	cfg->idiv = (REG_READ(&priv->regs->idiv) & IDIV_ID) >> IDIV_ID_BIT;
954	cfg->timer_prescaler =
955	(REG_READ(&priv->regs->tprescaler) & PRESCALER_RL) >> PRESCALER_RL_BIT;
956
957	#ifdef THREAD_SAFE
958	/* Unlock dev */
959	rtems_semaphore_release(priv->sem);
960	#endif
961
962	return ROUTER_ERR_OK;
963	}
964
965	/* Configure Router routing table.
966	* Leave field NULL in order to skip configuration
967	*/
968	int router_routing_table_set(void d, struct router_routing_table cfg)
969	{
970	struct router_priv *priv = d;
971	int error = router_check_open(d);
972
973	if (error)
974	return error;
975
976	if (cfg == NULL) {
977	DBG("ROUTER CFG wrong\n");
978	return ROUTER_ERR_EINVAL;
979	}
980
981	#ifdef THREAD_SAFE
982	/* Take device lock - Wait until we get semaphore */
983	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
984	!= RTEMS_SUCCESSFUL) {
985	DBG("ROUTER Sempahore failed\n");
986	return ROUTER_ERR_ERROR;
987	}
988	#endif
989
990	/* Write Address control */
991	if (cfg->flags & ROUTER_ROUTE_FLG_CTRL) {
992	router_acontrol_set(priv,&cfg->acontrol);
993	}
994
995	/* Write Port map */
996	if (cfg->flags & ROUTER_ROUTE_FLG_MAP) {
997	router_portmap_set(priv,&cfg->portmap);
998	}
999
1000	#ifdef THREAD_SAFE
1001	/* Unlock dev */
1002	rtems_semaphore_release(priv->sem);
1003	#endif
1004
1005	return ROUTER_ERR_OK;
1006	}
1007
1008	int router_routing_table_get(void d, struct router_routing_table cfg)
1009	{
1010	struct router_priv *priv = d;
1011	int error = router_check_open(d);
1012
1013	if (error)
1014	return error;
1015
1016	if (cfg == NULL) {
1017	DBG("ROUTER CFG wrong\n");
1018	return ROUTER_ERR_EINVAL;
1019	}
1020
1021	#ifdef THREAD_SAFE
1022	/* Take device lock - Wait until we get semaphore */
1023	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1024	!= RTEMS_SUCCESSFUL) {
1025	DBG("ROUTER Sempahore failed\n");
1026	return ROUTER_ERR_ERROR;
1027	}
1028	#endif
1029
1030	/* Read Address control */
1031	router_acontrol_get(priv,&cfg->acontrol);
1032
1033	/* Read Port map */
1034	router_portmap_get(priv,&cfg->portmap);
1035
1036	#ifdef THREAD_SAFE
1037	/* Unlock dev */
1038	rtems_semaphore_release(priv->sem);
1039	#endif
1040
1041	return ROUTER_ERR_OK;
1042	}
1043
1044	int router_route_set(void d, struct router_route route)
1045	{
1046	struct router_priv *priv = d;
1047	int i;
1048	unsigned int mask;
1049	int error = router_check_open(d);
1050
1051	if (error)
1052	return error;
1053
1054	if (route == NULL) {
1055	DBG("ROUTER route wrong\n");
1056	return ROUTER_ERR_EINVAL;
1057	}
1058
1059	if (route->from_address < 32) {
1060	/* Physical address */
1061	if ((route->from_address == 0) \|\|
1062	(route->from_address >= priv->nports)) {
1063	DBG("ROUTER wrong physical address\n");
1064	return ROUTER_ERR_TOOMANY;
1065	}
1066	}
1067
1068	/* Compute port map */
1069	mask=0;
1070	for (i=0; i < route->count; i++) {
1071	if ((route->to_port[i] == 0) \|\| (route->to_port[i] >= priv->nports)) {
1072	DBG("ROUTER route wrong destiny port\n");
1073	return ROUTER_ERR_EINVAL;
1074	}
1075	mask \|= (0x1 << route->to_port[i]);
1076	}
1077	if (route->options & ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE) {
1078	mask \|= RTPMAP_PD;
1079	}
1080
1081	#ifdef THREAD_SAFE
1082	/* Take device lock - Wait until we get semaphore */
1083	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1084	!= RTEMS_SUCCESSFUL) {
1085	DBG("ROUTER Sempahore failed\n");
1086	return ROUTER_ERR_ERROR;
1087	}
1088	#endif
1089
1090	/* Write port map */
1091	REG_WRITE(&priv->regs->psetup[route->from_address-1], mask);
1092
1093	/* Write Address control */
1094	REG_WRITE(&priv->regs->routes[route->from_address-1],
1095	route->options & (0xf));
1096
1097	#ifdef THREAD_SAFE
1098	/* Unlock dev */
1099	rtems_semaphore_release(priv->sem);
1100	#endif
1101
1102	return ROUTER_ERR_OK;
1103	}
1104
1105	int router_route_get(void d, struct router_route route)
1106	{
1107	struct router_priv *priv = d;
1108	int i,count;
1109	unsigned int mask;
1110	int error = router_check_open(d);
1111
1112	if (error)
1113	return error;
1114
1115	if (route == NULL) {
1116	DBG("ROUTER route wrong\n");
1117	return ROUTER_ERR_EINVAL;
1118	}
1119
1120	if (route->from_address < 32) {
1121	/* Physical address */
1122	if ((route->from_address == 0) \|\|
1123	(route->from_address >= priv->nports)) {
1124	DBG("ROUTER wrong physical address\n");
1125	return ROUTER_ERR_TOOMANY;
1126	}
1127	}
1128
1129	#ifdef THREAD_SAFE
1130	/* Take device lock - Wait until we get semaphore */
1131	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1132	!= RTEMS_SUCCESSFUL) {
1133	DBG("ROUTER Sempahore failed\n");
1134	return ROUTER_ERR_ERROR;
1135	}
1136	#endif
1137
1138	/* Get Address control */
1139	route->options =
1140	REG_READ(&priv->regs->routes[route->from_address-1]) & (0xf);
1141
1142	/* Read port map */
1143	mask=REG_READ(&priv->regs->psetup[route->from_address-1]);
1144
1145	#ifdef THREAD_SAFE
1146	/* Unlock dev */
1147	rtems_semaphore_release(priv->sem);
1148	#endif
1149
1150	if (mask & RTPMAP_PD) {
1151	route->options \|= ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE;
1152	}
1153
1154	/*DBG("ROUTE from address 0x%02x read, PMAP: 0x%08x, CTRL: 0x%08x\n",
1155	* (unsigned int) route->from_address, mask,
1156	* (unsigned int) route->options);*/
1157
1158	i=0;
1159	count=0;
1160	mask &= (RTPMAP_PE);
1161	while (mask != 0) {
1162	if (mask & 0x1) {
1163	route->to_port[count] = i;
1164	count++;
1165	}
1166	mask >>= 1;
1167	i++;
1168	}
1169	route->count=count;
1170
1171	return ROUTER_ERR_OK;
1172	}
1173
1174	int router_write_enable(void *d)
1175	{
1176	struct router_priv *priv = d;
1177	int error = router_check_open(d);
1178
1179	if (error)
1180	return error;
1181
1182	REG_WRITE(&priv->regs->cfgwe, 0x1);
1183
1184	return ROUTER_ERR_OK;
1185	}
1186
1187	int router_write_disable(void *d)
1188	{
1189	struct router_priv *priv = d;
1190	int error = router_check_open(d);
1191
1192	if (error)
1193	return error;
1194
1195	REG_WRITE(&priv->regs->cfgwe, 0x0);
1196
1197	return ROUTER_ERR_OK;
1198	}
1199
1200	int router_port_ioc(void d, int port, struct router_port cfg)
1201	{
1202	struct router_priv *priv = d;
1203	unsigned int ctrl, ctrl2, sts, timer, pktl;
1204	SPIN_IRQFLAGS(irqflags);
1205	int error = router_check_port(d, port);
1206
1207	if (error)
1208	return error;
1209
1210	if (cfg == NULL) {
1211	DBG("ROUTER Wrong cfg\n");
1212	return ROUTER_ERR_EINVAL;
1213	}
1214
1215	SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1216
1217	ctrl = cfg->ctrl;
1218	if (cfg->flag & ROUTER_PORT_FLG_GET_CTRL) {
1219	ctrl = REG_READ(&priv->regs->pctrl[port]);
1220	}
1221	ctrl2 = cfg->ctrl;
1222	if (cfg->flag & ROUTER_PORT_FLG_GET_CTRL2) {
1223	ctrl2 = REG_READ(&priv->regs->pctrl2[port]);
1224	}
1225	sts = cfg->sts;
1226	if (cfg->flag & ROUTER_PORT_FLG_GET_STS) {
1227	sts = REG_READ(&priv->regs->psts[port]);
1228	}
1229	timer = cfg->timer_reload;
1230	if (cfg->flag & ROUTER_PORT_FLG_GET_TIMER) {
1231	REG_READ(&priv->regs->treload[port]);
1232	}
1233	pktl = cfg->packet_length;
1234	if (cfg->flag & ROUTER_PORT_FLG_GET_PKTLEN) {
1235	REG_READ(&priv->regs->maxplen[port]);
1236	}
1237
1238	if (cfg->flag & ROUTER_PORT_FLG_SET_CTRL) {
1239	REG_WRITE(&priv->regs->pctrl[port], cfg->ctrl);
1240	}
1241	if (cfg->flag & ROUTER_PORT_FLG_SET_CTRL2) {
1242	REG_WRITE(&priv->regs->pctrl2[port], cfg->ctrl2);
1243	}
1244	if (cfg->flag & ROUTER_PORT_FLG_SET_STS) {
1245	REG_WRITE(&priv->regs->psts[port], cfg->sts);
1246	}
1247	if (cfg->flag & ROUTER_PORT_FLG_SET_TIMER) {
1248	REG_WRITE(&priv->regs->treload[port], cfg->timer_reload & PTIMER_RL);
1249	}
1250	if (cfg->flag & ROUTER_PORT_FLG_SET_PKTLEN) {
1251	REG_WRITE(&priv->regs->maxplen[port], cfg->packet_length & MAXPLEN_ML);
1252	}
1253
1254	SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1255
1256	cfg->ctrl = ctrl;
1257	cfg->ctrl2 = ctrl2;
1258	cfg->sts = sts;
1259	cfg->timer_reload = timer;
1260	cfg->packet_length = pktl;
1261
1262	return ROUTER_ERR_OK;
1263	}
1264
1265	int router_port_ctrl_rmw(void d, int port, uint32_t oldvalue, uint32_t bitmask, uint32_t value)
1266	{
1267	struct router_priv *priv = d;
1268	int error = router_check_port(d, port);
1269	unsigned int oldctrl, ctrl;
1270	SPIN_IRQFLAGS(irqflags);
1271
1272	if (error)
1273	return error;
1274
1275	SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1276
1277	oldctrl = REG_READ(&priv->regs->pctrl[port]);
1278	ctrl = ((oldctrl & ~(bitmask)) \| (value & bitmask));
1279	REG_WRITE(&priv->regs->pctrl[port], ctrl);
1280
1281	SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1282
1283	if (oldvalue != NULL) {
1284	*oldvalue = oldctrl;
1285	}
1286
1287	return ROUTER_ERR_OK;
1288	}
1289
1290	int router_port_ctrl2_rmw(void d, int port, uint32_t oldvalue, uint32_t bitmask, uint32_t value)
1291	{
1292	struct router_priv *priv = d;
1293	int error = router_check_port(d, port);
1294	unsigned int oldctrl, ctrl;
1295	SPIN_IRQFLAGS(irqflags);
1296
1297	if (error)
1298	return error;
1299
1300	SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1301
1302	oldctrl = REG_READ(&priv->regs->pctrl2[port]);
1303	ctrl = ((oldctrl & ~(bitmask)) \| (value & bitmask));
1304	REG_WRITE(&priv->regs->pctrl2[port], ctrl);
1305
1306	SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1307
1308	if (oldvalue != NULL) {
1309	*oldvalue = oldctrl;
1310	}
1311
1312	return ROUTER_ERR_OK;
1313	}
1314
1315	/* Read Port Control register */
1316	int router_port_ctrl_get(void d, int port, uint32_t ctrl)
1317	{
1318	struct router_priv *priv = d;
1319	int error = router_check_port(d, port);
1320
1321	if (error)
1322	return error;
1323
1324	if (ctrl == NULL) {
1325	DBG("ROUTER Wrong ctrl\n");
1326	return ROUTER_ERR_EINVAL;
1327	}
1328
1329	*ctrl = REG_READ(&priv->regs->pctrl[port]);
1330	return ROUTER_ERR_OK;
1331	}
1332
1333	/* Read Port Status register and clear errors if there are */
1334	int router_port_status(void d, int port, uint32_t sts, uint32_t clrmsk)
1335	{
1336	struct router_priv *priv = d;
1337	int error = router_check_port(d, port);
1338	SPIN_IRQFLAGS(irqflags);
1339
1340	if (error)
1341	return error;
1342
1343	if (sts == NULL) {
1344	DBG("ROUTER Wrong sts\n");
1345	return ROUTER_ERR_EINVAL;
1346	}
1347
1348	SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1349	*sts = REG_READ(&priv->regs->psts[port]);
1350	if (port == 0) {
1351	REG_WRITE(&priv->regs->psts[port], ((*sts) & (PSTSCFG_WCLEAR & clrmsk)) \| (PSTSCFG_WCLEAR2 & clrmsk));
1352	}else{
1353	REG_WRITE(&priv->regs->psts[port], (*sts) & (PSTS_WCLEAR & clrmsk));
1354	}
1355	SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1356	return ROUTER_ERR_OK;
1357	}
1358
1359	/* Read Port Control2 register */
1360	int router_port_ctrl2_get(void d, int port, uint32_t ctrl2)
1361	{
1362	struct router_priv *priv = d;
1363	int error = router_check_port(d, port);
1364
1365	if (error)
1366	return error;
1367
1368	if (ctrl2 == NULL) {
1369	DBG("ROUTER Wrong ctrl2\n");
1370	return ROUTER_ERR_EINVAL;
1371	}
1372
1373	*ctrl2 = REG_READ(&priv->regs->pctrl2[port]);
1374	return ROUTER_ERR_OK;
1375	}
1376
1377	/* Write Port Control Register */
1378	int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl)
1379	{
1380	return router_port_ctrl_rmw(d, port, NULL, mask, ctrl);
1381	}
1382
1383	/* Write Port Control2 Register */
1384	int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2)
1385	{
1386	return router_port_ctrl_rmw(d, port, NULL, mask, ctrl2);
1387	}
1388
1389	int router_port_treload_set(void *d, int port, uint32_t reload)
1390	{
1391	struct router_priv *priv = d;
1392	int error = router_check_port(d, port);
1393
1394	if (error)
1395	return error;
1396
1397	REG_WRITE(&priv->regs->treload[port], reload & PTIMER_RL);
1398
1399	return ROUTER_ERR_OK;
1400	}
1401
1402	int router_port_treload_get(void d, int port, uint32_t reload)
1403	{
1404	struct router_priv *priv = d;
1405	int error = router_check_port(d, port);
1406
1407	if (error)
1408	return error;
1409
1410	if (reload == NULL) {
1411	DBG("ROUTER Wrong reload pointer\n");
1412	return ROUTER_ERR_EINVAL;
1413	}
1414
1415	*reload = REG_READ(&priv->regs->treload[port]) & PTIMER_RL;
1416
1417	return ROUTER_ERR_OK;
1418	}
1419
1420	int router_port_maxplen_set(void *d, int port, uint32_t length)
1421	{
1422	struct router_priv *priv = d;
1423	int error = router_check_port(d, port);
1424
1425	if (error)
1426	return error;
1427
1428	REG_WRITE(&priv->regs->maxplen[port], length & MAXPLEN_ML);
1429
1430	return ROUTER_ERR_OK;
1431	}
1432
1433	int router_port_maxplen_get(void d, int port, uint32_t length)
1434	{
1435	struct router_priv *priv = d;
1436	int error = router_check_port(d, port);
1437
1438	if (error)
1439	return error;
1440
1441	if (length == NULL) {
1442	DBG("ROUTER Wrong length pointer\n");
1443	return ROUTER_ERR_EINVAL;
1444	}
1445
1446	*length = REG_READ(&priv->regs->maxplen[port]);
1447
1448	return ROUTER_ERR_OK;
1449	}
1450
1451	/* Get Port Link Status */
1452	int router_port_link_status(void *d, int port)
1453	{
1454	struct router_priv *priv = d;
1455	int error = router_check_port(d, port);
1456
1457	if (error)
1458	return error;
1459
1460	return ((REG_READ(&priv->regs->psts[port]) & PSTS_LS) >> PSTS_LS_BIT);
1461	}
1462
1463	int router_port_disable(void *d, int port)
1464	{
1465	return router_port_ctrl_rmw(d, port, NULL, PCTRL_DI, PCTRL_DI);
1466	}
1467
1468	int router_port_enable(void *d, int port)
1469	{
1470	return router_port_ctrl_rmw(d, port, NULL, PCTRL_DI, 0);
1471	}
1472
1473	int router_port_link_stop(void *d, int port)
1474	{
1475	return router_port_ctrl_rmw(d, port, NULL, PCTRL_LD \| PCTRL_LS, PCTRL_LD);
1476	}
1477
1478	int router_port_link_start(void *d, int port)
1479	{
1480	return router_port_ctrl_rmw(d, port, NULL, PCTRL_LD \| PCTRL_LS, PCTRL_LS);
1481	}
1482
1483	int router_port_link_receive_spill(void *d, int port)
1484	{
1485	struct router_priv *priv = d;
1486	unsigned int ctrl;
1487	SPIN_IRQFLAGS(irqflags);
1488	int error = router_check_port(d, port);
1489
1490	if (error)
1491	return error;
1492
1493	SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1494
1495	ctrl = REG_READ(&priv->regs->pctrl[port]);
1496	REG_WRITE(&priv->regs->pctrl[port], (ctrl\| (PCTRL_RS)));
1497
1498	/* Wait until the spill is done */
1499	while(REG_READ(&priv->regs->pctrl[port]) & PCTRL_RS) {};
1500
1501	SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1502
1503	return ROUTER_ERR_OK;
1504	}
1505
1506	int router_port_link_transmit_reset(void *d, int port)
1507	{
1508	struct router_priv *priv = d;
1509	unsigned int ctrl;
1510	SPIN_IRQFLAGS(irqflags);
1511	int error = router_check_port(d, port);
1512
1513	if (error)
1514	return error;
1515
1516	SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1517
1518	ctrl = REG_READ(&priv->regs->pctrl[port]);
1519	REG_WRITE(&priv->regs->pctrl[port], (ctrl\| (PCTRL_TF)));
1520
1521	/* Wait until the spill is done */
1522	while(REG_READ(&priv->regs->pctrl[port]) & PCTRL_TF) {};
1523
1524	SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1525
1526	return ROUTER_ERR_OK;
1527	}
1528
1529	int router_port_cred_get(void d, int port, uint32_t cred)
1530	{
1531	struct router_priv *priv = d;
1532	int error = router_check_port(d, port);
1533
1534	if (error)
1535	return error;
1536
1537	if (cred == NULL) {
1538	DBG("ROUTER Wrong cred pointer\n");
1539	return ROUTER_ERR_EINVAL;
1540	}
1541
1542	*cred = REG_READ(&priv->regs->credcnt[port]);
1543	return ROUTER_ERR_OK;
1544	}
1545
1546	int router_instance_set(void *d, uint8_t instance)
1547	{
1548	struct router_priv *priv = d;
1549	int error = router_check_open(d);
1550
1551	if (error)
1552	return error;
1553
1554	REG_WRITE(&priv->regs->ver, (instance << VER_ID_BIT) & VER_ID);
1555	return ROUTER_ERR_OK;
1556	}
1557
1558	int router_idiv_set(void *d, uint8_t idiv)
1559	{
1560	struct router_priv *priv = d;
1561	int error = router_check_open(d);
1562
1563	if (error)
1564	return error;
1565
1566	REG_WRITE(&priv->regs->idiv, (idiv << IDIV_ID_BIT) & IDIV_ID);
1567	return ROUTER_ERR_OK;
1568	}
1569
1570	int router_tpresc_set(void *d, uint32_t prescaler)
1571	{
1572	struct router_priv *priv = d;
1573	int error = router_check_open(d);
1574
1575	if (error)
1576	return error;
1577
1578	REG_WRITE(&priv->regs->tprescaler,
1579	(prescaler << PRESCALER_RL_BIT) & PRESCALER_RL);
1580	return ROUTER_ERR_OK;
1581	}
1582
1583	int router_instance_get(void d, uint8_t instance)
1584	{
1585	struct router_priv *priv = d;
1586	int error = router_check_open(d);
1587
1588	if (error)
1589	return error;
1590
1591	if (instance == NULL) {
1592	DBG("ROUTER Wrong instance pointer\n");
1593	return ROUTER_ERR_EINVAL;
1594	}
1595
1596	*instance = REG_READ(&priv->regs->ver);
1597
1598	return ROUTER_ERR_OK;
1599	}
1600
1601	int router_idiv_get(void d, uint8_t idiv)
1602	{
1603	struct router_priv *priv = d;
1604	int error = router_check_open(d);
1605
1606	if (error)
1607	return error;
1608
1609	if (idiv == NULL) {
1610	DBG("ROUTER Wrong idiv pointer\n");
1611	return ROUTER_ERR_EINVAL;
1612	}
1613
1614	*idiv = REG_READ(&priv->regs->idiv);
1615
1616	return ROUTER_ERR_OK;
1617	}
1618
1619	int router_tpresc_get(void d, uint32_t prescaler)
1620	{
1621	struct router_priv *priv = d;
1622	int error = router_check_open(d);
1623
1624	if (error)
1625	return error;
1626
1627	if (prescaler == NULL) {
1628	DBG("ROUTER Wrong prescaler pointer\n");
1629	return ROUTER_ERR_EINVAL;
1630	}
1631
1632	*prescaler = REG_READ(&priv->regs->tprescaler);
1633
1634	return ROUTER_ERR_OK;
1635	}
1636
1637	int router_cfgsts_set(void *d, uint32_t cfgsts)
1638	{
1639	struct router_priv *priv = d;
1640	int error = router_check_open(d);
1641
1642	if (error)
1643	return error;
1644
1645	REG_WRITE(&priv->regs->cfgsts, cfgsts);
1646
1647	return ROUTER_ERR_OK;
1648	}
1649
1650	int router_cfgsts_get(void d, uint32_t cfgsts)
1651	{
1652	struct router_priv *priv = d;
1653	int error = router_check_open(d);
1654
1655	if (error)
1656	return error;
1657
1658	if (cfgsts == NULL) {
1659	DBG("ROUTER Wrong cfgsts pointer\n");
1660	return ROUTER_ERR_EINVAL;
1661	}
1662
1663	*cfgsts = REG_READ(&priv->regs->cfgsts);
1664
1665	return ROUTER_ERR_OK;
1666	}
1667
1668	int router_tc_enable(void *d)
1669	{
1670	struct router_priv *priv = d;
1671	int error = router_check_open(d);
1672
1673	if (error)
1674	return error;
1675
1676	REG_WRITE(&priv->regs->timecode, TC_EN);
1677
1678	return ROUTER_ERR_OK;
1679	}
1680
1681	int router_tc_disable(void *d)
1682	{
1683	struct router_priv *priv = d;
1684	int error = router_check_open(d);
1685
1686	if (error)
1687	return error;
1688
1689	REG_WRITE(&priv->regs->timecode, 0);
1690
1691	return ROUTER_ERR_OK;
1692	}
1693
1694	int router_tc_reset(void *d)
1695	{
1696	struct router_priv *priv = d;
1697	unsigned int tc;
1698	int error = router_check_open(d);
1699
1700	if (error)
1701	return error;
1702
1703	tc = REG_READ(&priv->regs->timecode);
1704	REG_WRITE(&priv->regs->timecode, tc \| TC_RE);
1705
1706	return ROUTER_ERR_OK;
1707	}
1708
1709	int router_tc_get(void *d)
1710	{
1711	struct router_priv *priv = d;
1712	int error = router_check_open(d);
1713
1714	if (error)
1715	return error;
1716
1717	return (REG_READ(&priv->regs->timecode) & (TC_CF \| TC_TC)) >> TC_TC_BIT;
1718	}
1719
1720	int router_interrupt_unmask(void *d, int options)
1721	{
1722	struct router_priv *priv = d;
1723	unsigned int mask;
1724	int error = router_check_open(d);
1725
1726	if (error)
1727	return error;
1728
1729	#ifdef THREAD_SAFE
1730	/* Take device lock - Wait until we get semaphore */
1731	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1732	!= RTEMS_SUCCESSFUL) {
1733	DBG("ROUTER Sempahore failed\n");
1734	return ROUTER_ERR_ERROR;
1735	}
1736	#endif
1737
1738	/* Unmask interrupts in ROTUER */
1739	/* Get previous mask */
1740	mask = REG_READ(&priv->regs->imask);
1741
1742	/* Clear previous interrupts*/
1743	REG_WRITE(&priv->regs->pip, 0xffffffff);
1744
1745	/* Set new mask */
1746	REG_WRITE(&priv->regs->imask, mask \| options);
1747
1748	#ifdef THREAD_SAFE
1749	/* Unlock dev */
1750	rtems_semaphore_release(priv->sem);
1751	#endif
1752
1753	return ROUTER_ERR_OK;
1754	}
1755
1756	int router_interrupt_mask(void *d, int options)
1757	{
1758	struct router_priv *priv = d;
1759	unsigned int mask;
1760	int error = router_check_open(d);
1761
1762	if (error)
1763	return error;
1764
1765	#ifdef THREAD_SAFE
1766	/* Take device lock - Wait until we get semaphore */
1767	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1768	!= RTEMS_SUCCESSFUL) {
1769	DBG("ROUTER Sempahore failed\n");
1770	return ROUTER_ERR_ERROR;
1771	}
1772	#endif
1773
1774	/* Mask interrupts in ROTUER */
1775	/* Get previous mask */
1776	mask = REG_READ(&priv->regs->imask);
1777
1778	/* Clear previous interrupts*/
1779	REG_WRITE(&priv->regs->pip, 0xffffffff);
1780
1781	/* Set new mask */
1782	REG_WRITE(&priv->regs->imask, mask & ~(options));
1783
1784	#ifdef THREAD_SAFE
1785	/* Unlock dev */
1786	rtems_semaphore_release(priv->sem);
1787	#endif
1788
1789	return ROUTER_ERR_OK;
1790	}
1791
1792	int router_port_interrupt_unmask(void *d, int port)
1793	{
1794	struct router_priv *priv = d;
1795	unsigned int mask;
1796	int error = router_check_port(d, port);
1797
1798	if (error)
1799	return error;
1800
1801	#ifdef THREAD_SAFE
1802	/* Take device lock - Wait until we get semaphore */
1803	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1804	!= RTEMS_SUCCESSFUL) {
1805	DBG("ROUTER Sempahore failed\n");
1806	return ROUTER_ERR_ERROR;
1807	}
1808	#endif
1809
1810	/* Unmask interrupts in ROTUER */
1811	/* Get previous mask */
1812	mask = REG_READ(&priv->regs->ipmask);
1813
1814	/* Clear previous interrupts*/
1815	REG_WRITE(&priv->regs->pip, (0x1 << port));
1816
1817	/* Set new mask */
1818	REG_WRITE(&priv->regs->ipmask, mask \| (0x1 << port));
1819
1820	#ifdef THREAD_SAFE
1821	/* Unlock dev */
1822	rtems_semaphore_release(priv->sem);
1823	#endif
1824
1825	return ROUTER_ERR_OK;
1826	}
1827
1828	int router_port_interrupt_mask(void *d, int port)
1829	{
1830	struct router_priv *priv = d;
1831	unsigned int mask;
1832	int error = router_check_port(d, port);
1833
1834	if (error)
1835	return error;
1836
1837	#ifdef THREAD_SAFE
1838	/* Take device lock - Wait until we get semaphore */
1839	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1840	!= RTEMS_SUCCESSFUL) {
1841	DBG("ROUTER Sempahore failed\n");
1842	return ROUTER_ERR_ERROR;
1843	}
1844	#endif
1845
1846	/* Mask interrupts in ROTUER */
1847	/* Get previous mask */
1848	mask = REG_READ(&priv->regs->ipmask);
1849
1850	/* Clear previous interrupts*/
1851	REG_WRITE(&priv->regs->pip, (0x1 << port));
1852
1853	/* Set new mask */
1854	REG_WRITE(&priv->regs->ipmask, mask & ~(0x1 << port));
1855
1856	#ifdef THREAD_SAFE
1857	/* Unlock dev */
1858	rtems_semaphore_release(priv->sem);
1859	#endif
1860
1861	return ROUTER_ERR_OK;
1862	}
1863
1864	int router_reset(void *d)
1865	{
1866	struct router_priv *priv = d;
1867	int error = router_check_open(d);
1868
1869	if (error)
1870	return error;
1871
1872	/* Reset router */
1873	REG_WRITE(&priv->regs->cfgsts, RTRCFG_RE);
1874
1875	return ROUTER_ERR_OK;
1876	}
1877
1878	int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer,
1879	int options)
1880	{
1881	struct router_priv *priv = d;
1882	int error = router_check_distint_support(d);
1883
1884	if (error)
1885	return error;
1886
1887	#ifdef THREAD_SAFE
1888	/* Take device lock - Wait until we get semaphore */
1889	if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1890	!= RTEMS_SUCCESSFUL) {
1891	DBG("ROUTER Sempahore failed\n");
1892	return ROUTER_ERR_ERROR;
1893	}
1894	#endif
1895
1896	REG_WRITE(&priv->regs->icodegen, (options & ~(ICODEGEN_IN)) \|
1897	ICODEGEN_EN \| (intn & ICODEGEN_IN));
1898
1899	if (options & ICODEGEN_TE) {
1900	REG_WRITE(&priv->regs->aitimer, (aitimer & AITIMER_RL));
1901	}
1902
1903	#ifdef THREAD_SAFE
1904	/* Unlock dev */
1905	rtems_semaphore_release(priv->sem);
1906	#endif
1907
1908	return ROUTER_ERR_OK;
1909	}
1910
1911	int router_icodegen_disable(void *d)
1912	{
1913	struct router_priv *priv = d;
1914	int error = router_check_distint_support(d);
1915
1916	if (error)
1917	return error;
1918
1919	REG_WRITE(&priv->regs->icodegen, ICODEGEN_TE);
1920
1921	return ROUTER_ERR_OK;
1922	}
1923
1924	int router_isrctimer_set(void *d, uint32_t reloadvalue)
1925	{
1926	struct router_priv *priv = d;
1927	int error = router_check_distint_support(d);
1928
1929	if (error)
1930	return error;
1931
1932	/* Set ISRC TIMER */
1933	REG_WRITE(&priv->regs->isrctimer, (reloadvalue & (ISRCTIMER_RL)));
1934
1935	return ROUTER_ERR_OK;
1936	}
1937
1938	int router_isrtimer_set(void *d, uint32_t reloadvalue)
1939	{
1940	struct router_priv *priv = d;
1941	int error = router_check_distint_support(d);
1942
1943	if (error)
1944	return error;
1945
1946	/* Set ISR TIMER */
1947	REG_WRITE(&priv->regs->isrtimer, (reloadvalue & (ISRTIMER_RL)));
1948
1949	return ROUTER_ERR_OK;
1950	}
1951
1952	int router_isrctimer_get(void d, uint32_t reloadvalue)
1953	{
1954	struct router_priv *priv = d;
1955	int error = router_check_distint_support(d);
1956
1957	if (error)
1958	return error;
1959
1960	if (reloadvalue == NULL) {
1961	DBG("ROUTER Wrong reloadvalue pointer\n");
1962	return ROUTER_ERR_EINVAL;
1963	}
1964
1965	/* Set ISRC TIMER */
1966	*reloadvalue = REG_READ(&priv->regs->isrctimer) & (ISRCTIMER_RL);
1967
1968	return ROUTER_ERR_OK;
1969	}
1970
1971	int router_isrtimer_get(void d, uint32_t reloadvalue)
1972	{
1973	struct router_priv *priv = d;
1974	int error = router_check_distint_support(d);
1975
1976	if (error)
1977	return error;
1978
1979	if (reloadvalue == NULL) {
1980	DBG("ROUTER Wrong reloadvalue pointer\n");
1981	return ROUTER_ERR_EINVAL;
1982	}
1983
1984	/* Set ISR TIMER */
1985	*reloadvalue = REG_READ(&priv->regs->isrtimer) & (ISRTIMER_RL);
1986
1987	return ROUTER_ERR_OK;
1988	}

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source: rtems/bsps/sparc/shared/spw/grspw_router.c @ d60d303c

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