source: rtems/bsps/sparc/shared/spw/grspw_router.c @ a7267241

5
Last change on this file since a7267241 was a7267241, checked in by Sebastian Huber <sebastian.huber@…>, on 11/26/18 at 14:44:25

bsps/sparc: Add and use <grlib_impl.h>

Reduce copy and paste.
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Line 
1/* GRSPW ROUTER APB-Register Driver.
2 *
3 * COPYRIGHT (c) 2010-2017.
4 * Cobham Gaisler AB.
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 */
10
11#include <rtems.h>
12#include <rtems/libio.h>
13#include <rtems/bspIo.h>
14#include <stdio.h>
15#include <bsp.h>
16
17#include <drvmgr/drvmgr.h>
18#include <drvmgr/ambapp_bus.h>
19#include <bsp/grspw_router.h>
20
21#include <grlib_impl.h>
22
23//#define STATIC
24#define STATIC static
25
26#define UNUSED __attribute__((unused))
27
28//#define DEBUG 1
29
30#ifdef DEBUG
31#define DBG(x...) printf(x)
32#else
33#define DBG(x...)
34#endif
35
36#define THREAD_SAFE 1
37
38#define REG_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (unsigned int)(val))
39#define REG_READ(addr) (*(volatile unsigned int *)(addr))
40
41
42/*
43 * ROUTER RTPMAP register fields
44 */
45#define RTPMAP_PE (0x7fffffff << RTPMAP_PE_BIT)
46#define RTPMAP_PD (0x1 << RTPMAP_PD_BIT)
47
48#define RTPMAP_PE_BIT 1
49#define RTPMAP_PD_BIT 0
50
51/*
52 * ROUTER RTACTRL register fields
53 * DEFINED IN HEADER
54 */
55
56/*
57 * ROUTER PCTRL register fields
58 * DEFINED IN HEADER
59 */
60
61/*
62 * ROUTER PSTSCFG register fields
63 * DEFINED IN HEADER
64 */
65
66/*
67 * ROUTER PSTS register fields
68 * DEFINED IN HEADER
69 */
70
71/*
72 * ROUTER PTIMER register fields
73 */
74#define PTIMER_RL (0xffff << PTIMER_RL_BIT)
75
76#define PTIMER_RL_BIT 0
77
78/*
79 * ROUTER PCTRL2 register fields
80 * DEFINED IN HEADER
81 */
82
83/*
84 * ROUTER RTRCFG register fields
85 */
86#define RTRCFG_SP (0x1f << RTRCFG_SP_BIT)
87#define RTRCFG_AP (0x1f << RTRCFG_AP_BIT)
88#define RTRCFG_FP (0x1f << RTRCFG_FP_BIT)
89#define RTRCFG_SR (0x1 << RTRCFG_SR_BIT)
90#define RTRCFG_PE (0x1 << RTRCFG_PE_BIT)
91#define RTRCFG_IC (0x1 << RTRCFG_IC_BIT)
92#define RTRCFG_IS (0x1 << RTRCFG_IS_BIT)
93#define RTRCFG_IP (0x1 << RTRCFG_IP_BIT)
94#define RTRCFG_AI (0x1 << RTRCFG_AI_BIT)
95#define RTRCFG_AT (0x1 << RTRCFG_AT_BIT)
96#define RTRCFG_IE (0x1 << RTRCFG_IE_BIT)
97#define RTRCFG_RE (0x1 << RTRCFG_RE_BIT)
98#define RTRCFG_EE (0x1 << RTRCFG_EE_BIT)
99#define RTRCFG_LS (0x1 << RTRCFG_LS_BIT)
100#define RTRCFG_SA (0x1 << RTRCFG_SA_BIT)
101#define RTRCFG_TF (0x1 << RTRCFG_TF_BIT)
102#define RTRCFG_ME (0x1 << RTRCFG_ME_BIT)
103#define RTRCFG_TA (0x1 << RTRCFG_TA_BIT)
104#define RTRCFG_PP (0x1 << RTRCFG_PP_BIT)
105#define RTRCFG_WCLEAR (RTRCFG_ME)
106
107#define RTRCFG_SP_BIT 27
108#define RTRCFG_AP_BIT 22
109#define RTRCFG_FP_BIT 17
110#define RTRCFG_SR_BIT 15
111#define RTRCFG_PE_BIT 14
112#define RTRCFG_IC_BIT 13
113#define RTRCFG_IS_BIT 12
114#define RTRCFG_IP_BIT 11
115#define RTRCFG_AI_BIT 10
116#define RTRCFG_AT_BIT 9
117#define RTRCFG_IE_BIT 8
118#define RTRCFG_RE_BIT 7
119#define RTRCFG_EE_BIT 6
120#define RTRCFG_LS_BIT 5
121#define RTRCFG_SA_BIT 4
122#define RTRCFG_TF_BIT 3
123#define RTRCFG_ME_BIT 2
124#define RTRCFG_TA_BIT 1
125#define RTRCFG_PP_BIT 0
126
127/*
128 * ROUTER TC register fields
129 */
130#define TC_RE (0x3f << TC_RE_BIT)
131#define TC_EN (0x3f << TC_EN_BIT)
132#define TC_CF (0x3f << TC_CF_BIT)
133#define TC_TC (0x3f << TC_TC_BIT)
134
135#define TC_RE_BIT 9
136#define TC_EN_BIT 8
137#define TC_CF_BIT 6
138#define TC_TC_BIT 0
139
140/*
141 * ROUTER VER register fields
142 */
143#define VER_MA (0xff << VER_MA_BIT)
144#define VER_MI (0xff << VER_MI_BIT)
145#define VER_PA (0xff << VER_PA_BIT)
146#define VER_ID (0xff << VER_ID_BIT)
147
148#define VER_MA_BIT 24
149#define VER_MI_BIT 16
150#define VER_PA_BIT 8
151#define VER_ID_BIT 0
152
153/*
154 * ROUTER IDIV register fields
155 */
156#define IDIV_ID (0xff << IDIV_ID_BIT)
157
158#define IDIV_ID_BIT 0
159
160/*
161 * ROUTER CFGWE register fields
162 */
163#define CFGWE_WE (0x1 << CFGWE_WE_BIT)
164
165#define CFGWE_WE_BIT 0
166
167/*
168 * ROUTER PRESCALER register fields
169 */
170#define PRESCALER_RL (0xffff << PRESCALER_RL_BIT)
171
172#define PRESCALER_RL_BIT 0
173
174/*
175 * ROUTER IMASK register fields
176 * DEFINED IN HEADER
177 */
178
179/*
180 * ROUTER ICODEGEN register fields
181 * DEFINED IN HEADER
182 */
183
184/*
185 * ROUTER ISRTIMER register fields
186 */
187#define ISRTIMER_RL (0xffff << ISRTIMER_RL_BIT)
188
189#define ISRTIMER_RL_BIT 0
190
191/*
192 * ROUTER AITIMER register fields
193 */
194#define AITIMER_RL (0xffff << AITIMER_RL_BIT)
195
196#define AITIMER_RL_BIT 0
197
198/*
199 * ROUTER ISRCTIMER register fields
200 */
201#define ISRCTIMER_RL (0x1f << ISRCTIMER_RL_BIT)
202
203#define ISRCTIMER_RL_BIT 0
204
205/*
206 * ROUTER CAP register fields
207 */
208#define CAP_AF (0x3 << CAP_AF_BIT)
209#define CAP_PF (0x7 << CAP_PF_BIT)
210#define CAP_RM (0x7 << CAP_RM_BIT)
211#define CAP_AS (0x1 << CAP_AS_BIT)
212#define CAP_AX (0x1 << CAP_AX_BIT)
213#define CAP_DP (0x1 << CAP_DP_BIT)
214#define CAP_ID (0x1 << CAP_ID_BIT)
215#define CAP_SD (0x1 << CAP_SD_BIT)
216#define CAP_PC (0x1f << CAP_PC_BIT)
217#define CAP_CC (0x1f << CAP_CC_BIT)
218
219#define CAP_AF_BIT 24
220#define CAP_PF_BIT 29
221#define CAP_RM_BIT 16
222#define CAP_AS_BIT 14
223#define CAP_AX_BIT 13
224#define CAP_DP_BIT 12
225#define CAP_ID_BIT 11
226#define CAP_SD_BIT 10
227#define CAP_PC_BIT 4
228#define CAP_CC_BIT 0
229
230/*
231 * ROUTER PNPVEND register fields
232 */
233#define PNPVEND_VI (0xffff << PNPVEND_VI_BIT)
234#define PNPVEND_PI (0xffff << PNPVEND_PI_BIT)
235
236#define PNPVEND_VI_BIT 16
237#define PNPVEND_PI_BIT 0
238
239/*
240 * ROUTER PNPUVEND register fields
241 */
242#define PNPUVEND_VI (0xffff << PNPUVEND_VI_BIT)
243#define PNPUVEND_PI (0xffff << PNPUVEND_PI_BIT)
244
245#define PNPUVEND_VI_BIT 16
246#define PNPUVEND_PI_BIT 0
247
248/*
249 * ROUTER MAXPLEN register fields
250 */
251#define MAXPLEN_ML (0xffffff << MAXPLEN_ML_BIT)
252
253#define MAXPLEN_ML_BIT 0
254
255/*
256 * ROUTER CHARO register fields
257 */
258#define CHARO_OR (0x1 << CHARO_OR_BIT)
259#define CHARO_CC (0x7fffffff << CHARO_CC_BIT)
260
261#define CHARO_OR_BIT 31
262#define CHARO_CC_BIT 0
263
264/*
265 * ROUTER CHARI register fields
266 */
267#define CHARI_OR (0x1 << CHARI_OR_BIT)
268#define CHARI_CC (0x7fffffff << CHARI_CC_BIT)
269
270#define CHARI_OR_BIT 31
271#define CHARI_CC_BIT 0
272
273/*
274 * ROUTER PKTO register fields
275 */
276#define PKTO_OR (0x1 << PKTO_OR_BIT)
277#define PKTO_CC (0x7fffffff << PKTO_CC_BIT)
278
279#define PKTO_OR_BIT 31
280#define PKTO_CC_BIT 0
281
282/*
283 * ROUTER PKTI register fields
284 */
285#define PKTI_OR (0x1 << PKTI_OR_BIT)
286#define PKTI_CC (0x7fffffff << PKTI_CC_BIT)
287
288#define PKTI_OR_BIT 31
289#define PKTI_CC_BIT 0
290
291/*
292 * ROUTER CRED register fields
293 */
294#define CRED_OC (0x3f << CRED_OC_BIT)
295#define CRED_IC (0x3f << CRED_IC_BIT)
296
297#define CRED_OC_BIT 6
298#define CRED_IC_BIT 0
299
300/*
301 * ROUTER RTRCOMB register fields
302 */
303#define RTRCOMB_SR (0x1 << RTRCOMB_SR_BIT)
304#define RTRCOMB_EN (0x1 << RTRCOMB_EN_BIT)
305#define RTRCOMB_PR (0x1 << RTRCOMB_PR_BIT)
306#define RTRCOMB_HD (0x1 << RTRCOMB_HD_BIT)
307#define RTRCOMB_PE (0x7ffff << RTRCOMB_PE_BIT)
308#define RTRCOMB_PD (0x1 << RTRCOMB_PD_BIT)
309
310#define RTRCOMB_SR_BIT 31
311#define RTRCOMB_EN_BIT 30
312#define RTRCOMB_PR_BIT 29
313#define RTRCOMB_HD_BIT 28
314#define RTRCOMB_PE_BIT 1
315#define RTRCOMB_PD_BIT 0
316
317struct router_regs {
318        unsigned int resv1;             /* 0x000 */
319        unsigned int psetup[255];       /* 0x004 */
320        unsigned int resv2;             /* 0x400 */
321        unsigned int routes[255];       /* 0x404 */
322        unsigned int pctrl[32];         /* 0x800 */
323        unsigned int psts[32];          /* 0x880 */
324        unsigned int treload[32];       /* 0x900 */
325        unsigned int pctrl2[32];        /* 0x980 */
326        unsigned int cfgsts;            /* 0xA00 */
327        unsigned int timecode;          /* 0xA04 */
328        unsigned int ver;               /* 0xA08 */
329        unsigned int idiv;              /* 0xA0C */
330        unsigned int cfgwe;             /* 0xA10 */
331        unsigned int tprescaler;        /* 0xA14 */
332        unsigned int imask;             /* 0xA18 */
333        unsigned int ipmask;            /* 0xA1C */
334        unsigned int pip;               /* 0xA20 */
335        unsigned int icodegen;          /* 0xA24 */
336        unsigned int isr0;              /* 0xA28 */
337        unsigned int isr1;              /* 0xA2C */
338        unsigned int isrtimer;          /* 0xA30 */
339        unsigned int aitimer;           /* 0xA34 */
340        unsigned int isrctimer;         /* 0xA38 */
341        unsigned int resv4;             /* 0xA3C */
342        unsigned int lrunsts;           /* 0xA40 */
343        unsigned int cap;               /* 0xA44 */
344        unsigned int resv5[111];        /* 0xA48 */
345        unsigned int charo[31];         /* 0xC04 */ /* TODO check GR718 */
346        unsigned int resv6;             /* 0xC80 */
347        unsigned int chari[31];         /* 0xC84 */
348        unsigned int resv7;             /* 0xD00 */
349        unsigned int pkto[31];          /* 0xD04 */
350        unsigned int resv8;             /* 0xD80 */
351        unsigned int pkti[31];          /* 0xD84 */
352        unsigned int maxplen[32];               /* 0xE00 */
353        unsigned int resv9;             /* 0xE80 */
354        unsigned int credcnt[31];       /* 0xE84 */
355        unsigned int resv10[64];        /* 0xF00 */
356        unsigned int resv11;            /* 0x1000 */
357        unsigned int rtcomb[255];       /* 0x1004 */
358};
359
360struct router_priv {
361        struct drvmgr_dev *dev;
362
363        /* ROUTER control registers */
364        struct router_regs *regs;
365
366        #ifdef THREAD_SAFE
367        /* ROUTER semaphore */
368        rtems_id sem;
369        #endif
370
371        /* ROUTER driver register */
372        char devname[9];
373        int index;                      /* Index in order it was probed */
374
375        int minor;
376        int open;
377        struct router_hw_info hwinfo;
378        int nports;
379        int irq_init;
380
381        SPIN_DECLARE(plock[32])
382
383};
384
385int router_count = 0;
386static struct router_priv *priv_tab[ROUTER_MAX];
387
388/* Driver prototypes */
389
390STATIC int router_init(struct router_priv *priv);
391STATIC void router_hwinfo(struct router_priv *priv,
392                          struct router_hw_info *hwinfo);
393STATIC int router_acontrol_set(struct router_priv *priv,
394                struct router_route_acontrol *control);
395STATIC int router_acontrol_get(struct router_priv *priv,
396                struct router_route_acontrol *control);
397STATIC int router_portmap_set(struct router_priv *priv,
398                struct router_route_portmap *pmap);
399STATIC int router_portmap_get(struct router_priv *priv,
400                struct router_route_portmap *pmap);
401
402/* -IRQ handler */
403void router_isr(void *arg);
404
405int router_init2(struct drvmgr_dev *dev);
406
407struct drvmgr_drv_ops router_ops =
408{
409        .init = {NULL,  router_init2, NULL, NULL},
410        .remove = NULL,
411        .info = NULL
412};
413
414struct amba_dev_id router_ids[] =
415{
416        {VENDOR_GAISLER, GAISLER_SPW_ROUTER},
417        {0, 0}          /* Mark end of table */
418};
419
420struct amba_drv_info router_drv_info =
421{
422        {
423                DRVMGR_OBJ_DRV,                 /* Driver */
424                NULL,                           /* Next driver */
425                NULL,                           /* Device list */
426                DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID,/* Driver ID */
427                "ROUTER_DRV",                   /* Driver Name */
428                DRVMGR_BUS_TYPE_AMBAPP,         /* Bus Type */
429                &router_ops,
430                NULL,                           /* Funcs */
431                0,                              /* No devices yet */
432                sizeof(struct router_priv),     /* Let DRVMGR allocate for us */
433        },
434        &router_ids[0],
435};
436
437void router_register_drv (void)
438{
439        DBG("Registering SPW ROUTER driver\n");
440        drvmgr_drv_register(&router_drv_info.general);
441}
442
443STATIC void router_hwinfo(struct router_priv *priv,
444                struct router_hw_info *hwinfo)
445{
446        unsigned int tmp;
447
448        /* Find router info */
449        tmp = REG_READ(&priv->regs->cfgsts);
450        hwinfo->nports_spw   = (tmp & RTRCFG_SP) >> RTRCFG_SP_BIT;
451        hwinfo->nports_amba  = (tmp & RTRCFG_AP) >> RTRCFG_AP_BIT;
452        hwinfo->nports_fifo  = (tmp & RTRCFG_FP) >> RTRCFG_FP_BIT;
453        hwinfo->srouting     = (tmp & RTRCFG_SR) >> RTRCFG_SR_BIT;
454        hwinfo->pnp_enable   = (tmp & RTRCFG_PE) >> RTRCFG_PE_BIT;
455        hwinfo->timers_avail = (tmp & RTRCFG_TA) >> RTRCFG_TA_BIT;
456        hwinfo->pnp_avail    = (tmp & RTRCFG_PP) >> RTRCFG_PP_BIT;
457
458        tmp = REG_READ(&priv->regs->ver);
459        hwinfo->ver_major = (tmp & VER_MA) >> VER_MA_BIT;
460        hwinfo->ver_minor = (tmp & VER_MI) >> VER_MI_BIT;
461        hwinfo->ver_patch = (tmp & VER_PA) >> VER_PA_BIT;
462        hwinfo->iid       = (tmp & VER_ID) >> VER_ID_BIT;
463
464        /* Find router capabilities */
465        tmp = REG_READ(&priv->regs->cap);
466        hwinfo->amba_port_fifo_size = 4 << ((tmp & CAP_AF) >> CAP_AF_BIT);
467        hwinfo->spw_port_fifo_size = 16 << ((tmp & CAP_PF) >> CAP_PF_BIT);
468        hwinfo->rmap_maxdlen = 4 << ((tmp & CAP_RM) >> CAP_RM_BIT);
469        hwinfo->aux_async = (tmp & CAP_AS) >> CAP_AS_BIT;
470        hwinfo->aux_dist_int_support = (tmp & CAP_AX) >> CAP_AX_BIT;
471        hwinfo->dual_port_support = (tmp & CAP_ID) >> CAP_ID_BIT;
472        hwinfo->dist_int_support = (tmp & CAP_DP) >> CAP_DP_BIT;
473        hwinfo->spwd_support = (tmp & CAP_SD) >> CAP_SD_BIT;
474        hwinfo->pktcnt_support = (tmp & CAP_PC) >> CAP_PC_BIT;
475        hwinfo->charcnt_support = (tmp & CAP_CC) >> CAP_CC_BIT;
476}
477
478STATIC void router_hwinfo_print(struct router_hw_info *hwinfo)
479{
480        DBG(" -PORTS= SPW: %d, AMBA: %d, FIFO: %d\n", hwinfo->nports_spw,
481                        hwinfo->nports_amba, hwinfo->nports_fifo);
482        DBG(" -Static routing: %s, Timers: %s\n",
483                        (hwinfo->srouting?"Enabled":"Disabled"),
484                        (hwinfo->timers_avail?"Available":"N/A"));
485        DBG(" -PnP: %s, %s\n",
486                        (hwinfo->pnp_avail?"Available":"N/A"),
487                        (hwinfo->pnp_enable?"Enabled":"Disabled"));
488        DBG(" -Version= Major: 0x%02x, Minor: 0x%02x, Patch: 0x%02x, ID: 0x%02x\n",
489                        hwinfo->ver_major, hwinfo->ver_minor,
490                        hwinfo->ver_patch, hwinfo->iid);
491        DBG(" -Aux: %s, AuxDistInt: %s, DistInt: %s, SPWD: %s, PKTCNT: %s, "
492                "CHARCNT: %s\n",
493                        (hwinfo->aux_async?"Async":"Sync"),
494                        (hwinfo->aux_dist_int_support?"Supported":"N/A"),
495                        (hwinfo->dist_int_support?"Supported":"N/A"),
496                        (hwinfo->spwd_support?"Supported":"N/A"),
497                        (hwinfo->pktcnt_support?"Supported":"N/A"),
498                        (hwinfo->charcnt_support?"Supported":"N/A"));
499}
500
501STATIC int router_acontrol_set(struct router_priv *priv,
502                struct router_route_acontrol *control)
503{
504        int i;
505        for (i=0; i<31; i++) {
506                REG_WRITE(&priv->regs->routes[i], control->control[i]);
507        }
508        for (i=0; i<224; i++) {
509                REG_WRITE(&priv->regs->routes[i+31], control->control_logical[i]);
510        }
511        return ROUTER_ERR_OK;
512}
513
514STATIC int router_acontrol_get(struct router_priv *priv,
515                struct router_route_acontrol *control)
516{
517        int i;
518        for (i=0; i<31; i++) {
519                control->control[i] = REG_READ(&priv->regs->routes[i]);
520        }
521        for (i=0; i<224; i++) {
522                control->control_logical[i] = REG_READ(&priv->regs->routes[i+31]);
523        }
524        return ROUTER_ERR_OK;
525}
526
527STATIC int router_portmap_set(struct router_priv *priv,
528                struct router_route_portmap *pmap)
529{
530        int i;
531        for (i=0; i<31; i++) {
532                REG_WRITE(&priv->regs->psetup[i], pmap->pmap[i]);
533        }
534        for (i=0; i<224; i++) {
535                REG_WRITE(&priv->regs->psetup[i+31], pmap->pmap_logical[i]);
536        }
537        return ROUTER_ERR_OK;
538}
539
540STATIC int router_portmap_get(struct router_priv *priv,
541                struct router_route_portmap *pmap)
542{
543        int i;
544        for (i=0; i<31; i++) {
545                pmap->pmap[i] = REG_READ(&priv->regs->psetup[i]);
546        }
547        for (i=0; i<224; i++) {
548                pmap->pmap_logical[i] = REG_READ(&priv->regs->psetup[i+31]);
549        }
550        return ROUTER_ERR_OK;
551}
552
553STATIC int router_init(struct router_priv *priv)
554{
555        #ifdef THREAD_SAFE
556        int i;
557
558        /* Device Semaphore created with count = 1 */
559        if (rtems_semaphore_create(
560                        rtems_build_name('S', 'R', 'O', '0' + priv->index), 1,
561                        RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE | \
562                        RTEMS_NO_INHERIT_PRIORITY | RTEMS_LOCAL | \
563                        RTEMS_NO_PRIORITY_CEILING, 0, &priv->sem) != RTEMS_SUCCESSFUL) {
564                return DRVMGR_FAIL;
565        }
566        #endif
567
568        /* Find router info */
569        router_hwinfo(priv, &priv->hwinfo);
570
571        priv->open = 0;
572        /* Number of ports has to consider the configuration port (1 + SPW + AMBA + FIFO) */
573        priv->nports = 1 + priv->hwinfo.nports_spw + priv->hwinfo.nports_amba +
574                priv->hwinfo.nports_fifo;
575        if ((priv->nports < 2) || (priv->nports > 32)) {
576                return DRVMGR_EIO;
577        }
578
579        #ifdef THREAD_SAFE
580        /* Init port spin-lock memory structures */
581        for (i=0; i<priv->nports; i++) {
582                SPIN_INIT(&priv->plock[i],"portlock");
583        }
584        #endif
585
586        /* DEBUG print */
587        DBG("SPW ROUTER[%d] with following capabilities:\n", priv->index);
588        router_hwinfo_print(&priv->hwinfo);
589
590        return DRVMGR_OK;
591}
592
593int router_init2(struct drvmgr_dev *dev)
594{
595        struct router_priv *priv = dev->priv;
596        struct amba_dev_info *ambadev;
597        struct ambapp_core *pnpinfo;
598        unsigned int tmp;
599        int i;
600        int status;
601
602        DBG("SPW ROUTER[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
603
604        if (router_count >= ROUTER_MAX) {
605                return DRVMGR_ENORES;
606        }
607
608        if (priv == NULL) {
609                return DRVMGR_NOMEM;
610        }
611        priv->dev = dev;
612
613        /* Get device information from AMBA PnP information */
614        ambadev = (struct amba_dev_info *)priv->dev->businfo;
615        if (ambadev == NULL) {
616                return DRVMGR_FAIL;
617        }
618        pnpinfo = &ambadev->info;
619        priv->regs = (struct router_regs *)pnpinfo->ahb_slv->start[0];
620        priv->minor = dev->minor_drv;
621
622        /* Initilize driver struct */
623        status = router_init(priv);
624        if (status != DRVMGR_OK) {
625                return status;
626        }
627
628        /* Startup Action:
629         *  - Clear interrupts
630         *  - Mask interrupts
631         */
632
633        /* Mask interrupts in ROTUER */
634        REG_WRITE(&priv->regs->imask,0);
635        REG_WRITE(&priv->regs->ipmask,0);
636
637        /* Clear interrupts in ROTUER */
638        REG_WRITE(&priv->regs->pip,0xffffffff);
639
640        /* Clear errors in router and ports */
641        tmp = REG_READ(&priv->regs->cfgsts);
642        REG_WRITE(&priv->regs->cfgsts, tmp | RTRCFG_WCLEAR);
643        tmp = REG_READ(&priv->regs->psts[0]);
644        REG_WRITE(&priv->regs->psts[0], (tmp & PSTSCFG_WCLEAR) | PSTSCFG_WCLEAR2);
645        for (i=1; i<priv->nports; i++) {
646                tmp = REG_READ(&priv->regs->psts[i]);
647                REG_WRITE(&priv->regs->psts[i], tmp & PSTS_WCLEAR);
648        }
649
650        /* Register driver internally */
651        priv->index = router_count;
652        priv_tab[priv->index] = priv;
653        router_count++;
654
655        /* Device name */
656        sprintf(priv->devname, "router%d", priv->index);
657
658        return DRVMGR_OK;
659}
660
661void *router_open(unsigned int dev_no)
662{
663        struct router_priv *priv, *ret;
664
665        if (dev_no >= router_count) {
666                DBG("ROUTER Wrong index %u\n", dev_no);
667                return NULL;
668        }
669
670        priv = priv_tab[dev_no];
671
672        if (priv == NULL) {
673                DBG("ROUTER Device not initialized\n");
674                return NULL;
675        }
676
677        #ifdef THREAD_SAFE
678        /* Take device lock - Wait until we get semaphore */
679        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
680                        != RTEMS_SUCCESSFUL) {
681                DBG("ROUTER Sempahore failed\n");
682                return NULL;
683        }
684        #endif
685
686        if (priv->open) {
687                DBG("ROUTER Device already opened\n");
688                ret = NULL;
689        } else {
690                /* Take the device */
691                priv->open = 1;
692                ret = priv;
693        }
694        #ifdef THREAD_SAFE
695        /* Unlock dev */
696        rtems_semaphore_release(priv->sem);
697        #endif
698
699        return ret;
700}
701
702int router_close(void *d)
703{
704        struct router_priv *priv = d;
705        int ret;
706
707        if (priv == NULL) {
708                DBG("ROUTER Device not initialized\n");
709                return ROUTER_ERR_EINVAL;
710        }
711
712        #ifdef THREAD_SAFE
713        /* Take device lock - Wait until we get semaphore */
714        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
715                        != RTEMS_SUCCESSFUL) {
716                DBG("ROUTER Sempahore failed\n");
717                return ROUTER_ERR_ERROR;
718        }
719        #endif
720
721        if (priv->open == 0) {
722                DBG("ROUTER Device already closed\n");
723                ret = ROUTER_ERR_ERROR;
724        } else {
725                /* Mark not open */
726                priv->open = 0;
727                ret = ROUTER_ERR_OK;
728        }
729
730        #ifdef THREAD_SAFE
731        /* Unlock dev */
732        rtems_semaphore_release(priv->sem);
733        #endif
734
735        return ret;
736}
737
738STATIC int router_check_open(void *d)
739{
740        struct router_priv *priv = d;
741
742        if (priv == NULL) {
743                DBG("ROUTER Device not initialized\n");
744                return ROUTER_ERR_EINVAL;
745        }
746
747        if (priv->open == 0) {
748                DBG("ROUTER Device closed\n");
749                return ROUTER_ERR_ERROR;
750        }
751
752        return 0;
753}
754
755STATIC int router_check_port(void *d, int port)
756{
757        int ret = router_check_open(d);
758
759        if (ret == 0) {
760                struct router_priv *priv = d;
761                if((port < 0) || (port >= priv->nports)) {
762                        DBG("ROUTER wrong port\n");
763                        ret = ROUTER_ERR_EINVAL;
764                }
765        }
766
767        return ret;
768}
769
770STATIC int router_check_distint_support(void *d)
771{
772        int ret = router_check_open(d);
773
774        if (ret == 0) {
775                struct router_priv *priv = d;
776                if (priv->hwinfo.dist_int_support == 0) {
777                        DBG("ROUTER Dist interrupts not supported\n");
778                        ret = ROUTER_ERR_IMPLEMENTED;
779                }
780        }
781
782        return ret;
783}
784
785int router_hwinfo_get(void *d, struct router_hw_info *hwinfo)
786{
787        struct router_priv *priv = d;
788        int error = router_check_open(d);
789
790        if (error)
791                return error;
792
793        if (hwinfo == NULL) {
794                DBG("ROUTER Wrong pointer\n");
795                return ROUTER_ERR_EINVAL;
796        }
797
798        /* Get hwinfo */
799        router_hwinfo(priv, hwinfo);
800
801        return ROUTER_ERR_OK;
802}
803
804int router_print(void *d)
805{
806        struct router_priv *priv = d;
807        int error = router_check_open(d);
808
809        if (error)
810                return error;
811
812        /* DEBUG print */
813        DBG("Number of routers: %d\n", router_count);
814        DBG("SPW ROUTER[%d] with following capabilities:\n", priv->index);
815        router_hwinfo_print(&priv->hwinfo);
816
817        return ROUTER_ERR_OK;
818}
819
820/* Configure Router. Leave field NULL in order to skip configuration
821 */
822int router_config_set(void *d, struct router_config *cfg)
823{
824        struct router_priv *priv = d;
825        int error = router_check_open(d);
826
827        if (error)
828                return error;
829
830        if (cfg == NULL) {
831                DBG("ROUTER CFG wrong\n");
832                return ROUTER_ERR_EINVAL;
833        }
834
835        if ((cfg->flags & (ROUTER_FLG_TPRES|ROUTER_FLG_TRLD)) &&
836                        !priv->hwinfo.timers_avail) {
837                return ROUTER_ERR_IMPLEMENTED;
838        }
839
840        #ifdef THREAD_SAFE
841        /* Take device lock - Wait until we get semaphore */
842        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
843                        != RTEMS_SUCCESSFUL) {
844                DBG("ROUTER Sempahore failed\n");
845                return ROUTER_ERR_ERROR;
846        }
847        #endif
848
849        /* Write only configuration bits in Config register */
850        if (cfg->flags & ROUTER_FLG_CFG) {
851                REG_WRITE(&priv->regs->cfgsts, cfg->config & ~(RTRCFG_WCLEAR));
852        }
853
854        /* Write Instance ID to Version Register */
855        if (cfg->flags & ROUTER_FLG_IID) {
856                REG_WRITE(&priv->regs->ver, (cfg->iid << VER_ID_BIT) & VER_ID);
857        }
858
859        /* Write startup-clock-divisor Register */
860        if (cfg->flags & ROUTER_FLG_IDIV) {
861                REG_WRITE(&priv->regs->idiv, (cfg->idiv << IDIV_ID_BIT) & IDIV_ID);
862        }
863
864        /* Write Timer Prescaler Register */
865        if (cfg->flags & ROUTER_FLG_TPRES) {
866                REG_WRITE(&priv->regs->tprescaler,
867                                (cfg->timer_prescaler << PRESCALER_RL_BIT) & PRESCALER_RL);
868        }
869
870        #ifdef THREAD_SAFE
871        /* Unlock dev */
872        rtems_semaphore_release(priv->sem);
873        #endif
874
875        return ROUTER_ERR_OK;
876}
877
878int router_config_get(void *d, struct router_config *cfg)
879{
880        struct router_priv *priv = d;
881        int error = router_check_open(d);
882
883        if (error)
884                return error;
885
886        if (cfg == NULL) {
887                DBG("ROUTER CFG wrong\n");
888                return ROUTER_ERR_EINVAL;
889        }
890
891        #ifdef THREAD_SAFE
892        /* Take device lock - Wait until we get semaphore */
893        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
894                        != RTEMS_SUCCESSFUL) {
895                DBG("ROUTER Sempahore failed\n");
896                return ROUTER_ERR_ERROR;
897        }
898        #endif
899
900        cfg->config = REG_READ(&priv->regs->cfgsts) &
901                ~(RTRCFG_SP|RTRCFG_AP|RTRCFG_FP|RTRCFG_SR|RTRCFG_PE|RTRCFG_ME|
902                  RTRCFG_TA|RTRCFG_PP);
903        cfg->iid = (REG_READ(&priv->regs->ver) & VER_ID) >> VER_ID_BIT;
904        cfg->idiv = (REG_READ(&priv->regs->idiv) & IDIV_ID) >> IDIV_ID_BIT;
905        cfg->timer_prescaler =
906                (REG_READ(&priv->regs->tprescaler) & PRESCALER_RL) >> PRESCALER_RL_BIT;
907
908        #ifdef THREAD_SAFE
909        /* Unlock dev */
910        rtems_semaphore_release(priv->sem);
911        #endif
912
913        return ROUTER_ERR_OK;
914}
915
916/* Configure Router routing table.
917 * Leave field NULL in order to skip configuration
918 */
919int router_routing_table_set(void *d, struct router_routing_table *cfg)
920{
921        struct router_priv *priv = d;
922        int error = router_check_open(d);
923
924        if (error)
925                return error;
926
927        if (cfg == NULL) {
928                DBG("ROUTER CFG wrong\n");
929                return ROUTER_ERR_EINVAL;
930        }
931
932        #ifdef THREAD_SAFE
933        /* Take device lock - Wait until we get semaphore */
934        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
935                        != RTEMS_SUCCESSFUL) {
936                DBG("ROUTER Sempahore failed\n");
937                return ROUTER_ERR_ERROR;
938        }
939        #endif
940
941        /* Write Address control */
942        if (cfg->flags & ROUTER_ROUTE_FLG_CTRL) {
943                router_acontrol_set(priv,&cfg->acontrol);
944        }
945
946        /* Write Port map */
947        if (cfg->flags & ROUTER_ROUTE_FLG_MAP) {
948                router_portmap_set(priv,&cfg->portmap);
949        }
950
951        #ifdef THREAD_SAFE
952        /* Unlock dev */
953        rtems_semaphore_release(priv->sem);
954        #endif
955
956        return ROUTER_ERR_OK;
957}
958
959int router_routing_table_get(void *d, struct router_routing_table *cfg)
960{
961        struct router_priv *priv = d;
962        int error = router_check_open(d);
963
964        if (error)
965                return error;
966
967        if (cfg == NULL) {
968                DBG("ROUTER CFG wrong\n");
969                return ROUTER_ERR_EINVAL;
970        }
971
972        #ifdef THREAD_SAFE
973        /* Take device lock - Wait until we get semaphore */
974        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
975                        != RTEMS_SUCCESSFUL) {
976                DBG("ROUTER Sempahore failed\n");
977                return ROUTER_ERR_ERROR;
978        }
979        #endif
980
981        /* Read Address control */
982        router_acontrol_get(priv,&cfg->acontrol);
983
984        /* Read Port map */
985        router_portmap_get(priv,&cfg->portmap);
986
987        #ifdef THREAD_SAFE
988        /* Unlock dev */
989        rtems_semaphore_release(priv->sem);
990        #endif
991
992        return ROUTER_ERR_OK;
993}
994
995int router_route_set(void *d, struct router_route *route)
996{
997        struct router_priv *priv = d;
998        int i;
999        unsigned int mask;
1000        int error = router_check_open(d);
1001
1002        if (error)
1003                return error;
1004
1005        if (route == NULL) {
1006                DBG("ROUTER route wrong\n");
1007                return ROUTER_ERR_EINVAL;
1008        }
1009
1010        if (route->from_address < 32) {
1011                /* Physical address */
1012                if ((route->from_address == 0) ||
1013                                (route->from_address >= priv->nports)) {
1014                        DBG("ROUTER wrong physical address\n");
1015                        return ROUTER_ERR_TOOMANY;
1016                }
1017        }
1018
1019        /* Compute port map */
1020        mask=0;
1021        for (i=0; i < route->count; i++) {
1022                if ((route->to_port[i] == 0) || (route->to_port[i] >= priv->nports)) {
1023                        DBG("ROUTER route wrong destiny port\n");
1024                        return ROUTER_ERR_EINVAL;
1025                }
1026                mask |= (0x1 << route->to_port[i]);
1027        }
1028        if (route->options & ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE) {
1029                mask |= RTPMAP_PD;
1030        }
1031
1032        #ifdef THREAD_SAFE
1033        /* Take device lock - Wait until we get semaphore */
1034        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1035                        != RTEMS_SUCCESSFUL) {
1036                DBG("ROUTER Sempahore failed\n");
1037                return ROUTER_ERR_ERROR;
1038        }
1039        #endif
1040
1041        /* Write port map */
1042        REG_WRITE(&priv->regs->psetup[route->from_address-1], mask);
1043
1044        /* Write Address control */
1045        REG_WRITE(&priv->regs->routes[route->from_address-1],
1046                        route->options & (0xf));
1047
1048        #ifdef THREAD_SAFE
1049        /* Unlock dev */
1050        rtems_semaphore_release(priv->sem);
1051        #endif
1052
1053        return ROUTER_ERR_OK;
1054}
1055
1056int router_route_get(void *d, struct router_route *route)
1057{
1058        struct router_priv *priv = d;
1059        int i,count;
1060        unsigned int mask;
1061        int error = router_check_open(d);
1062
1063        if (error)
1064                return error;
1065
1066        if (route == NULL) {
1067                DBG("ROUTER route wrong\n");
1068                return ROUTER_ERR_EINVAL;
1069        }
1070
1071        if (route->from_address < 32) {
1072                /* Physical address */
1073                if ((route->from_address == 0) ||
1074                                (route->from_address >= priv->nports)) {
1075                        DBG("ROUTER wrong physical address\n");
1076                        return ROUTER_ERR_TOOMANY;
1077                }
1078        }
1079
1080        #ifdef THREAD_SAFE
1081        /* Take device lock - Wait until we get semaphore */
1082        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1083                        != RTEMS_SUCCESSFUL) {
1084                DBG("ROUTER Sempahore failed\n");
1085                return ROUTER_ERR_ERROR;
1086        }
1087        #endif
1088
1089        /* Get Address control */
1090        route->options =
1091                REG_READ(&priv->regs->routes[route->from_address-1]) & (0xf);
1092
1093        /* Read port map */
1094        mask=REG_READ(&priv->regs->psetup[route->from_address-1]);
1095
1096        #ifdef THREAD_SAFE
1097        /* Unlock dev */
1098        rtems_semaphore_release(priv->sem);
1099        #endif
1100
1101        if (mask & RTPMAP_PD) {
1102                route->options |= ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE;
1103        }
1104
1105        /*DBG("ROUTE from address 0x%02x read, PMAP: 0x%08x, CTRL: 0x%08x\n",
1106         *              (unsigned int) route->from_address, mask,
1107         *              (unsigned int) route->options);*/
1108
1109        i=0;
1110        count=0;
1111        mask &= (RTPMAP_PE);
1112        while (mask != 0) {
1113                if (mask & 0x1) {
1114                        route->to_port[count] = i;
1115                        count++;
1116                }
1117                mask >>= 1;
1118                i++;
1119        }
1120        route->count=count;
1121
1122        return ROUTER_ERR_OK;
1123}
1124
1125int router_write_enable(void *d)
1126{
1127        struct router_priv *priv = d;
1128        int error = router_check_open(d);
1129
1130        if (error)
1131                return error;
1132
1133        REG_WRITE(&priv->regs->cfgwe, 0x1);
1134
1135        return ROUTER_ERR_OK;
1136}
1137
1138int router_write_disable(void *d)
1139{
1140        struct router_priv *priv = d;
1141        int error = router_check_open(d);
1142
1143        if (error)
1144                return error;
1145
1146        REG_WRITE(&priv->regs->cfgwe, 0x0);
1147
1148        return ROUTER_ERR_OK;
1149}
1150
1151int router_port_ioc(void *d, int port, struct router_port *cfg)
1152{
1153        struct router_priv *priv = d;
1154        unsigned int ctrl, ctrl2, sts, timer, pktl;
1155        SPIN_IRQFLAGS(irqflags);
1156        int error = router_check_port(d, port);
1157
1158        if (error)
1159                return error;
1160
1161        if (cfg == NULL) {
1162                DBG("ROUTER Wrong cfg\n");
1163                return ROUTER_ERR_EINVAL;
1164        }
1165
1166        SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1167
1168        ctrl = cfg->ctrl;
1169        if (cfg->flag & ROUTER_PORT_FLG_GET_CTRL) {
1170                ctrl = REG_READ(&priv->regs->pctrl[port]);
1171        }
1172        ctrl2 = cfg->ctrl;
1173        if (cfg->flag & ROUTER_PORT_FLG_GET_CTRL2) {
1174                ctrl2 = REG_READ(&priv->regs->pctrl2[port]);
1175        }
1176        sts = cfg->sts;
1177        if (cfg->flag & ROUTER_PORT_FLG_GET_STS) {
1178                sts = REG_READ(&priv->regs->psts[port]);
1179        }
1180        timer = cfg->timer_reload;
1181        if (cfg->flag & ROUTER_PORT_FLG_GET_TIMER) {
1182                REG_READ(&priv->regs->treload[port]);
1183        }
1184        pktl = cfg->packet_length;
1185        if (cfg->flag & ROUTER_PORT_FLG_GET_PKTLEN) {
1186                REG_READ(&priv->regs->maxplen[port]);
1187        }
1188
1189        if (cfg->flag & ROUTER_PORT_FLG_SET_CTRL) {
1190                REG_WRITE(&priv->regs->pctrl[port], cfg->ctrl);
1191        }
1192        if (cfg->flag & ROUTER_PORT_FLG_SET_CTRL2) {
1193                REG_WRITE(&priv->regs->pctrl2[port], cfg->ctrl2);
1194        }
1195        if (cfg->flag & ROUTER_PORT_FLG_SET_STS) {
1196                REG_WRITE(&priv->regs->psts[port], cfg->sts);
1197        }
1198        if (cfg->flag & ROUTER_PORT_FLG_SET_TIMER) {
1199                REG_WRITE(&priv->regs->treload[port], cfg->timer_reload & PTIMER_RL);
1200        }
1201        if (cfg->flag & ROUTER_PORT_FLG_SET_PKTLEN) {
1202                REG_WRITE(&priv->regs->maxplen[port], cfg->packet_length & MAXPLEN_ML);
1203        }
1204
1205        SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1206
1207        cfg->ctrl = ctrl;
1208        cfg->ctrl2 = ctrl2;
1209        cfg->sts = sts;
1210        cfg->timer_reload = timer;
1211        cfg->packet_length = pktl;
1212
1213        return ROUTER_ERR_OK;
1214}
1215
1216int router_port_ctrl_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value)
1217{
1218        struct router_priv *priv = d;
1219        int error = router_check_port(d, port);
1220        unsigned int oldctrl, ctrl;
1221        SPIN_IRQFLAGS(irqflags);
1222
1223        if (error)
1224                return error;
1225
1226        SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1227
1228        oldctrl = REG_READ(&priv->regs->pctrl[port]);
1229        ctrl = ((oldctrl & ~(bitmask)) | (value & bitmask));
1230        REG_WRITE(&priv->regs->pctrl[port], ctrl);
1231
1232        SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1233
1234        if (oldvalue != NULL) {
1235                *oldvalue = oldctrl;
1236        }
1237
1238        return ROUTER_ERR_OK;
1239}
1240
1241int router_port_ctrl2_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value)
1242{
1243        struct router_priv *priv = d;
1244        int error = router_check_port(d, port);
1245        unsigned int oldctrl, ctrl;
1246        SPIN_IRQFLAGS(irqflags);
1247
1248        if (error)
1249                return error;
1250
1251        SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1252
1253        oldctrl = REG_READ(&priv->regs->pctrl2[port]);
1254        ctrl = ((oldctrl & ~(bitmask)) | (value & bitmask));
1255        REG_WRITE(&priv->regs->pctrl2[port], ctrl);
1256
1257        SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1258
1259        if (oldvalue != NULL) {
1260                *oldvalue = oldctrl;
1261        }
1262
1263        return ROUTER_ERR_OK;
1264}
1265
1266/* Read Port Control register */
1267int router_port_ctrl_get(void *d, int port, uint32_t *ctrl)
1268{
1269        struct router_priv *priv = d;
1270        int error = router_check_port(d, port);
1271
1272        if (error)
1273                return error;
1274
1275        if (ctrl == NULL) {
1276                DBG("ROUTER Wrong ctrl\n");
1277                return ROUTER_ERR_EINVAL;
1278        }
1279
1280        *ctrl = REG_READ(&priv->regs->pctrl[port]);
1281        return ROUTER_ERR_OK;
1282}
1283
1284/* Read Port Status register and clear errors if there are */
1285int router_port_status(void *d, int port, uint32_t *sts, uint32_t clrmsk)
1286{
1287        struct router_priv *priv = d;
1288        int error = router_check_port(d, port);
1289        SPIN_IRQFLAGS(irqflags);
1290
1291        if (error)
1292                return error;
1293
1294        if (sts == NULL) {
1295                DBG("ROUTER Wrong sts\n");
1296                return ROUTER_ERR_EINVAL;
1297        }
1298
1299        SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1300        *sts = REG_READ(&priv->regs->psts[port]);
1301        if (port == 0) {
1302                REG_WRITE(&priv->regs->psts[port], ((*sts) & (PSTSCFG_WCLEAR & clrmsk)) | (PSTSCFG_WCLEAR2 & clrmsk));
1303        }else{
1304                REG_WRITE(&priv->regs->psts[port], (*sts) & (PSTS_WCLEAR & clrmsk));
1305        }
1306        SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1307        return ROUTER_ERR_OK;
1308}
1309
1310/* Read Port Control2 register */
1311int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2)
1312{
1313        struct router_priv *priv = d;
1314        int error = router_check_port(d, port);
1315
1316        if (error)
1317                return error;
1318
1319        if (ctrl2 == NULL) {
1320                DBG("ROUTER Wrong ctrl2\n");
1321                return ROUTER_ERR_EINVAL;
1322        }
1323
1324        *ctrl2 = REG_READ(&priv->regs->pctrl2[port]);
1325        return ROUTER_ERR_OK;
1326}
1327
1328/* Write Port Control Register */
1329int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl)
1330{
1331        return router_port_ctrl_rmw(d, port, NULL, mask, ctrl);
1332}
1333
1334/* Write Port Control2 Register */
1335int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2)
1336{
1337        return router_port_ctrl_rmw(d, port, NULL, mask, ctrl2);
1338}
1339
1340int router_port_treload_set(void *d, int port, uint32_t reload)
1341{
1342        struct router_priv *priv = d;
1343        int error = router_check_port(d, port);
1344
1345        if (error)
1346                return error;
1347
1348        REG_WRITE(&priv->regs->treload[port], reload & PTIMER_RL);
1349
1350        return ROUTER_ERR_OK;
1351}
1352
1353int router_port_treload_get(void *d, int port, uint32_t *reload)
1354{
1355        struct router_priv *priv = d;
1356        int error = router_check_port(d, port);
1357
1358        if (error)
1359                return error;
1360
1361        if (reload == NULL) {
1362                DBG("ROUTER Wrong reload pointer\n");
1363                return ROUTER_ERR_EINVAL;
1364        }
1365
1366        *reload = REG_READ(&priv->regs->treload[port]) & PTIMER_RL;
1367
1368        return ROUTER_ERR_OK;
1369}
1370
1371int router_port_maxplen_set(void *d, int port, uint32_t length)
1372{
1373        struct router_priv *priv = d;
1374        int error = router_check_port(d, port);
1375
1376        if (error)
1377                return error;
1378
1379        REG_WRITE(&priv->regs->maxplen[port], length & MAXPLEN_ML);
1380
1381        return ROUTER_ERR_OK;
1382}
1383
1384int router_port_maxplen_get(void *d, int port, uint32_t *length)
1385{
1386        struct router_priv *priv = d;
1387        int error = router_check_port(d, port);
1388
1389        if (error)
1390                return error;
1391
1392        if (length == NULL) {
1393                DBG("ROUTER Wrong length pointer\n");
1394                return ROUTER_ERR_EINVAL;
1395        }
1396
1397        *length = REG_READ(&priv->regs->maxplen[port]);
1398
1399        return ROUTER_ERR_OK;
1400}
1401
1402/* Get Port Link Status */
1403int router_port_link_status(void *d, int port)
1404{
1405        struct router_priv *priv = d;
1406        int error = router_check_port(d, port);
1407
1408        if (error)
1409                return error;
1410
1411        return ((REG_READ(&priv->regs->psts[port]) & PSTS_LS) >> PSTS_LS_BIT);
1412}
1413
1414int router_port_disable(void *d, int port)
1415{
1416        return router_port_ctrl_rmw(d, port, NULL, PCTRL_DI, PCTRL_DI);
1417}
1418
1419int router_port_enable(void *d, int port)
1420{
1421        return router_port_ctrl_rmw(d, port, NULL, PCTRL_DI, 0);
1422}
1423
1424int router_port_link_stop(void *d, int port)
1425{
1426        return router_port_ctrl_rmw(d, port, NULL, PCTRL_LD | PCTRL_LS, PCTRL_LD);
1427}
1428
1429int router_port_link_start(void *d, int port)
1430{
1431        return router_port_ctrl_rmw(d, port, NULL, PCTRL_LD | PCTRL_LS, PCTRL_LS);
1432}
1433
1434int router_port_link_receive_spill(void *d, int port)
1435{
1436        struct router_priv *priv = d;
1437        unsigned int ctrl;
1438        SPIN_IRQFLAGS(irqflags);
1439        int error = router_check_port(d, port);
1440
1441        if (error)
1442                return error;
1443
1444        SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1445
1446        ctrl = REG_READ(&priv->regs->pctrl[port]);
1447        REG_WRITE(&priv->regs->pctrl[port], (ctrl| (PCTRL_RS)));
1448
1449        /* Wait until the spill is done */
1450        while(REG_READ(&priv->regs->pctrl[port]) & PCTRL_RS) {};
1451
1452        SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1453
1454        return ROUTER_ERR_OK;
1455}
1456
1457int router_port_link_transmit_reset(void *d, int port)
1458{
1459        struct router_priv *priv = d;
1460        unsigned int ctrl;
1461        SPIN_IRQFLAGS(irqflags);
1462        int error = router_check_port(d, port);
1463
1464        if (error)
1465                return error;
1466
1467        SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1468
1469        ctrl = REG_READ(&priv->regs->pctrl[port]);
1470        REG_WRITE(&priv->regs->pctrl[port], (ctrl| (PCTRL_TF)));
1471
1472        /* Wait until the spill is done */
1473        while(REG_READ(&priv->regs->pctrl[port]) & PCTRL_TF) {};
1474
1475        SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1476
1477        return ROUTER_ERR_OK;
1478}
1479
1480int router_port_cred_get(void *d, int port, uint32_t *cred)
1481{
1482        struct router_priv *priv = d;
1483        int error = router_check_port(d, port);
1484
1485        if (error)
1486                return error;
1487
1488        if (cred == NULL) {
1489                DBG("ROUTER Wrong cred pointer\n");
1490                return ROUTER_ERR_EINVAL;
1491        }
1492
1493        *cred = REG_READ(&priv->regs->credcnt[port]);
1494        return ROUTER_ERR_OK;
1495}
1496
1497int router_instance_set(void *d, uint8_t instance)
1498{
1499        struct router_priv *priv = d;
1500        int error = router_check_open(d);
1501
1502        if (error)
1503                return error;
1504
1505        REG_WRITE(&priv->regs->ver, (instance << VER_ID_BIT) & VER_ID);
1506        return ROUTER_ERR_OK;
1507}
1508
1509int router_idiv_set(void *d, uint8_t idiv)
1510{
1511        struct router_priv *priv = d;
1512        int error = router_check_open(d);
1513
1514        if (error)
1515                return error;
1516
1517        REG_WRITE(&priv->regs->idiv, (idiv << IDIV_ID_BIT) & IDIV_ID);
1518        return ROUTER_ERR_OK;
1519}
1520
1521int router_tpresc_set(void *d, uint32_t prescaler)
1522{
1523        struct router_priv *priv = d;
1524        int error = router_check_open(d);
1525
1526        if (error)
1527                return error;
1528
1529        REG_WRITE(&priv->regs->tprescaler,
1530                        (prescaler << PRESCALER_RL_BIT) & PRESCALER_RL);
1531        return ROUTER_ERR_OK;
1532}
1533
1534int router_instance_get(void *d, uint8_t *instance)
1535{
1536        struct router_priv *priv = d;
1537        int error = router_check_open(d);
1538
1539        if (error)
1540                return error;
1541
1542        if (instance == NULL) {
1543                DBG("ROUTER Wrong instance pointer\n");
1544                return ROUTER_ERR_EINVAL;
1545        }
1546
1547        *instance = REG_READ(&priv->regs->ver);
1548
1549        return ROUTER_ERR_OK;
1550}
1551
1552int router_idiv_get(void *d, uint8_t *idiv)
1553{
1554        struct router_priv *priv = d;
1555        int error = router_check_open(d);
1556
1557        if (error)
1558                return error;
1559
1560        if (idiv == NULL) {
1561                DBG("ROUTER Wrong idiv pointer\n");
1562                return ROUTER_ERR_EINVAL;
1563        }
1564
1565        *idiv = REG_READ(&priv->regs->idiv);
1566
1567        return ROUTER_ERR_OK;
1568}
1569
1570int router_tpresc_get(void *d, uint32_t *prescaler)
1571{
1572        struct router_priv *priv = d;
1573        int error = router_check_open(d);
1574
1575        if (error)
1576                return error;
1577
1578        if (prescaler == NULL) {
1579                DBG("ROUTER Wrong prescaler pointer\n");
1580                return ROUTER_ERR_EINVAL;
1581        }
1582
1583        *prescaler = REG_READ(&priv->regs->tprescaler);
1584
1585        return ROUTER_ERR_OK;
1586}
1587
1588int router_cfgsts_set(void *d, uint32_t cfgsts)
1589{
1590        struct router_priv *priv = d;
1591        int error = router_check_open(d);
1592
1593        if (error)
1594                return error;
1595
1596        REG_WRITE(&priv->regs->cfgsts, cfgsts);
1597
1598        return ROUTER_ERR_OK;
1599}
1600
1601int router_cfgsts_get(void *d, uint32_t *cfgsts)
1602{
1603        struct router_priv *priv = d;
1604        int error = router_check_open(d);
1605
1606        if (error)
1607                return error;
1608
1609        if (cfgsts == NULL) {
1610                DBG("ROUTER Wrong cfgsts pointer\n");
1611                return ROUTER_ERR_EINVAL;
1612        }
1613
1614        *cfgsts = REG_READ(&priv->regs->cfgsts);
1615
1616        return ROUTER_ERR_OK;
1617}
1618
1619int router_tc_enable(void *d)
1620{
1621        struct router_priv *priv = d;
1622        int error = router_check_open(d);
1623
1624        if (error)
1625                return error;
1626
1627        REG_WRITE(&priv->regs->timecode, TC_EN);
1628
1629        return ROUTER_ERR_OK;
1630}
1631
1632int router_tc_disable(void *d)
1633{
1634        struct router_priv *priv = d;
1635        int error = router_check_open(d);
1636
1637        if (error)
1638                return error;
1639
1640        REG_WRITE(&priv->regs->timecode, 0);
1641
1642        return ROUTER_ERR_OK;
1643}
1644
1645int router_tc_reset(void *d)
1646{
1647        struct router_priv *priv = d;
1648        unsigned int tc;
1649        int error = router_check_open(d);
1650
1651        if (error)
1652                return error;
1653
1654        tc = REG_READ(&priv->regs->timecode);
1655        REG_WRITE(&priv->regs->timecode, tc | TC_RE);
1656
1657        return ROUTER_ERR_OK;
1658}
1659
1660int router_tc_get(void *d)
1661{
1662        struct router_priv *priv = d;
1663        int error = router_check_open(d);
1664
1665        if (error)
1666                return error;
1667
1668        return (REG_READ(&priv->regs->timecode) & (TC_CF | TC_TC)) >> TC_TC_BIT;
1669}
1670
1671int router_interrupt_unmask(void *d, int options)
1672{
1673        struct router_priv *priv = d;
1674        unsigned int mask;
1675        int error = router_check_open(d);
1676
1677        if (error)
1678                return error;
1679
1680        #ifdef THREAD_SAFE
1681        /* Take device lock - Wait until we get semaphore */
1682        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1683                        != RTEMS_SUCCESSFUL) {
1684                DBG("ROUTER Sempahore failed\n");
1685                return ROUTER_ERR_ERROR;
1686        }
1687        #endif
1688
1689        /* Unmask interrupts in ROTUER */
1690        /* Get previous mask */
1691        mask = REG_READ(&priv->regs->imask);
1692
1693        /* Clear previous interrupts*/
1694        REG_WRITE(&priv->regs->pip, 0xffffffff);
1695
1696        /* Set new mask */
1697        REG_WRITE(&priv->regs->imask, mask | options);
1698
1699        #ifdef THREAD_SAFE
1700        /* Unlock dev */
1701        rtems_semaphore_release(priv->sem);
1702        #endif
1703
1704        return ROUTER_ERR_OK;
1705}
1706
1707int router_interrupt_mask(void *d, int options)
1708{
1709        struct router_priv *priv = d;
1710        unsigned int mask;
1711        int error = router_check_open(d);
1712
1713        if (error)
1714                return error;
1715
1716        #ifdef THREAD_SAFE
1717        /* Take device lock - Wait until we get semaphore */
1718        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1719                        != RTEMS_SUCCESSFUL) {
1720                DBG("ROUTER Sempahore failed\n");
1721                return ROUTER_ERR_ERROR;
1722        }
1723        #endif
1724
1725        /* Mask interrupts in ROTUER */
1726        /* Get previous mask */
1727        mask = REG_READ(&priv->regs->imask);
1728
1729        /* Clear previous interrupts*/
1730        REG_WRITE(&priv->regs->pip, 0xffffffff);
1731
1732        /* Set new mask */
1733        REG_WRITE(&priv->regs->imask, mask & ~(options));
1734
1735        #ifdef THREAD_SAFE
1736        /* Unlock dev */
1737        rtems_semaphore_release(priv->sem);
1738        #endif
1739
1740        return ROUTER_ERR_OK;
1741}
1742
1743int router_port_interrupt_unmask(void *d, int port)
1744{
1745        struct router_priv *priv = d;
1746        unsigned int mask;
1747        int error = router_check_port(d, port);
1748
1749        if (error)
1750                return error;
1751
1752        #ifdef THREAD_SAFE
1753        /* Take device lock - Wait until we get semaphore */
1754        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1755                        != RTEMS_SUCCESSFUL) {
1756                DBG("ROUTER Sempahore failed\n");
1757                return ROUTER_ERR_ERROR;
1758        }
1759        #endif
1760
1761        /* Unmask interrupts in ROTUER */
1762        /* Get previous mask */
1763        mask = REG_READ(&priv->regs->ipmask);
1764
1765        /* Clear previous interrupts*/
1766        REG_WRITE(&priv->regs->pip, (0x1 << port));
1767
1768        /* Set new mask */
1769        REG_WRITE(&priv->regs->ipmask, mask | (0x1 << port));
1770
1771        #ifdef THREAD_SAFE
1772        /* Unlock dev */
1773        rtems_semaphore_release(priv->sem);
1774        #endif
1775
1776        return ROUTER_ERR_OK;
1777}
1778
1779int router_port_interrupt_mask(void *d, int port)
1780{
1781        struct router_priv *priv = d;
1782        unsigned int mask;
1783        int error = router_check_port(d, port);
1784
1785        if (error)
1786                return error;
1787
1788        #ifdef THREAD_SAFE
1789        /* Take device lock - Wait until we get semaphore */
1790        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1791                        != RTEMS_SUCCESSFUL) {
1792                DBG("ROUTER Sempahore failed\n");
1793                return ROUTER_ERR_ERROR;
1794        }
1795        #endif
1796
1797        /* Mask interrupts in ROTUER */
1798        /* Get previous mask */
1799        mask = REG_READ(&priv->regs->ipmask);
1800
1801        /* Clear previous interrupts*/
1802        REG_WRITE(&priv->regs->pip, (0x1 << port));
1803
1804        /* Set new mask */
1805        REG_WRITE(&priv->regs->ipmask, mask & ~(0x1 << port));
1806
1807        #ifdef THREAD_SAFE
1808        /* Unlock dev */
1809        rtems_semaphore_release(priv->sem);
1810        #endif
1811
1812        return ROUTER_ERR_OK;
1813}
1814
1815int router_reset(void *d)
1816{
1817        struct router_priv *priv = d;
1818        int error = router_check_open(d);
1819
1820        if (error)
1821                return error;
1822
1823        /* Reset router */
1824        REG_WRITE(&priv->regs->cfgsts, RTRCFG_RE);
1825
1826        return ROUTER_ERR_OK;
1827}
1828
1829int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer,
1830                int options)
1831{
1832        struct router_priv *priv = d;
1833        int error = router_check_distint_support(d);
1834
1835        if (error)
1836                return error;
1837
1838        #ifdef THREAD_SAFE
1839        /* Take device lock - Wait until we get semaphore */
1840        if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1841                        != RTEMS_SUCCESSFUL) {
1842                DBG("ROUTER Sempahore failed\n");
1843                return ROUTER_ERR_ERROR;
1844        }
1845        #endif
1846
1847        REG_WRITE(&priv->regs->icodegen, (options & ~(ICODEGEN_IN)) |
1848                        ICODEGEN_EN | (intn & ICODEGEN_IN));
1849
1850        if (options & ICODEGEN_TE) {
1851                REG_WRITE(&priv->regs->aitimer, (aitimer & AITIMER_RL));
1852        }
1853
1854        #ifdef THREAD_SAFE
1855        /* Unlock dev */
1856        rtems_semaphore_release(priv->sem);
1857        #endif
1858
1859        return ROUTER_ERR_OK;
1860}
1861
1862int router_icodegen_disable(void *d)
1863{
1864        struct router_priv *priv = d;
1865        int error = router_check_distint_support(d);
1866
1867        if (error)
1868                return error;
1869
1870        REG_WRITE(&priv->regs->icodegen, ICODEGEN_TE);
1871
1872        return ROUTER_ERR_OK;
1873}
1874
1875int router_isrctimer_set(void *d, uint32_t reloadvalue)
1876{
1877        struct router_priv *priv = d;
1878        int error = router_check_distint_support(d);
1879
1880        if (error)
1881                return error;
1882
1883        /* Set ISRC TIMER */
1884        REG_WRITE(&priv->regs->isrctimer, (reloadvalue & (ISRCTIMER_RL)));
1885
1886        return ROUTER_ERR_OK;
1887}
1888
1889int router_isrtimer_set(void *d, uint32_t reloadvalue)
1890{
1891        struct router_priv *priv = d;
1892        int error = router_check_distint_support(d);
1893
1894        if (error)
1895                return error;
1896
1897        /* Set ISR TIMER */
1898        REG_WRITE(&priv->regs->isrtimer, (reloadvalue & (ISRTIMER_RL)));
1899
1900        return ROUTER_ERR_OK;
1901}
1902
1903int router_isrctimer_get(void *d, uint32_t *reloadvalue)
1904{
1905        struct router_priv *priv = d;
1906        int error = router_check_distint_support(d);
1907
1908        if (error)
1909                return error;
1910
1911        if (reloadvalue == NULL) {
1912                DBG("ROUTER Wrong reloadvalue pointer\n");
1913                return ROUTER_ERR_EINVAL;
1914        }
1915
1916        /* Set ISRC TIMER */
1917        *reloadvalue = REG_READ(&priv->regs->isrctimer) & (ISRCTIMER_RL);
1918
1919        return ROUTER_ERR_OK;
1920}
1921
1922int router_isrtimer_get(void *d, uint32_t *reloadvalue)
1923{
1924        struct router_priv *priv = d;
1925        int error = router_check_distint_support(d);
1926
1927        if (error)
1928                return error;
1929
1930        if (reloadvalue == NULL) {
1931                DBG("ROUTER Wrong reloadvalue pointer\n");
1932                return ROUTER_ERR_EINVAL;
1933        }
1934
1935        /* Set ISR TIMER */
1936        *reloadvalue = REG_READ(&priv->regs->isrtimer) & (ISRTIMER_RL);
1937
1938        return ROUTER_ERR_OK;
1939}
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