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source: rtems/bsps/sparc/shared/spw/grspw.c @ 31720925

5

Last change on this file since 31720925 was 31720925, checked in by Sebastian Huber <sebastian.huber@…>, on 12/22/18 at 06:13:44

grlib: Move header files

Update #3678.

Property mode set to 100644

File size: 61.6 KB

Line
1	/*
2	* This file contains the GRSPW SpaceWire Driver for LEON2 and LEON3.
3	*
4	* COPYRIGHT (c) 2006
5	* Cobham Gaisler AB.
6	*
7	* The license and distribution terms for this file may be
8	* found in the file LICENSE in this distribution or at
9	* http://www.rtems.org/license/LICENSE.
10	*/
11
12	#include <bsp.h>
13	#include <rtems/libio.h>
14	#include <stdlib.h>
15	#include <stdio.h>
16	#include <string.h>
17	#include <assert.h>
18	#include <ctype.h>
19	#include <rtems/bspIo.h>
20	#include <grlib/ambapp.h>
21
22	#include <drvmgr/drvmgr.h>
23	#include <grlib/ambapp_bus.h>
24	#include <grlib/grspw.h>
25
26	#include <grlib/grlib_impl.h>
27
28	#define DBGSPW_IOCALLS 1
29	#define DBGSPW_TX 2
30	#define DBGSPW_RX 4
31	#define DBGSPW_IOCTRL 1
32	#define DBGSPW_DUMP 16
33	#define DEBUG_SPACEWIRE_FLAGS (DBGSPW_IOCALLS \| DBGSPW_TX \| DBGSPW_RX )
34
35	/* #define DEBUG_SPACEWIRE_ONOFF */
36
37	#ifdef DEBUG_SPACEWIRE_ONOFF
38	#define SPACEWIRE_DBG(fmt, args...) do { { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0)
39	#define SPACEWIRE_DBG2(fmt) do { { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__); }} while(0)
40	#define SPACEWIRE_DBGC(c,fmt, args...) do { if (DEBUG_SPACEWIRE_FLAGS & c) { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0)
41	#else
42	#define SPACEWIRE_DBG(fmt, args...)
43	#define SPACEWIRE_DBG2(fmt, args...)
44	#define SPACEWIRE_DBGC(c, fmt, args...)
45	#endif
46
47	typedef struct {
48	volatile unsigned int ctrl;
49	volatile unsigned int status;
50	volatile unsigned int nodeaddr;
51	volatile unsigned int clkdiv;
52	volatile unsigned int destkey;
53	volatile unsigned int time;
54	volatile unsigned int timer;
55	volatile unsigned int pad;
56
57	volatile unsigned int dma0ctrl;
58	volatile unsigned int dma0rxmax;
59	volatile unsigned int dma0txdesc;
60	volatile unsigned int dma0rxdesc;
61
62	/* For GRSPW core 2 and onwards */
63	volatile unsigned int dma0addr;
64
65	} LEON3_SPACEWIRE_Regs_Map;
66
67	typedef struct {
68	volatile unsigned int ctrl;
69	volatile unsigned int addr;
70	} SPACEWIRE_RXBD;
71
72	typedef struct {
73	volatile unsigned int ctrl;
74	volatile unsigned int addr_header;
75	volatile unsigned int len;
76	volatile unsigned int addr_data;
77	} SPACEWIRE_TXBD;
78
79	#define SPACEWIRE_INIT_TIMEOUT 10
80	#define SPACEWIRE_BDTABLE_SIZE 0x400
81	#define SPACEWIRE_TXD_SIZE 1024
82	#define SPACEWIRE_TXH_SIZE 64
83	#define SPACEWIRE_RXPCK_SIZE 1024
84	#define SPACEWIRE_TXBUFS_NR 64
85	#define SPACEWIRE_RXBUFS_NR 128
86
87	#define BUFMEM_PER_LINK (SPACEWIRE_TXBUFS_NR(SPACEWIRE_TXD_SIZE+SPACEWIRE_TXH_SIZE) + SPACEWIRE_RXBUFS_NRSPACEWIRE_RXPCK_SIZE)
88
89	typedef struct {
90	/* configuration parameters */
91	struct drvmgr_dev dev; / Driver manager device */
92	char devName[32]; /* Device Name */
93	LEON3_SPACEWIRE_Regs_Map *regs;
94	spw_config config;
95
96	unsigned int tx_all_in_use;
97	unsigned int tx_sent;
98	unsigned int tx_cur;
99	unsigned int rxcur;
100	unsigned int rxbufcur;
101	unsigned int txdbufsize;
102	unsigned int txhbufsize;
103	unsigned int rxbufsize;
104	unsigned int txbufcnt;
105	unsigned int rxbufcnt;
106
107	/* DMA Area set by user */
108	unsigned int rx_dma_area;
109	unsigned int tx_data_dma_area;
110	unsigned int tx_hdr_dma_area;
111	unsigned int bd_dma_area;
112
113	/* statistics */
114	spw_stats stat;
115
116	unsigned int _ptr_rxbuf0;
117	char *ptr_rxbuf0;
118	char *ptr_txdbuf0;
119	char *ptr_txhbuf0;
120	char _ptr_bd0, ptr_bd0;
121
122	char *ptr_rxbuf0_remote;
123	char *ptr_txdbuf0_remote;
124	char *ptr_txhbuf0_remote;
125	char *ptr_bd0_remote;
126
127	unsigned int irq;
128	int minor;
129	int core_ver;
130	int open;
131	int running;
132	unsigned int core_freq_khz;
133	unsigned int rtimeout;
134
135	/* semaphores*/
136	rtems_id txsp;
137	rtems_id rxsp;
138
139	SPACEWIRE_RXBD *rx;
140	SPACEWIRE_TXBD *tx;
141
142	unsigned int rx_remote;
143	unsigned int tx_remote;
144	} GRSPW_DEV;
145
146	/* Function pointer called upon timecode receive */
147	void (*grspw_timecode_callback)
148	(void pDev, void regs, int minor, unsigned int tc) = NULL;
149
150	#ifdef GRSPW_DONT_BYPASS_CACHE
151	#define _SPW_READ(address) ((volatile unsigned int )(address))
152	#define _MEM_READ8(address) ((volatile unsigned char )(address))
153	#define _MEM_READ32(address) ((volatile unsigned int )(address))
154	#else
155	static inline unsigned int _SPW_READ(volatile void *addr) {
156	unsigned int tmp;
157	__asm__ (" lda [%1]1, %0 "
158	: "=r"(tmp)
159	: "r"(addr)
160	);
161	return tmp;
162	}
163
164	static inline unsigned int _MEM_READ8(volatile void *addr) {
165	unsigned int tmp;
166	__asm__ (" lduba [%1]1, %0 "
167	: "=r"(tmp)
168	: "r"(addr)
169	);
170	return tmp;
171	}
172
173	static inline unsigned int _MEM_READ32(volatile void *addr) {
174	unsigned int tmp;
175	__asm__ (" lda [%1]1, %0 "
176	: "=r"(tmp)
177	: "r"(addr)
178	);
179	return tmp;
180	}
181	#endif
182
183	#define MEM_READ8(addr) _MEM_READ8((volatile void *)(addr))
184	#define MEM_READ32(addr) _MEM_READ32((volatile void *)(addr))
185	#define SPW_READ(addr) _SPW_READ((volatile void *)(addr))
186	#define SPW_WRITE(addr,v) ((volatile unsigned int )addr)=v
187
188	#define SPW_REG(c,r) (c->regs->r)
189	#define SPW_REG_CTRL(c) SPW_REG(c,ctrl)
190	#define SPW_REG_STATUS(c) SPW_REG(c,status)
191	#define SPW_REG_NODEADDR(c) SPW_REG(c,nodeaddr)
192
193	#define SPW_CTRL_READ(c) SPW_READ(&SPW_REG_CTRL(c))
194	#define SPW_CTRL_WRITE(c,v) SPW_WRITE(&SPW_REG_CTRL(c),v)
195	#define SPW_STATUS_READ(c) SPW_READ(&SPW_REG_STATUS(c))
196	#define SPW_STATUS_WRITE(c,v) SPW_WRITE(&SPW_REG_STATUS(c),v)
197
198	#define SPW_LINKSTATE(c) (((c) >> 21) & 0x7)
199
200	#define SPACEWIRE_RXNR(c) ((c&~(SPACEWIRE_BDTABLE_SIZE-1))>>3)
201	#define SPACEWIRE_TXNR(c) ((c&~(SPACEWIRE_BDTABLE_SIZE-1))>>4)
202
203	#define SPW_RXBD_LENGTH 0x1ffffff
204	#define SPW_RXBD_EN (1 << 25)
205	#define SPW_RXBD_WR (1 << 26)
206	#define SPW_RXBD_IE (1 << 27)
207
208	#define SPW_RXBD_EEP (1 << 28)
209	#define SPW_RXBD_EHC (1 << 29)
210	#define SPW_RXBD_EDC (1 << 30)
211	#define SPW_RXBD_ETR (1 << 31)
212
213	#define SPW_RXBD_ERROR (SPW_RXBD_EEP \| \
214	SPW_RXBD_ETR)
215
216	#define SPW_RXBD_RMAPERROR (SPW_RXBD_EHC \| SPW_RXBD_EDC)
217
218	#define SPW_TXBD_LENGTH 0xffffff
219
220	#define SPW_TXBD_EN (1 << 12)
221	#define SPW_TXBD_WR (1 << 13)
222	#define SPW_TXBD_IE (1 << 14)
223	#define SPW_TXBD_LE (1 << 15)
224	#define SPW_TXBD_HC (1 << 16)
225	#define SPW_TXBD_DC (1 << 17)
226
227	#define SPW_TXBD_ERROR (SPW_TXBD_LE)
228
229	#define SPW_CTRL_LINKDISABLED (1 << 0)
230	#define SPW_CTRL_LINKSTART (1 << 1)
231	#define SPW_CTRL_AUTOSTART (1 << 2)
232	#define SPW_CTRL_IE (1 << 3)
233	#define SPW_CTRL_TI (1 << 4)
234	#define SPW_CTRL_PM (1 << 5)
235	#define SPW_CTRL_RESET (1 << 6)
236	#define SPW_CTRL_TQ (1 << 8)
237	#define SPW_CTRL_LI (1 << 9)
238	#define SPW_CTRL_TT (1 << 10)
239	#define SPW_CTRL_TR (1 << 11)
240	#define SPW_CTRL_RE (1 << 16)
241	#define SPW_CTRL_RD (1 << 17)
242
243	#define SPW_CTRL_RC (1 << 29)
244	#define SPW_CTRL_RX (1 << 30)
245	#define SPW_CTRL_RA (1 << 31)
246
247	#define SPW_STATUS_TO (1 << 0)
248	#define SPW_STATUS_CE (1 << 1)
249	#define SPW_STATUS_ER (1 << 2)
250	#define SPW_STATUS_DE (1 << 3)
251	#define SPW_STATUS_PE (1 << 4)
252	#define SPW_STATUS_WE (1 << 6)
253	#define SPW_STATUS_IA (1 << 7)
254	#define SPW_STATUS_EE (1 << 8)
255
256	#define SPW_DMACTRL_TXEN (1 << 0)
257	#define SPW_DMACTRL_RXEN (1 << 1)
258	#define SPW_DMACTRL_TXIE (1 << 2)
259	#define SPW_DMACTRL_RXIE (1 << 3)
260	#define SPW_DMACTRL_AI (1 << 4)
261	#define SPW_DMACTRL_PS (1 << 5)
262	#define SPW_DMACTRL_PR (1 << 6)
263	#define SPW_DMACTRL_TA (1 << 7)
264	#define SPW_DMACTRL_RA (1 << 8)
265	#define SPW_DMACTRL_AT (1 << 9)
266	#define SPW_DMACTRL_RX (1 << 10)
267	#define SPW_DMACTRL_RD (1 << 11)
268	#define SPW_DMACTRL_NS (1 << 12)
269
270	#define SPW_PREPAREMASK_TX (SPW_DMACTRL_RXEN \| SPW_DMACTRL_RXIE \| SPW_DMACTRL_PS \| SPW_DMACTRL_TA \| SPW_DMACTRL_RD \| SPW_DMACTRL_NS)
271	#define SPW_PREPAREMASK_RX (SPW_DMACTRL_TXEN \| SPW_DMACTRL_TXIE \| SPW_DMACTRL_AI \| SPW_DMACTRL_PR \| SPW_DMACTRL_RA)
272
273	static int grspw_hw_init(GRSPW_DEV *pDev);
274	static int grspw_hw_send(GRSPW_DEV pDev, unsigned int hlen, char hdr, unsigned int dlen, char *data, unsigned int options);
275	static int grspw_hw_receive(GRSPW_DEV pDev,char b,int c);
276	static int grspw_hw_startup (GRSPW_DEV *pDev, int timeout);
277	static int grspw_hw_stop (GRSPW_DEV *pDev, int rx, int tx);
278	static void grspw_hw_wait_rx_inactive(GRSPW_DEV *pDev);
279	static int grspw_hw_waitlink (GRSPW_DEV *pDev, int timeout);
280	static void grspw_hw_reset(GRSPW_DEV *pDev);
281	static void grspw_hw_read_config(GRSPW_DEV *pDev);
282
283	static void check_rx_errors(GRSPW_DEV *pDev, int ctrl);
284	static void grspw_rxnext(GRSPW_DEV *pDev);
285	static void grspw_interrupt(void *arg);
286	static int grspw_buffer_alloc(GRSPW_DEV *pDev);
287
288	static rtems_device_driver grspw_initialize(
289	rtems_device_major_number major,
290	rtems_device_minor_number minor,
291	void * arg
292	);
293
294	static rtems_device_driver grspw_open(
295	rtems_device_major_number major,
296	rtems_device_minor_number minor,
297	void * arg
298	);
299
300	static rtems_device_driver grspw_close(
301	rtems_device_major_number major,
302	rtems_device_minor_number minor,
303	void * arg
304	);
305
306	static rtems_device_driver grspw_read(
307	rtems_device_major_number major,
308	rtems_device_minor_number minor,
309	void * arg
310	);
311
312	static rtems_device_driver grspw_write(
313	rtems_device_major_number major,
314	rtems_device_minor_number minor,
315	void * arg
316	);
317
318	static rtems_device_driver grspw_control(
319	rtems_device_major_number major,
320	rtems_device_minor_number minor,
321	void * arg
322	);
323
324	#define GRSPW_DRIVER_TABLE_ENTRY \
325	{ grspw_initialize, \
326	grspw_open, \
327	grspw_close, \
328	grspw_read, \
329	grspw_write, \
330	grspw_control }
331
332	static rtems_driver_address_table grspw_driver = GRSPW_DRIVER_TABLE_ENTRY;
333	static int grspw_driver_io_registered = 0;
334	static rtems_device_major_number grspw_driver_io_major = 0;
335
336	/***************** Driver manager interface *********************/
337
338	/* Driver prototypes */
339	int grspw_register_io(rtems_device_major_number *m);
340	int grspw_device_init(GRSPW_DEV *pDev);
341
342	int grspw_init2(struct drvmgr_dev *dev);
343	int grspw_init3(struct drvmgr_dev *dev);
344
345	struct drvmgr_drv_ops grspw_ops =
346	{
347	.init = {NULL, grspw_init2, grspw_init3, NULL},
348	.remove = NULL,
349	.info = NULL
350	};
351
352	struct amba_dev_id grspw_ids[] =
353	{
354	{VENDOR_GAISLER, GAISLER_SPW},
355	{VENDOR_GAISLER, GAISLER_SPW2},
356	{VENDOR_GAISLER, GAISLER_SPW2_DMA},
357	{0, 0} /* Mark end of table */
358	};
359
360	struct amba_drv_info grspw_drv_info =
361	{
362	{
363	DRVMGR_OBJ_DRV, /* Driver */
364	NULL, /* Next driver */
365	NULL, /* Device list */
366	DRIVER_AMBAPP_GAISLER_GRSPW_ID, /* Driver ID */
367	"GRSPW_DRV", /* Driver Name */
368	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
369	&grspw_ops,
370	NULL, /* Funcs */
371	0, /* No devices yet */
372	0,
373	},
374	&grspw_ids[0]
375	};
376
377	void grspw_register_drv (void)
378	{
379	SPACEWIRE_DBG("Registering GRSPW driver\n");
380	drvmgr_drv_register(&grspw_drv_info.general);
381	}
382
383	int grspw_init2(struct drvmgr_dev *dev)
384	{
385	GRSPW_DEV *priv;
386
387	SPACEWIRE_DBG("GRSPW[%d] on bus %s\n", dev->minor_drv,
388	dev->parent->dev->name);
389	priv = dev->priv = grlib_calloc(1, sizeof(*priv));
390	if ( !priv )
391	return DRVMGR_NOMEM;
392	priv->dev = dev;
393
394	/* This core will not find other cores, so we wait for init2() */
395
396	return DRVMGR_OK;
397	}
398
399	int grspw_init3(struct drvmgr_dev *dev)
400	{
401	GRSPW_DEV *priv;
402	char prefix[32];
403	rtems_status_code status;
404
405	priv = dev->priv;
406
407	/* Do initialization */
408
409	if ( grspw_driver_io_registered == 0) {
410	/* Register the I/O driver only once for all cores */
411	if ( grspw_register_io(&grspw_driver_io_major) ) {
412	/* Failed to register I/O driver */
413	free(dev->priv);
414	dev->priv = NULL;
415	return DRVMGR_FAIL;
416	}
417
418	grspw_driver_io_registered = 1;
419	}
420
421	/* I/O system registered and initialized
422	* Now we take care of device initialization.
423	*/
424
425	/* Get frequency in Hz */
426	if ( drvmgr_freq_get(dev, DEV_APB_SLV, &priv->core_freq_khz) ) {
427	return DRVMGR_FAIL;
428	}
429	/* Convert from Hz -> kHz */
430	priv->core_freq_khz = priv->core_freq_khz / 1000;
431
432	if ( grspw_device_init(priv) ) {
433	return DRVMGR_FAIL;
434	}
435
436	/* Get Filesystem name prefix */
437	prefix[0] = '\0';
438	if ( drvmgr_get_dev_prefix(dev, prefix) ) {
439	/* Failed to get prefix, make sure of a unique FS name
440	* by using the driver minor.
441	*/
442	sprintf(priv->devName, "/dev/grspw%d", dev->minor_drv);
443	} else {
444	/* Got special prefix, this means we have a bus prefix
445	* And we should use our "bus minor"
446	*/
447	sprintf(priv->devName, "/dev/%sgrspw%d", prefix, dev->minor_bus);
448	}
449
450	/* Register Device */
451	status = rtems_io_register_name(priv->devName, grspw_driver_io_major, dev->minor_drv);
452	if (status != RTEMS_SUCCESSFUL) {
453	return DRVMGR_FAIL;
454	}
455
456	return DRVMGR_OK;
457	}
458
459	/***************** Driver Implementation *********************/
460
461	int grspw_register_io(rtems_device_major_number *m)
462	{
463	rtems_status_code r;
464
465	if ((r = rtems_io_register_driver(0, &grspw_driver, m)) == RTEMS_SUCCESSFUL) {
466	SPACEWIRE_DBG("GRSPW driver successfully registered, major: %d\n", *m);
467	} else {
468	switch(r) {
469	case RTEMS_TOO_MANY:
470	printk("GRSPW rtems_io_register_driver failed: RTEMS_TOO_MANY\n");
471	return -1;
472	case RTEMS_INVALID_NUMBER:
473	printk("GRSPW rtems_io_register_driver failed: RTEMS_INVALID_NUMBER\n");
474	return -1;
475	case RTEMS_RESOURCE_IN_USE:
476	printk("GRSPW rtems_io_register_driver failed: RTEMS_RESOURCE_IN_USE\n");
477	return -1;
478	default:
479	printk("GRSPW rtems_io_register_driver failed\n");
480	return -1;
481	}
482	}
483	return 0;
484	}
485
486	int grspw_device_init(GRSPW_DEV *pDev)
487	{
488	struct amba_dev_info *ambadev;
489	struct ambapp_core *pnpinfo;
490	union drvmgr_key_value *value;
491
492	/* Get device information from AMBA PnP information */
493	ambadev = (struct amba_dev_info *)pDev->dev->businfo;
494	if ( ambadev == NULL ) {
495	return -1;
496	}
497	pnpinfo = &ambadev->info;
498	pDev->irq = pnpinfo->irq;
499	pDev->regs = (LEON3_SPACEWIRE_Regs_Map *)pnpinfo->apb_slv->start;
500	pDev->minor = pDev->dev->minor_drv;
501
502	/* Get SpaceWire core version */
503	switch( pnpinfo->device ) {
504	case GAISLER_SPW:
505	pDev->core_ver = 1;
506	break;
507	case GAISLER_SPW2:
508	pDev->core_ver = 2;
509	break;
510	case GAISLER_SPW2_DMA:
511	pDev->core_ver = 3;
512	break;
513	default:
514	return -1;
515	}
516
517	/* initialize the code with some resonable values,
518	* actual initialization is done later using ioctl(fd)
519	* on the opened device */
520	pDev->config.rxmaxlen = SPACEWIRE_RXPCK_SIZE;
521	pDev->txdbufsize = SPACEWIRE_TXD_SIZE;
522	pDev->txhbufsize = SPACEWIRE_TXH_SIZE;
523	pDev->rxbufsize = SPACEWIRE_RXPCK_SIZE;
524	pDev->txbufcnt = SPACEWIRE_TXBUFS_NR;
525	pDev->rxbufcnt = SPACEWIRE_RXBUFS_NR;
526
527	pDev->_ptr_rxbuf0 = 0;
528	pDev->ptr_rxbuf0 = 0;
529	pDev->ptr_txdbuf0 = 0;
530	pDev->ptr_txhbuf0 = 0;
531	pDev->ptr_bd0 = 0;
532	pDev->rx_dma_area = 0;
533	pDev->tx_data_dma_area = 0;
534	pDev->tx_hdr_dma_area = 0;
535	pDev->bd_dma_area = 0;
536
537	/* Get Configuration from Bus resources (Let user override defaults) */
538
539	value = drvmgr_dev_key_get(pDev->dev, "txBdCnt", DRVMGR_KT_INT);
540	if ( value )
541	pDev->txbufcnt = value->i;
542
543	value = drvmgr_dev_key_get(pDev->dev, "rxBdCnt", DRVMGR_KT_INT);
544	if ( value )
545	pDev->rxbufcnt = value->i;
546
547	value = drvmgr_dev_key_get(pDev->dev, "txDataSize", DRVMGR_KT_INT);
548	if ( value )
549	pDev->txdbufsize = value->i;
550
551	value = drvmgr_dev_key_get(pDev->dev, "txHdrSize", DRVMGR_KT_INT);
552	if ( value )
553	pDev->txhbufsize = value->i;
554
555	value = drvmgr_dev_key_get(pDev->dev, "rxPktSize", DRVMGR_KT_INT);
556	if ( value ) {
557	pDev->rxbufsize = value->i;
558	pDev->config.rxmaxlen = pDev->rxbufsize;
559	}
560
561	value = drvmgr_dev_key_get(pDev->dev, "rxDmaArea", DRVMGR_KT_INT);
562	if ( value )
563	pDev->rx_dma_area = value->i;
564
565	value = drvmgr_dev_key_get(pDev->dev, "txDataDmaArea", DRVMGR_KT_INT);
566	if ( value )
567	pDev->tx_data_dma_area = value->i;
568
569	value = drvmgr_dev_key_get(pDev->dev, "txHdrDmaArea", DRVMGR_KT_INT);
570	if ( value )
571	pDev->tx_hdr_dma_area = value->i;
572
573	value = drvmgr_dev_key_get(pDev->dev, "bdDmaArea", DRVMGR_KT_INT);
574	if ( value )
575	pDev->bd_dma_area = value->i;
576
577	if (grspw_buffer_alloc(pDev))
578	return RTEMS_NO_MEMORY;
579
580	/* Create semaphores */
581	rtems_semaphore_create(
582	rtems_build_name('T', 'x', 'S', '0' + pDev->minor),
583	0,
584	RTEMS_FIFO \| RTEMS_SIMPLE_BINARY_SEMAPHORE \| RTEMS_NO_INHERIT_PRIORITY \| \
585	RTEMS_NO_PRIORITY_CEILING,
586	0,
587	&(pDev->txsp));
588
589	rtems_semaphore_create(
590	rtems_build_name('R', 'x', 'S', '0' + pDev->minor),
591	0,
592	RTEMS_FIFO \| RTEMS_SIMPLE_BINARY_SEMAPHORE \| RTEMS_NO_INHERIT_PRIORITY \| \
593	RTEMS_NO_PRIORITY_CEILING,
594	0,
595	&(pDev->rxsp));
596
597	grspw_hw_init(pDev);
598
599	return 0;
600	}
601
602	/* Get a value at least 6.4us in number of clock cycles */
603	static unsigned int grspw_calc_timer64(int freq_khz){
604	unsigned int timer64 = (freq_khz*64+9999)/10000;
605	return timer64 & 0xfff;
606	}
607
608	/* Get a value at least 850ns in number of clock cycles - 3 */
609	static unsigned int grspw_calc_disconnect(int freq_khz){
610	unsigned int disconnect = ((freq_khz*85+99999)/100000) - 3;
611	return disconnect & 0x3ff;
612	}
613
614	static int grspw_buffer_alloc(GRSPW_DEV *pDev)
615	{
616	/* RX DMA AREA */
617	if (pDev->rx_dma_area & 1) {
618	/* Address given in remote address */
619	pDev->ptr_rxbuf0_remote = (char *)(pDev->rx_dma_area & ~1);
620	drvmgr_translate_check(
621	pDev->dev,
622	DMAMEM_TO_CPU,
623	(void *)pDev->ptr_rxbuf0_remote,
624	(void **)&pDev->ptr_rxbuf0,
625	pDev->rxbufsize * pDev->rxbufcnt);
626
627	} else {
628	if (pDev->rx_dma_area == 0) {
629	if (pDev->_ptr_rxbuf0)
630	free((void *)pDev->_ptr_rxbuf0);
631	pDev->_ptr_rxbuf0 = (unsigned int) grlib_malloc(
632	pDev->rxbufsize * pDev->rxbufcnt+4);
633	pDev->ptr_rxbuf0 = (char *)((pDev->_ptr_rxbuf0+7)&~7);
634	if ( !pDev->ptr_rxbuf0 )
635	return 1;
636	} else {
637	pDev->ptr_rxbuf0 = (char *)pDev->rx_dma_area;
638	}
639	drvmgr_translate_check(
640	pDev->dev,
641	CPUMEM_TO_DMA,
642	(void *)pDev->ptr_rxbuf0,
643	(void **)&pDev->ptr_rxbuf0_remote,
644	pDev->rxbufsize * pDev->rxbufcnt);
645	}
646
647	/* TX-DATA DMA AREA */
648	if (pDev->tx_data_dma_area & 1) {
649	/* Address given in remote address */
650	pDev->ptr_txdbuf0_remote = (char*)(pDev->tx_data_dma_area & ~1);
651	drvmgr_translate_check(
652	pDev->dev,
653	DMAMEM_TO_CPU,
654	(void *)pDev->ptr_txdbuf0_remote,
655	(void **)&pDev->ptr_txdbuf0,
656	pDev->txdbufsize * pDev->txbufcnt);
657	} else {
658	if (pDev->tx_data_dma_area == 0) {
659	if (pDev->ptr_txdbuf0)
660	free(pDev->ptr_txdbuf0);
661	pDev->ptr_txdbuf0 = (char *) grlib_malloc(
662	pDev->txdbufsize * pDev->txbufcnt);
663	if (!pDev->ptr_txdbuf0)
664	return 1;
665	} else {
666	pDev->ptr_txdbuf0 = (char *)pDev->tx_data_dma_area;
667	}
668	drvmgr_translate_check(
669	pDev->dev,
670	CPUMEM_TO_DMA,
671	(void *)pDev->ptr_txdbuf0,
672	(void **)&pDev->ptr_txdbuf0_remote,
673	pDev->txdbufsize * pDev->txbufcnt);
674	}
675
676	/* TX-HEADER DMA AREA */
677	if (pDev->tx_hdr_dma_area & 1) {
678	/* Address given in remote address */
679	pDev->ptr_txhbuf0_remote = (char *)(pDev->tx_hdr_dma_area & ~1);
680	drvmgr_translate_check(
681	pDev->dev,
682	DMAMEM_TO_CPU,
683	(void *)pDev->ptr_txhbuf0_remote,
684	(void **)&pDev->ptr_txhbuf0,
685	pDev->txhbufsize * pDev->txbufcnt);
686	} else {
687	if (pDev->tx_hdr_dma_area == 0) {
688	if (pDev->ptr_txhbuf0)
689	free(pDev->ptr_txhbuf0);
690	pDev->ptr_txhbuf0 = (char *) grlib_malloc(
691	pDev->txhbufsize * pDev->txbufcnt);
692	if (!pDev->ptr_txhbuf0)
693	return 1;
694	} else {
695	pDev->ptr_txhbuf0 = (char *)pDev->tx_hdr_dma_area;
696	}
697	drvmgr_translate_check(
698	pDev->dev,
699	CPUMEM_TO_DMA,
700	(void *)pDev->ptr_txhbuf0,
701	(void **)&pDev->ptr_txhbuf0_remote,
702	pDev->txhbufsize * pDev->txbufcnt);
703	}
704
705	/* DMA DESCRIPTOR TABLES */
706	if (pDev->bd_dma_area & 1) {
707	/* Address given in remote address */
708	pDev->ptr_bd0_remote = (char *)(pDev->bd_dma_area & ~1);
709	drvmgr_translate_check(
710	pDev->dev,
711	DMAMEM_TO_CPU,
712	(void *)pDev->ptr_bd0_remote,
713	(void **)&pDev->ptr_bd0,
714	2 * SPACEWIRE_BDTABLE_SIZE);
715	} else {
716	if (pDev->bd_dma_area == 0) {
717	if (pDev->_ptr_bd0)
718	free(pDev->_ptr_bd0);
719	pDev->_ptr_bd0 =
720	rtems_heap_allocate_aligned_with_boundary(
721	SPACEWIRE_BDTABLE_SIZE*2, 1024, 0);
722	if (!pDev->_ptr_bd0)
723	return 1;
724	pDev->ptr_bd0 = (char *)pDev->_ptr_bd0;
725	} else {
726	pDev->ptr_bd0 = (char *)pDev->bd_dma_area;
727	}
728	drvmgr_translate_check(
729	pDev->dev,
730	CPUMEM_TO_DMA,
731	(void *)pDev->ptr_bd0,
732	(void **)&pDev->ptr_bd0_remote,
733	2 * SPACEWIRE_BDTABLE_SIZE);
734	}
735
736	return 0;
737	}
738
739	static void grspw_interrupt(void *arg)
740	{
741	GRSPW_DEV pDev = (GRSPW_DEV )arg;
742	int dmactrl;
743	int status;
744	int ctrl;
745	unsigned int timecode;
746
747	status = SPW_STATUS_READ(pDev);
748	/SPW_STATUS_WRITE(pDev, SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \| SPW_STATUS_WE \| SPW_STATUS_IA \| SPW_STATUS_EE \| SPW_STATUS_TO);/
749	SPW_STATUS_WRITE(pDev, status & (SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \| SPW_STATUS_WE \| SPW_STATUS_IA \| SPW_STATUS_EE));
750
751	/* Make sure to put the timecode handling first in order to get the smallest
752	* possible interrupt latency
753	*/
754	if ( (status & SPW_STATUS_TO) && (grspw_timecode_callback != NULL) ) {
755	/* Timecode received. Let custom function handle this */
756	SPW_STATUS_WRITE(pDev, SPW_STATUS_TO);
757	timecode = SPW_READ(&pDev->regs->time);
758	(grspw_timecode_callback)(pDev,pDev->regs,pDev->minor,timecode);
759	}
760
761	/* Clear SPW_DMACTRL_PR if set */
762	dmactrl = SPW_READ(&pDev->regs->dma0ctrl);
763	/SPW_WRITE(&pDev->regs->dma0ctrl, dmactrl \| SPW_DMACTRL_PR);/
764	SPW_WRITE(&pDev->regs->dma0ctrl, dmactrl);
765
766	/* If linkinterrupts are enabled check if it was a linkerror irq and then send an event to the
767	process set in the config */
768	if (pDev->config.link_err_irq) {
769	if (status & (SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \| SPW_STATUS_WE)) {
770	rtems_event_send(pDev->config.event_id, SPW_LINKERR_EVENT);
771	if (pDev->config.disable_err) {
772	/* disable link*/
773	SPW_CTRL_WRITE(pDev, (SPW_CTRL_READ(pDev) & 0xFFFFFFFC) \| SPW_CTRL_LINKDISABLED);
774	pDev->config.linkdisabled = 1;
775	pDev->config.linkstart = 0;
776	pDev->running = 0;
777	}
778	}
779	}
780	if (status & SPW_STATUS_CE) {
781	pDev->stat.credit_err++;
782	}
783	if (status & SPW_STATUS_ER) {
784	pDev->stat.escape_err++;
785	}
786	if (status & SPW_STATUS_DE) {
787	pDev->stat.disconnect_err++;
788	}
789	if (status & SPW_STATUS_PE) {
790	pDev->stat.parity_err++;
791	}
792	if (status & SPW_STATUS_WE) {
793	pDev->stat.write_sync_err++;
794	}
795	if (status & SPW_STATUS_IA) {
796	pDev->stat.invalid_address++;
797	}
798	if (status & SPW_STATUS_EE) {
799	pDev->stat.early_ep++;
800	}
801
802	/* Check for tx interrupts */
803	while( (pDev->tx_sent != pDev->tx_cur) \|\| pDev->tx_all_in_use) {
804	/* Has this descriptor been sent? */
805	ctrl = SPW_READ((volatile void *)&pDev->tx[pDev->tx_sent].ctrl);
806	if ( ctrl & SPW_TXBD_EN ) {
807	break;
808	}
809	/* Yes, increment status counters & tx_sent so we can use this descriptor to send more packets with */
810	pDev->stat.packets_sent++;
811
812	rtems_semaphore_release(pDev->txsp);
813
814	if ( ctrl & SPW_TXBD_LE ) {
815	pDev->stat.tx_link_err++;
816	}
817
818	/* step to next descriptor */
819	pDev->tx_sent = (pDev->tx_sent + 1) % pDev->txbufcnt;
820	pDev->tx_all_in_use = 0; /* not all of the descriptors can be in use since we just freed one. */
821	}
822
823	/* Check for rx interrupts */
824	if (dmactrl & SPW_DMACTRL_PR) {
825	rtems_semaphore_release(pDev->rxsp);
826	}
827	}
828
829	static rtems_device_driver grspw_initialize(
830	rtems_device_major_number major,
831	rtems_device_minor_number minor,
832	void *arg
833	)
834	{
835	/* Initialize device-common data structures here */
836	return RTEMS_SUCCESSFUL;
837	}
838
839	static rtems_device_driver grspw_open(
840	rtems_device_major_number major,
841	rtems_device_minor_number minor,
842	void * arg
843	)
844	{
845	GRSPW_DEV *pDev;
846	struct drvmgr_dev *dev;
847	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "open [%i,%i]\n", major, minor);
848
849	if ( drvmgr_get_dev(&grspw_drv_info.general, minor, &dev) ) {
850	SPACEWIRE_DBG("Wrong minor %d\n", minor);
851	return RTEMS_INVALID_NAME;
852	}
853	pDev = (GRSPW_DEV *)dev->priv;
854
855	if ( pDev->open )
856	return RTEMS_RESOURCE_IN_USE;
857
858	/* Mark device open */
859	pDev->open = 1;
860
861	pDev->stat.tx_link_err = 0;
862	pDev->stat.rx_rmap_header_crc_err = 0;
863	pDev->stat.rx_rmap_data_crc_err = 0;
864	pDev->stat.rx_eep_err = 0;
865	pDev->stat.rx_truncated = 0;
866	pDev->stat.parity_err = 0;
867	pDev->stat.escape_err = 0;
868	pDev->stat.credit_err = 0;
869	pDev->stat.write_sync_err = 0;
870	pDev->stat.disconnect_err = 0;
871	pDev->stat.early_ep = 0;
872	pDev->stat.invalid_address = 0;
873	pDev->stat.packets_sent = 0;
874	pDev->stat.packets_received = 0;
875
876	pDev->config.rm_prot_id = 0;
877	pDev->config.keep_source = 0;
878	pDev->config.check_rmap_err = 0;
879	pDev->config.tx_blocking = 0;
880	pDev->config.tx_block_on_full = 0;
881	pDev->config.rx_blocking = 0;
882	pDev->config.disable_err = 0;
883	pDev->config.link_err_irq = 0;
884	pDev->config.event_id = 0;
885	pDev->config.rtimeout = 0;
886
887	pDev->running = 0;
888	pDev->core_freq_khz = 0;
889
890	/* Reset Core */
891	grspw_hw_reset(pDev);
892
893	/* Read default configuration */
894	grspw_hw_read_config(pDev);
895
896	return RTEMS_SUCCESSFUL;
897	}
898
899	static rtems_device_driver grspw_close(
900	rtems_device_major_number major,
901	rtems_device_minor_number minor,
902	void * arg
903	)
904	{
905	GRSPW_DEV *pDev;
906	struct drvmgr_dev *dev;
907
908	if ( drvmgr_get_dev(&grspw_drv_info.general, minor, &dev) ) {
909	return RTEMS_INVALID_NAME;
910	}
911	pDev = (GRSPW_DEV *)dev->priv;
912
913	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "close [%i,%i]\n", major, minor);
914	rtems_semaphore_delete(pDev->txsp);
915	rtems_semaphore_delete(pDev->rxsp);
916
917	grspw_hw_stop(pDev,1,1);
918
919	grspw_hw_reset(pDev);
920
921	/* Mark device closed - not open */
922	pDev->open = 0;
923
924	return RTEMS_SUCCESSFUL;
925	}
926
927	static rtems_device_driver grspw_read(
928	rtems_device_major_number major,
929	rtems_device_minor_number minor,
930	void * arg
931	)
932	{
933	rtems_libio_rw_args_t *rw_args;
934	unsigned int count = 0;
935	GRSPW_DEV *pDev;
936	struct drvmgr_dev *dev;
937	int status;
938
939	if ( drvmgr_get_dev(&grspw_drv_info.general, minor, &dev) ) {
940	return RTEMS_INVALID_NAME;
941	}
942	pDev = (GRSPW_DEV *)dev->priv;
943
944	rw_args = (rtems_libio_rw_args_t *) arg;
945
946	/* is link up? */
947	if ( !pDev->running ) {
948	return RTEMS_INVALID_NAME;
949	}
950
951	if ((rw_args->count < 1) \|\| (rw_args->buffer == NULL)) {
952	return RTEMS_INVALID_NAME;
953	}
954
955	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "read [%i,%i]: buf:0x%x len:%i \n", major, minor, (unsigned int)rw_args->buffer, rw_args->count);
956
957	while ( (count = grspw_hw_receive(pDev, rw_args->buffer, rw_args->count)) == 0) {
958	/* wait a moment for any descriptors to get available
959	*
960	* Semaphore is signaled by interrupt handler
961	*/
962	if (pDev->config.rx_blocking) {
963	SPACEWIRE_DBG2("Rx blocking\n");
964	if ( pDev->config.rtimeout ) {
965	status = rtems_semaphore_obtain(pDev->rxsp, RTEMS_WAIT, pDev->config.rtimeout);
966	if ( status == RTEMS_TIMEOUT )
967	return RTEMS_TIMEOUT;
968	} else {
969	rtems_semaphore_obtain(pDev->rxsp, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
970	}
971	} else {
972	SPACEWIRE_DBG2("Rx non blocking\n");
973	return RTEMS_RESOURCE_IN_USE;
974	}
975	}
976
977	#ifdef DEBUG_SPACEWIRE_ONOFF
978	if (DEBUG_SPACEWIRE_FLAGS & DBGSPW_DUMP) {
979	int k;
980	for (k = 0; k < count; k++){
981	if (k % 16 == 0) {
982	printf ("\n");
983	}
984	printf ("%.2x(%c) ", rw_args->buffer[k] & 0xff, isprint(rw_args->buffer[k] & 0xff) ? rw_args->buffer[k] & 0xff : ' ');
985	}
986	printf ("\n");
987	}
988	#endif
989
990	rw_args->bytes_moved = count;
991	return RTEMS_SUCCESSFUL;
992	}
993
994	static rtems_device_driver grspw_write(
995	rtems_device_major_number major,
996	rtems_device_minor_number minor,
997	void * arg
998	)
999	{
1000	rtems_libio_rw_args_t *rw_args;
1001	GRSPW_DEV *pDev;
1002	struct drvmgr_dev *dev;
1003
1004	if ( drvmgr_get_dev(&grspw_drv_info.general, minor, &dev) ) {
1005	return RTEMS_INVALID_NAME;
1006	}
1007	pDev = (GRSPW_DEV *)dev->priv;
1008
1009	rw_args = (rtems_libio_rw_args_t *) arg;
1010	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "write [%i,%i]: buf:0x%x len:%i\n", major, minor, (unsigned int)rw_args->buffer, rw_args->count);
1011
1012	/* is link up? */
1013	if ( !pDev->running ) {
1014	return RTEMS_INVALID_NAME;
1015	}
1016
1017	if ((rw_args->count > pDev->txdbufsize) \|\| (rw_args->count < 1) \|\| (rw_args->buffer == NULL)) {
1018	return RTEMS_INVALID_NAME;
1019	}
1020
1021	while ((rw_args->bytes_moved = grspw_hw_send(pDev, 0, NULL, rw_args->count, rw_args->buffer, 0)) == 0) {
1022	if (pDev->config.tx_block_on_full == 1) {
1023	SPACEWIRE_DBG2("Tx Block on full \n");
1024	rtems_semaphore_obtain(pDev->txsp, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
1025	} else {
1026	SPACEWIRE_DBG2("Tx non blocking return when full \n");
1027	return RTEMS_RESOURCE_IN_USE;
1028	}
1029	}
1030	return RTEMS_SUCCESSFUL;
1031	}
1032
1033	static rtems_device_driver grspw_control(
1034	rtems_device_major_number major,
1035	rtems_device_minor_number minor,
1036	void * arg
1037	)
1038	{
1039	spw_ioctl_pkt_send *args;
1040	spw_ioctl_packetsize *ps;
1041	int status;
1042	unsigned int tmp,mask,nodeaddr,nodemask;
1043	int timeout;
1044	rtems_device_driver ret;
1045	rtems_libio_ioctl_args_t ioarg = (rtems_libio_ioctl_args_t ) arg;
1046	GRSPW_DEV *pDev;
1047	struct drvmgr_dev *dev;
1048
1049	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "ctrl [%i,%i]\n", major, minor);
1050
1051	if ( drvmgr_get_dev(&grspw_drv_info.general, minor, &dev) ) {
1052	return RTEMS_INVALID_NAME;
1053	}
1054	pDev = (GRSPW_DEV *)dev->priv;
1055
1056	if (!ioarg)
1057	return RTEMS_INVALID_NAME;
1058
1059	ioarg->ioctl_return = 0;
1060	switch(ioarg->command) {
1061	case SPACEWIRE_IOCTRL_SET_NODEADDR:
1062	/set node address/
1063	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_NODEADDR %i\n",(unsigned int)ioarg->buffer);
1064	if ((unsigned int)ioarg->buffer > 255) {
1065	return RTEMS_INVALID_NAME;
1066	}
1067	nodeaddr = ((unsigned int)ioarg->buffer) & 0xff;
1068	tmp = SPW_READ(&pDev->regs->nodeaddr);
1069	tmp &= 0xffffff00; /* Remove old address */
1070	tmp \|= nodeaddr;
1071	SPW_WRITE(&pDev->regs->nodeaddr, tmp);
1072	if ((SPW_READ(&pDev->regs->nodeaddr)&0xff) != nodeaddr) {
1073	return RTEMS_IO_ERROR;
1074	}
1075	pDev->config.nodeaddr = nodeaddr;
1076	break;
1077	case SPACEWIRE_IOCTRL_SET_NODEMASK:
1078	/set node address/
1079	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_NODEMASK %i\n",(unsigned int)ioarg->buffer);
1080	if ( pDev->core_ver > 1 ){
1081	if ((unsigned int)ioarg->buffer > 255) {
1082	return RTEMS_INVALID_NAME;
1083	}
1084	nodemask = ((unsigned int)ioarg->buffer) & 0xff;
1085	tmp = SPW_READ(&pDev->regs->nodeaddr);
1086	tmp &= 0xffff00ff; /* Remove old mask */
1087	tmp \|= nodemask<<8;
1088	SPW_WRITE(&pDev->regs->nodeaddr, tmp);
1089	if (((SPW_READ(&pDev->regs->nodeaddr)>>8)&0xff) != nodemask) {
1090	return RTEMS_IO_ERROR;
1091	}
1092	pDev->config.nodemask = nodemask;
1093	}else{
1094	SPACEWIRE_DBG("SPACEWIRE_IOCTRL_SET_NODEMASK: not implemented in GRSPW1 HW\n");
1095	}
1096	break;
1097	case SPACEWIRE_IOCTRL_SET_RXBLOCK:
1098	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_RXBLOCK %i \n", (unsigned int)ioarg->buffer);
1099	if ((unsigned int)ioarg->buffer > 1) {
1100	return RTEMS_INVALID_NAME;
1101	}
1102	pDev->config.rx_blocking = (unsigned int)ioarg->buffer;
1103	break;
1104	case SPACEWIRE_IOCTRL_SET_DESTKEY:
1105	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_DESTKEY %i\n", (unsigned int)ioarg->buffer);
1106	if (!pDev->config.is_rmap) {
1107	return RTEMS_NOT_IMPLEMENTED;
1108	}
1109	if ((unsigned int)ioarg->buffer > 255) {
1110	return RTEMS_INVALID_NAME;
1111	}
1112	SPW_WRITE(&pDev->regs->destkey, (unsigned int)ioarg->buffer);
1113	if (SPW_READ(&pDev->regs->destkey) != (unsigned int)ioarg->buffer) {
1114	return RTEMS_IO_ERROR;
1115	}
1116	pDev->config.destkey = (unsigned int)ioarg->buffer;
1117	break;
1118	case SPACEWIRE_IOCTRL_SET_CLKDIV:
1119	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_CLKDIV %i\n", (unsigned int)ioarg->buffer);
1120	if ((unsigned int)ioarg->buffer > 255) {
1121	return RTEMS_INVALID_NAME;
1122	}
1123	if ( pDev->core_ver == 3 )
1124	break;
1125	tmp = SPW_READ(&pDev->regs->clkdiv);
1126	tmp &= ~0xff; /* Remove old Clockdiv Setting */
1127	tmp \|= ((unsigned int)ioarg->buffer) & 0xff; /* add new clockdiv setting */
1128	SPW_WRITE(&pDev->regs->clkdiv, tmp);
1129	if (SPW_READ(&pDev->regs->clkdiv) != tmp) {
1130	return RTEMS_IO_ERROR;
1131	}
1132	pDev->config.clkdiv = tmp;
1133	break;
1134	case SPACEWIRE_IOCTRL_SET_CLKDIVSTART:
1135	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_CLKDIVSTART %i\n", (unsigned int)ioarg->buffer);
1136	if ((unsigned int)ioarg->buffer > 255) {
1137	return RTEMS_INVALID_NAME;
1138	}
1139	if ( pDev->core_ver == 3 )
1140	break;
1141	tmp = SPW_READ(&pDev->regs->clkdiv);
1142	tmp &= ~0xff00; /* Remove old Clockdiv Start Setting */
1143	tmp \|= (((unsigned int)ioarg->buffer) & 0xff)<<8; /* add new clockdiv start setting */
1144	SPW_WRITE(&pDev->regs->clkdiv, tmp);
1145	if (SPW_READ(&pDev->regs->clkdiv) != tmp) {
1146	return RTEMS_IO_ERROR;
1147	}
1148	pDev->config.clkdiv = tmp;
1149	break;
1150	case SPACEWIRE_IOCTRL_SET_TIMER:
1151	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_TIMER %i\n", (unsigned int)ioarg->buffer);
1152	if ( pDev->core_ver <= 1 ) {
1153	if ((unsigned int)ioarg->buffer > 4095) {
1154	return RTEMS_INVALID_NAME;
1155	}
1156	SPW_WRITE(&pDev->regs->timer, (SPW_READ(&pDev->regs->timer) & 0xFFFFF000) \| ((unsigned int)ioarg->buffer & 0xFFF));
1157	if ((SPW_READ(&pDev->regs->timer) & 0xFFF) != (unsigned int)ioarg->buffer) {
1158	return RTEMS_IO_ERROR;
1159	}
1160	pDev->config.timer = (unsigned int)ioarg->buffer;
1161	}else{
1162	SPACEWIRE_DBG("SPACEWIRE_IOCTRL_SET_TIMER: removed in GRSPW2 HW\n");
1163	}
1164	break;
1165	case SPACEWIRE_IOCTRL_SET_DISCONNECT:
1166	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_DISCONNECT %i\n", (unsigned int)ioarg->buffer);
1167	if ( pDev->core_ver <= 1 ) {
1168	if ((unsigned int)ioarg->buffer > 1023) {
1169	return RTEMS_INVALID_NAME;
1170	}
1171	SPW_WRITE(&pDev->regs->timer, (SPW_READ(&pDev->regs->timer) & 0xFFC00FFF) \| (((unsigned int)ioarg->buffer & 0x3FF) << 12));
1172	if (((SPW_READ(&pDev->regs->timer) >> 12) & 0x3FF) != (unsigned int)ioarg->buffer) {
1173	return RTEMS_IO_ERROR;
1174	}
1175	pDev->config.disconnect = (unsigned int)ioarg->buffer;
1176	}else{
1177	SPACEWIRE_DBG("SPACEWIRE_IOCTRL_SET_DISCONNECT: not implemented for GRSPW2\n");
1178	}
1179	break;
1180	case SPACEWIRE_IOCTRL_SET_PROMISCUOUS:
1181	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_PROMISCUOUS %i \n", (unsigned int)ioarg->buffer);
1182	if ((unsigned int)ioarg->buffer > 1) {
1183	return RTEMS_INVALID_NAME;
1184	}
1185	SPW_CTRL_WRITE(pDev, SPW_CTRL_READ(pDev) \| ((unsigned int)ioarg->buffer << 5));
1186	if (((SPW_CTRL_READ(pDev) >> 5) & 1) != (unsigned int)ioarg->buffer) {
1187	return RTEMS_IO_ERROR;
1188	}
1189	pDev->config.promiscuous = (unsigned int)ioarg->buffer;
1190	break;
1191	case SPACEWIRE_IOCTRL_SET_RMAPEN:
1192	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_RMAPEN %i \n", (unsigned int)ioarg->buffer);
1193	if ((unsigned int)ioarg->buffer > 1) {
1194	return RTEMS_INVALID_NAME;
1195	}
1196	SPW_CTRL_WRITE(pDev, (SPW_CTRL_READ(pDev) & 0xFFFEFFFF) \| ((unsigned int)ioarg->buffer << 16));
1197	if (((SPW_CTRL_READ(pDev) >> 16) & 1) != (unsigned int)ioarg->buffer) {
1198	return RTEMS_IO_ERROR;
1199	}
1200	pDev->config.rmapen = (unsigned int)ioarg->buffer;
1201	break;
1202	case SPACEWIRE_IOCTRL_SET_RMAPBUFDIS:
1203	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_RMAPBUFDIS %i \n", (unsigned int)ioarg->buffer);
1204	if ((unsigned int)ioarg->buffer > 1) {
1205	return RTEMS_INVALID_NAME;
1206	}
1207	SPW_CTRL_WRITE(pDev, (SPW_CTRL_READ(pDev) & 0xFFFDFFFF) \| ((unsigned int)ioarg->buffer << 17));
1208	if (((SPW_CTRL_READ(pDev) >> 17) & 1) != (unsigned int)ioarg->buffer) {
1209	return RTEMS_IO_ERROR;
1210	}
1211	pDev->config.rmapbufdis = (unsigned int)ioarg->buffer;
1212	break;
1213	case SPACEWIRE_IOCTRL_SET_CHECK_RMAP:
1214	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_CHECK_RMAP %i \n", (unsigned int)ioarg->buffer);
1215	if ((unsigned int)ioarg->buffer > 1) {
1216	return RTEMS_INVALID_NAME;
1217	}
1218	pDev->config.check_rmap_err = (unsigned int)ioarg->buffer;
1219	break;
1220	case SPACEWIRE_IOCTRL_SET_RM_PROT_ID:
1221	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_RM_PROT_ID %i \n", (unsigned int)ioarg->buffer);
1222	if ((unsigned int)ioarg->buffer > 1) {
1223	return RTEMS_INVALID_NAME;
1224	}
1225	pDev->config.rm_prot_id = (unsigned int)ioarg->buffer;
1226	break;
1227	case SPACEWIRE_IOCTRL_SET_KEEP_SOURCE:
1228	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_KEEP_SOURCE %i \n", (unsigned int)ioarg->buffer);
1229	if ((unsigned int)ioarg->buffer > 1) {
1230	return RTEMS_INVALID_NAME;
1231	}
1232	pDev->config.keep_source = (unsigned int)ioarg->buffer;
1233	break;
1234	case SPACEWIRE_IOCTRL_SET_TXBLOCK:
1235	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_TXBLOCK %i \n", (unsigned int)ioarg->buffer);
1236	if ((unsigned int)ioarg->buffer > 1) {
1237	return RTEMS_INVALID_NAME;
1238	}
1239	pDev->config.tx_blocking = (unsigned int)ioarg->buffer;
1240	break;
1241	case SPACEWIRE_IOCTRL_SET_TXBLOCK_ON_FULL:
1242	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_TXBLOCK_ON_FULL %i \n", (unsigned int)ioarg->buffer);
1243	if ((unsigned int)ioarg->buffer > 1) {
1244	return RTEMS_INVALID_NAME;
1245	}
1246	pDev->config.tx_block_on_full = (unsigned int)ioarg->buffer;
1247	break;
1248	case SPACEWIRE_IOCTRL_SET_DISABLE_ERR:
1249	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_DISABLE_ERR %i \n", (unsigned int)ioarg->buffer);
1250	if ((unsigned int)ioarg->buffer > 1) {
1251	return RTEMS_INVALID_NAME;
1252	}
1253	pDev->config.disable_err = (unsigned int)ioarg->buffer;
1254	break;
1255	case SPACEWIRE_IOCTRL_SET_LINK_ERR_IRQ:
1256	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_LINK_ERR_IRQ %i \n", (unsigned int)ioarg->buffer);
1257	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "CTRL REG: %x\n", SPW_CTRL_READ(pDev));
1258	if ((unsigned int)ioarg->buffer > 1) {
1259	return RTEMS_INVALID_NAME;
1260	}
1261	tmp = (SPW_CTRL_READ(pDev) & 0xFFFFFDF7) \| ((unsigned int)ioarg->buffer << 9);
1262	if (tmp & (SPW_CTRL_LI\|SPW_CTRL_TQ))
1263	tmp \|= SPW_CTRL_IE;
1264	SPW_CTRL_WRITE(pDev, tmp);
1265	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "CTRL REG: %x\n", SPW_CTRL_READ(pDev));
1266	if (((SPW_CTRL_READ(pDev) >> 9) & 1) != (unsigned int)ioarg->buffer) {
1267	return RTEMS_IO_ERROR;
1268	}
1269	pDev->config.link_err_irq = (unsigned int)ioarg->buffer;
1270	break;
1271	case SPACEWIRE_IOCTRL_SET_EVENT_ID:
1272	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "SPACEWIRE_IOCTRL_SET_EVENT_ID %i \n", (unsigned int)ioarg->buffer);
1273	pDev->config.event_id = (rtems_id)ioarg->buffer;
1274	SPACEWIRE_DBGC(DBGSPW_IOCTRL, "Event id: %i\n", pDev->config.event_id);
1275	break;
1276
1277	/* Change MAX Packet size by:
1278	* - stop RX/TX (if on)
1279	* - wait for hw to complete RX DMA (if on)
1280	* - reallocate buffers with new size
1281	* - tell hw about new size & start RX/TX again (if previously on)
1282	*/
1283	case SPACEWIRE_IOCTRL_SET_PACKETSIZE:
1284	if (ioarg->buffer == NULL)
1285	return RTEMS_INVALID_NAME;
1286	ps = (spw_ioctl_packetsize*) ioarg->buffer;
1287	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_SET_RXPACKETSIZE %i \n", (unsigned int)ioarg->buffer);
1288
1289	tmp = pDev->running;
1290
1291	if ( pDev->running ){
1292	/* Stop RX */
1293	grspw_hw_stop(pDev,1,1);
1294
1295	/* If packetsize fails it is good to know if in running mode */
1296	pDev->running = 0;
1297
1298	/* Wait for Receiver to finnish pending DMA transfers if any */
1299	grspw_hw_wait_rx_inactive(pDev);
1300	}
1301
1302	/* Save new buffer sizes */
1303	pDev->rxbufsize = ((ps->rxsize+7)&~7);
1304	pDev->txdbufsize = ps->txdsize;
1305	pDev->txhbufsize = ps->txhsize;
1306	pDev->config.rxmaxlen = pDev->rxbufsize;
1307
1308	/* Free previous buffers & allocate buffers with new size */
1309	if (grspw_buffer_alloc(pDev))
1310	return RTEMS_NO_MEMORY;
1311
1312	/* if RX was actived before, we reactive it again */
1313	if ( tmp ) {
1314	if ( (status = grspw_hw_startup(pDev,-1)) != RTEMS_SUCCESSFUL ) {
1315	return status;
1316	}
1317	pDev->running = 1;
1318	}
1319	#if 0
1320	/* Rewrite previous config which was wasted due to reset in hw_startup */
1321	SPW_WRITE(&pDev->regs->nodeaddr, pDev->config.nodeaddr);
1322	SPW_WRITE(&pDev->regs->destkey, pDev->config.destkey);
1323	SPW_WRITE(&pDev->regs->clkdiv, pDev->config.clkdiv);
1324	SPW_WRITE(&pDev->regs->timer, pDev->config.timer \| ( (pDev->config.disconnect & 0x3FF) << 12) );
1325	SPW_CTRL_WRITE(pDev, (SPW_CTRL_READ(pDev) & !(SPW_CTRL_LINKSTART \| SPW_CTRL_PM \| SPW_CTRL_RE \| SPW_CTRL_RD \| SPW_CTRL_TT \| SPW_CTRL_TR)) \| \
1326	(pDev->config.promiscuous << 5) \| (pDev->config.rmapen << 16) \| (pDev->config.rmapbufdis << 17) \| \
1327	(pDev->config.linkdisabled) \| (pDev->config.linkstart << 1));
1328	#endif
1329	break;
1330	case SPACEWIRE_IOCTRL_GET_CONFIG:
1331	if (ioarg->buffer == NULL)
1332	return RTEMS_INVALID_NAME;
1333	SPACEWIRE_DBG2("SPACEWIRE_IOCTRL_GET_CONFIG \n");
1334	((spw_config )ioarg->buffer).nodeaddr = pDev->config.nodeaddr;
1335	((spw_config )ioarg->buffer).nodemask = pDev->config.nodemask;
1336	((spw_config )ioarg->buffer).destkey = pDev->config.destkey;
1337	((spw_config )ioarg->buffer).clkdiv = pDev->config.clkdiv;
1338	((spw_config )ioarg->buffer).rxmaxlen = pDev->config.rxmaxlen;
1339	((spw_config )ioarg->buffer).timer = pDev->config.timer;
1340	((spw_config )ioarg->buffer).disconnect = pDev->config.disconnect;
1341	((spw_config )ioarg->buffer).promiscuous = pDev->config.promiscuous;
1342	((spw_config )ioarg->buffer).rmapen = pDev->config.rmapen;
1343	((spw_config )ioarg->buffer).rmapbufdis = pDev->config.rmapbufdis;
1344	((spw_config )ioarg->buffer).check_rmap_err = pDev->config.check_rmap_err;
1345	((spw_config )ioarg->buffer).rm_prot_id = pDev->config.rm_prot_id;
1346	((spw_config )ioarg->buffer).tx_blocking = pDev->config.tx_blocking;
1347	((spw_config )ioarg->buffer).disable_err = pDev->config.disable_err;
1348	((spw_config )ioarg->buffer).link_err_irq = pDev->config.link_err_irq;
1349	((spw_config )ioarg->buffer).event_id = pDev->config.event_id;
1350	((spw_config )ioarg->buffer).is_rmap = pDev->config.is_rmap;
1351	((spw_config )ioarg->buffer).is_rmapcrc = pDev->config.is_rmapcrc;
1352	((spw_config )ioarg->buffer).is_rxunaligned = pDev->config.is_rxunaligned;
1353	((spw_config )ioarg->buffer).linkdisabled = pDev->config.linkdisabled;
1354	((spw_config )ioarg->buffer).linkstart = pDev->config.linkstart;
1355	((spw_config )ioarg->buffer).rx_blocking = pDev->config.rx_blocking;
1356	((spw_config )ioarg->buffer).tx_block_on_full = pDev->config.tx_block_on_full;
1357	((spw_config )ioarg->buffer).keep_source = pDev->config.keep_source;
1358	((spw_config )ioarg->buffer).rtimeout = pDev->config.rtimeout;
1359	break;
1360	case SPACEWIRE_IOCTRL_GET_LINK_STATUS:
1361	SPACEWIRE_DBGC(DBGSPW_IOCTRL,"SPACEWIRE_IOCTRL_GET_STATUS=%i \n", (unsigned int)((SPW_STATUS_READ(pDev) >> 21) & 0x7));
1362	(unsigned int )ioarg->buffer = (unsigned int )((SPW_STATUS_READ(pDev) >> 21) & 0x7);
1363	break;
1364	case SPACEWIRE_IOCTRL_GET_STATISTICS:
1365	if (ioarg->buffer == NULL)
1366	return RTEMS_INVALID_NAME;
1367	SPACEWIRE_DBG2("SPACEWIRE_IOCTRL_GET_STATISTICS \n");
1368	((spw_stats )ioarg->buffer).tx_link_err = pDev->stat.tx_link_err;
1369	((spw_stats )ioarg->buffer).rx_rmap_header_crc_err = pDev->stat.rx_rmap_header_crc_err;
1370	((spw_stats )ioarg->buffer).rx_rmap_data_crc_err = pDev->stat.rx_rmap_data_crc_err;
1371	((spw_stats )ioarg->buffer).rx_eep_err = pDev->stat.rx_eep_err;
1372	((spw_stats )ioarg->buffer).rx_truncated = pDev->stat.rx_truncated;
1373	((spw_stats )ioarg->buffer).parity_err = pDev->stat.parity_err;
1374	((spw_stats )ioarg->buffer).escape_err = pDev->stat.escape_err;
1375	((spw_stats )ioarg->buffer).credit_err = pDev->stat.credit_err;
1376	((spw_stats )ioarg->buffer).write_sync_err = pDev->stat.write_sync_err;
1377	((spw_stats )ioarg->buffer).disconnect_err = pDev->stat.disconnect_err;
1378	((spw_stats )ioarg->buffer).early_ep = pDev->stat.early_ep;
1379	((spw_stats )ioarg->buffer).invalid_address = pDev->stat.invalid_address;
1380	((spw_stats )ioarg->buffer).packets_sent = pDev->stat.packets_sent;
1381	((spw_stats )ioarg->buffer).packets_received = pDev->stat.packets_received;
1382	break;
1383	case SPACEWIRE_IOCTRL_CLR_STATISTICS:
1384	SPACEWIRE_DBG2("SPACEWIRE_IOCTRL_CLR_STATISTICS \n");
1385	pDev->stat.tx_link_err = 0;
1386	pDev->stat.rx_rmap_header_crc_err = 0;
1387	pDev->stat.rx_rmap_data_crc_err = 0;
1388	pDev->stat.rx_eep_err = 0;
1389	pDev->stat.rx_truncated = 0;
1390	pDev->stat.parity_err = 0;
1391	pDev->stat.escape_err = 0;
1392	pDev->stat.credit_err = 0;
1393	pDev->stat.write_sync_err = 0;
1394	pDev->stat.disconnect_err = 0;
1395	pDev->stat.early_ep = 0;
1396	pDev->stat.invalid_address = 0;
1397	pDev->stat.packets_sent = 0;
1398	pDev->stat.packets_received = 0;
1399	break;
1400	case SPACEWIRE_IOCTRL_SEND:
1401	if (ioarg->buffer == NULL)
1402	return RTEMS_INVALID_NAME;
1403	args = (spw_ioctl_pkt_send *)ioarg->buffer;
1404	args->sent = 0;
1405
1406	/* is link up? */
1407	if ( !pDev->running ) {
1408	return RTEMS_INVALID_NAME;
1409	}
1410
1411	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "write [%i,%i]: hlen: %i hbuf:0x%x dlen:%i dbuf:0x%x\n", major, minor,
1412	(unsigned int)args->hlen, (int)args->hdr,(unsigned int)args->dlen, (int)args->data);
1413
1414	if ((args->hlen > pDev->txhbufsize) \|\| (args->dlen > pDev->txdbufsize) \|\|
1415	((args->hlen+args->dlen) < 1) \|\|
1416	((args->hdr == NULL) && (args->hlen != 0)) \|\| ((args->data == NULL) && (args->dlen != 0))) {
1417	return RTEMS_INVALID_NAME;
1418	}
1419	while ((args->sent = grspw_hw_send(pDev, args->hlen, args->hdr, args->dlen, args->data, args->options)) == 0) {
1420	if (pDev->config.tx_block_on_full == 1) {
1421	SPACEWIRE_DBG2("Tx Block on full \n");
1422	rtems_semaphore_obtain(pDev->txsp, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
1423	} else {
1424	SPACEWIRE_DBG2("Tx non blocking return when full \n");
1425	return RTEMS_RESOURCE_IN_USE;
1426	}
1427	}
1428	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "Tx ioctl return: %i \n", args->sent);
1429	break;
1430
1431	case SPACEWIRE_IOCTRL_LINKDISABLE:
1432	pDev->config.linkdisabled = 1;
1433	pDev->config.linkstart = 0;
1434	if ( pDev->core_ver != 3 ) {
1435	SPW_CTRL_WRITE(pDev, (SPW_CTRL_READ(pDev) & 0xFFFFFFFC) \| 1);
1436	if ((SPW_CTRL_READ(pDev) & 3) != 1) {
1437	return RTEMS_IO_ERROR;
1438	}
1439	}
1440	break;
1441
1442	case SPACEWIRE_IOCTRL_LINKSTART:
1443	pDev->config.linkdisabled = 0;
1444	pDev->config.linkstart = 1;
1445	if ( pDev->core_ver != 3 ) {
1446	SPW_CTRL_WRITE(pDev, (SPW_CTRL_READ(pDev) & 0xFFFFFFFC) \| 2);
1447	if ((SPW_CTRL_READ(pDev) & 3) != 2) {
1448	return RTEMS_IO_ERROR;
1449	}
1450	}
1451	break;
1452
1453	/* Calculate timer register from GRSPW Core frequency
1454	* Also possible to set disconnect and timer64 from
1455	* - SPACEWIRE_IOCTRL_SET_DISCONNECT
1456	* - SPACEWIRE_IOCTRL_SET_TIMER
1457	*/
1458	case SPACEWIRE_IOCTRL_SET_COREFREQ:
1459	pDev->core_freq_khz = (unsigned int)ioarg->buffer;
1460	if ( pDev->core_freq_khz == 0 ){
1461	/* Get GRSPW clock frequency from system clock.
1462	* System clock has been read from timer inited
1463	* by RTEMS loader (mkprom)
1464	*/
1465	drvmgr_freq_get(pDev->dev, DEV_APB_SLV,
1466	&pDev->core_freq_khz);
1467	/* Convert from Hz -> kHz */
1468	pDev->core_freq_khz = pDev->core_freq_khz / 1000;
1469	}
1470
1471	/* Only GRSPW1 needs the Timer64 and Disconnect values
1472	* GRSPW2 and onwards doesn't have this register.
1473	*/
1474	if ( pDev->core_ver <= 1 ){
1475	/* Calculate Timer64 & Disconnect */
1476	pDev->config.timer = grspw_calc_timer64(pDev->core_freq_khz);
1477	pDev->config.disconnect = grspw_calc_disconnect(pDev->core_freq_khz);
1478
1479	/* Set Timer64 & Disconnect Register */
1480	SPW_WRITE(&pDev->regs->timer,
1481	(SPW_READ(&pDev->regs->timer) & 0xFFC00000) \|
1482	((pDev->config.disconnect & 0x3FF)<<12) \|
1483	(pDev->config.timer & 0xFFF));
1484
1485	/* Check that the registers were written successfully */
1486	tmp = SPW_READ(&pDev->regs->timer) & 0x003fffff;
1487	if ( ((tmp & 0xFFF) != pDev->config.timer) \|\|
1488	(((tmp >> 12) & 0x3FF) != pDev->config.disconnect) ) {
1489	return RTEMS_IO_ERROR;
1490	}
1491	}
1492	break;
1493
1494	case SPACEWIRE_IOCTRL_START:
1495	if ( pDev->running ){
1496	return RTEMS_INVALID_NAME;
1497	}
1498
1499	/* Get timeout from userspace
1500	* timeout:
1501	* € -1 = Default timeout
1502	* € less than -1 = forever
1503	* € 0 = no wait, proceed if link is up
1504	* € positive = specifies number of system clock ticks that
1505	* startup will wait for link to enter ready mode.
1506	*/
1507	timeout = (int)ioarg->buffer;
1508
1509	if ( (ret=grspw_hw_startup(pDev,timeout)) != RTEMS_SUCCESSFUL ) {
1510	return ret;
1511	}
1512	pDev->running = 1;
1513	/* Register interrupt routine and unmask IRQ */
1514	drvmgr_interrupt_register(pDev->dev, 0, "grspw", grspw_interrupt, pDev);
1515
1516	break;
1517
1518	case SPACEWIRE_IOCTRL_STOP:
1519	if ( !pDev->running ){
1520	return RTEMS_INVALID_NAME;
1521	}
1522	/* Disable interrupts */
1523	drvmgr_interrupt_unregister(dev, 0, grspw_interrupt, pDev);
1524
1525	pDev->running = 0;
1526
1527	/* Stop Receiver and transmitter */
1528	grspw_hw_stop(pDev,1,1);
1529	break;
1530
1531	/* Set time-code control register bits, and Enables/Disables
1532	* Time code interrupt, make sure to connect the callback
1533	* grspw_timecode_callback if using interrupts.
1534	*/
1535	case SPACEWIRE_IOCTRL_SET_TCODE_CTRL:
1536	tmp = (unsigned int)ioarg->buffer;
1537	mask = tmp & (SPACEWIRE_TCODE_CTRL_IE_MSK\|SPACEWIRE_TCODE_CTRL_TT_MSK\|SPACEWIRE_TCODE_CTRL_TR_MSK);
1538	mask <<= 8;
1539	tmp &= mask;
1540	tmp = (SPW_CTRL_READ(pDev) & ~(mask \| SPW_CTRL_IE)) \| tmp;
1541	if (tmp & (SPW_CTRL_LI\|SPW_CTRL_TQ))
1542	tmp \|= SPW_CTRL_IE;
1543	SPW_CTRL_WRITE(pDev, tmp);
1544	break;
1545
1546	/* Set time register and optionaly send a time code */
1547	case SPACEWIRE_IOCTRL_SET_TCODE:
1548	tmp = (unsigned int)ioarg->buffer;
1549	/* Set timecode register */
1550	if (tmp & SPACEWIRE_TCODE_SET) {
1551	SPW_WRITE(&pDev->regs->time,
1552	((SPW_READ(&pDev->regs->time) & ~(0xff)) \|
1553	(tmp & SPACEWIRE_TCODE_TCODE)));
1554	}
1555	/* Send timecode directly (tick-in) ? */
1556	if (tmp & SPACEWIRE_TCODE_TX) {
1557	SPW_CTRL_WRITE(pDev,
1558	((SPW_CTRL_READ(pDev) & ~(SPW_CTRL_TI)) \| SPW_CTRL_TI));
1559	}
1560	break;
1561
1562	/* Read time code register and tick-out status bit */
1563	case SPACEWIRE_IOCTRL_GET_TCODE:
1564	tmp = (unsigned int)ioarg->buffer;
1565	if ( !tmp ){
1566	return RTEMS_INVALID_NAME;
1567	}
1568
1569	/* Copy timecode register */
1570	if (SPW_READ(&pDev->regs->status) & SPW_STATUS_TO) {
1571	(unsigned int )tmp = (1 << 8) \| SPW_READ(&pDev->regs->time);
1572	} else {
1573	(unsigned int )tmp = SPW_READ(&pDev->regs->time);
1574	}
1575	break;
1576
1577	case SPACEWIRE_IOCTRL_SET_READ_TIMEOUT:
1578	pDev->config.rtimeout = (unsigned int)ioarg->buffer;
1579	break;
1580
1581	default:
1582	return RTEMS_NOT_IMPLEMENTED;
1583	}
1584
1585	SPACEWIRE_DBGC(DBGSPW_IOCALLS, "SPW_IOCTRL Return\n");
1586	return RTEMS_SUCCESSFUL;
1587	}
1588
1589	/* ============================================================================== */
1590
1591	static int grspw_set_rxmaxlen(GRSPW_DEV *pDev) {
1592	unsigned int rxmax;
1593	SPW_WRITE(&pDev->regs->dma0rxmax,pDev->config.rxmaxlen); /set rx maxlength/
1594	rxmax = SPW_READ(&pDev->regs->dma0rxmax);
1595	if (rxmax != pDev->config.rxmaxlen) {
1596	return 0;
1597	}
1598	return 1;
1599	}
1600
1601	static int grspw_hw_init(GRSPW_DEV *pDev) {
1602	unsigned int ctrl;
1603
1604	ctrl = SPW_CTRL_READ(pDev);
1605
1606	pDev->rx = (SPACEWIRE_RXBD *) pDev->ptr_bd0;
1607	pDev->tx = (SPACEWIRE_TXBD *) (pDev->ptr_bd0 + SPACEWIRE_BDTABLE_SIZE);
1608
1609	/* Set up remote addresses */
1610	pDev->rx_remote = (unsigned int)pDev->ptr_bd0_remote;
1611	pDev->tx_remote = pDev->rx_remote + SPACEWIRE_BDTABLE_SIZE;
1612
1613	SPACEWIRE_DBG("hw_init [minor %i]\n", pDev->minor);
1614
1615	pDev->config.is_rmap = ctrl & SPW_CTRL_RA;
1616	pDev->config.is_rxunaligned = ctrl & SPW_CTRL_RX;
1617	pDev->config.is_rmapcrc = ctrl & SPW_CTRL_RC;
1618	return 0;
1619	}
1620
1621	static int grspw_hw_waitlink (GRSPW_DEV *pDev, int timeout)
1622	{
1623	int j;
1624
1625	/* No actual link interface on a DMA-only GRSPW2 connected to the
1626	* SPW router
1627	*/
1628	if (pDev->core_ver == 3)
1629	return 0;
1630
1631	if ( timeout == -1 ){
1632	/* Wait default timeout */
1633	timeout = SPACEWIRE_INIT_TIMEOUT;
1634	}
1635
1636	j=0;
1637	while (SPW_LINKSTATE(SPW_STATUS_READ(pDev)) != 5) {
1638	if ( timeout < -1 ) {
1639	/* wait forever */
1640	}else if ( j >= timeout ){
1641	/* timeout reached, return fail */
1642	return 1;
1643	}
1644
1645	/* Sleep for 10 ticks */
1646	rtems_task_wake_after(10);
1647	j+=10;
1648	}
1649	return 0;
1650	}
1651
1652	static void grspw_hw_reset(GRSPW_DEV *pDev)
1653	{
1654	SPW_CTRL_WRITE(pDev, SPW_CTRL_RESET); /reset core/
1655	SPW_STATUS_WRITE(pDev, SPW_STATUS_TO \| SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \|
1656	SPW_STATUS_WE \| SPW_STATUS_IA \| SPW_STATUS_EE); /clear status/
1657
1658	/* Add extra writes to make sure we wait the number of clocks required
1659	* after reset
1660	*/
1661	SPW_STATUS_WRITE(pDev, SPW_STATUS_TO \| SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \|
1662	SPW_STATUS_WE \| SPW_STATUS_IA \| SPW_STATUS_EE); /clear status/
1663	SPW_STATUS_WRITE(pDev, SPW_STATUS_TO \| SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \|
1664	SPW_STATUS_WE \| SPW_STATUS_IA \| SPW_STATUS_EE); /clear status/
1665	SPW_STATUS_WRITE(pDev, SPW_STATUS_TO \| SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \|
1666	SPW_STATUS_WE \| SPW_STATUS_IA \| SPW_STATUS_EE); /clear status/
1667	SPW_STATUS_WRITE(pDev, SPW_STATUS_TO \| SPW_STATUS_CE \| SPW_STATUS_ER \| SPW_STATUS_DE \| SPW_STATUS_PE \|
1668	SPW_STATUS_WE \| SPW_STATUS_IA \| SPW_STATUS_EE); /clear status/
1669
1670	SPW_CTRL_WRITE(pDev, SPW_CTRL_LINKSTART); /start link core/
1671	}
1672
1673	static void grspw_hw_read_config(GRSPW_DEV *pDev)
1674	{
1675	unsigned int tmp;
1676
1677	tmp = SPW_READ(&pDev->regs->nodeaddr);
1678	pDev->config.nodeaddr = 0xFF & tmp;
1679	pDev->config.nodemask = 0xFF & (tmp>>8);
1680	pDev->config.destkey = 0xFF & SPW_READ(&pDev->regs->destkey);
1681	pDev->config.clkdiv = 0xFFFF & SPW_READ(&pDev->regs->clkdiv);
1682
1683	tmp = SPW_CTRL_READ(pDev);
1684	pDev->config.promiscuous = 1 & (tmp >> 5);
1685	pDev->config.rmapen = 1 & (tmp >> 16);
1686	pDev->config.rmapbufdis = 1 & (tmp >> 17);
1687	pDev->config.is_rmap = 1 & (tmp >> 31);
1688	pDev->config.is_rxunaligned = 1 & (tmp >> 30);
1689	pDev->config.is_rmapcrc = 1 & (tmp >> 29);
1690	pDev->config.linkdisabled = 1 & tmp;
1691	pDev->config.linkstart = 1 & (tmp >> 1);
1692
1693	if ( pDev->core_ver <= 1 ){
1694	tmp = SPW_READ(&pDev->regs->timer);
1695	pDev->config.timer = 0xFFF & tmp;
1696	pDev->config.disconnect = 0x3FF & (tmp >> 12);
1697	}else{
1698	pDev->config.timer = 0;
1699	pDev->config.disconnect = 0;
1700	}
1701
1702	return;
1703	}
1704
1705	/* timeout is given in ticks */
1706	static int grspw_hw_startup (GRSPW_DEV *pDev, int timeout)
1707	{
1708	int i;
1709	unsigned int dmactrl;
1710
1711	SPW_WRITE(&pDev->regs->status, (SPW_STATUS_TO\|SPW_STATUS_CE\|SPW_STATUS_ER\|SPW_STATUS_DE\|SPW_STATUS_PE\|SPW_STATUS_WE\|SPW_STATUS_IA\|SPW_STATUS_EE)); /clear status/
1712
1713	if (grspw_hw_waitlink(pDev,timeout)) {
1714	SPACEWIRE_DBG2("Device open. Link is not up\n");
1715	return RTEMS_TIMEOUT;
1716	}
1717
1718	SPW_WRITE(&pDev->regs->dma0ctrl, SPW_DMACTRL_PS \| SPW_DMACTRL_PR \| SPW_DMACTRL_TA \| SPW_DMACTRL_RA); /clear status, set ctrl/
1719
1720	if ((dmactrl = SPW_READ(&pDev->regs->dma0ctrl)) != 0) {
1721	SPACEWIRE_DBG2("DMACtrl is not cleared\n");
1722	return RTEMS_IO_ERROR;
1723	}
1724
1725	/* prepare transmit buffers */
1726	for (i = 0; i < pDev->txbufcnt; i++) {
1727	pDev->tx[i].ctrl = 0;
1728	pDev->tx[i].addr_header = ((unsigned int)&pDev->ptr_txhbuf0_remote[0]) + (i * pDev->txhbufsize);
1729	pDev->tx[i].addr_data = ((unsigned int)&pDev->ptr_txdbuf0_remote[0]) + (i * pDev->txdbufsize);
1730	}
1731	pDev->tx_cur = 0;
1732	pDev->tx_sent = 0;
1733	pDev->tx_all_in_use = 0;
1734
1735	/* prepare receive buffers */
1736	for (i = 0; i < pDev->rxbufcnt; i++) {
1737	if (i+1 == pDev->rxbufcnt) {
1738	pDev->rx[i].ctrl = SPW_RXBD_IE \| SPW_RXBD_EN \| SPW_RXBD_WR;
1739	} else {
1740	pDev->rx[i].ctrl = SPW_RXBD_IE \| SPW_RXBD_EN;
1741	}
1742	pDev->rx[i].addr = ((unsigned int)&pDev->ptr_rxbuf0_remote[0]) + (i * pDev->rxbufsize);
1743	}
1744	pDev->rxcur = 0;
1745	pDev->rxbufcur = -1;
1746	grspw_set_rxmaxlen(pDev);
1747
1748	SPW_WRITE(&pDev->regs->dma0txdesc, pDev->tx_remote);
1749	SPW_WRITE(&pDev->regs->dma0rxdesc, pDev->rx_remote);
1750
1751	/* start RX */
1752	dmactrl = SPW_READ(&pDev->regs->dma0ctrl);
1753	SPW_WRITE(&pDev->regs->dma0ctrl, (dmactrl & SPW_PREPAREMASK_RX) \| SPW_DMACTRL_RD \| SPW_DMACTRL_RXEN \| SPW_DMACTRL_NS \| SPW_DMACTRL_TXIE \| SPW_DMACTRL_RXIE);
1754
1755	SPACEWIRE_DBGC(DBGSPW_TX,"0x%x: setup complete\n", (unsigned int)pDev->regs);
1756	return RTEMS_SUCCESSFUL;
1757	}
1758
1759	/* Wait until the receiver is inactive */
1760	static void grspw_hw_wait_rx_inactive(GRSPW_DEV *pDev)
1761	{
1762	while( SPW_READ(&pDev->regs->dma0ctrl) & SPW_DMACTRL_RX ){
1763	/* switching may be needed:
1764	* - low frequency GRSPW
1765	* - mega packet incoming
1766	*/
1767	rtems_task_wake_after(1);
1768	}
1769	}
1770
1771	/* Stop the rx or/and tx by disabling the receiver/transmitter */
1772	static int grspw_hw_stop (GRSPW_DEV *pDev, int rx, int tx)
1773	{
1774	unsigned int dmactrl;
1775
1776	/* stop rx and/or tx */
1777	dmactrl = SPW_READ(&pDev->regs->dma0ctrl);
1778	if ( rx ) {
1779	dmactrl &= ~(SPW_DMACTRL_RXEN\|SPW_DMACTRL_RXIE\|SPW_DMACTRL_RD);
1780	}
1781	if ( tx ) {
1782	dmactrl &= ~(SPW_DMACTRL_TXEN\|SPW_DMACTRL_TXIE);
1783	}
1784	/SPW_WRITE(&pDev->regs->dma0ctrl, (dmactrl & SPW_PREPAREMASK_RX) & ~(SPW_DMACTRL_RD \| SPW_DMACTRL_RXEN) & ~(SPW_DMACTRL_TXEN));/
1785
1786	/* don't clear status flags */
1787	dmactrl &= ~(SPW_DMACTRL_RA\|SPW_DMACTRL_PR\|SPW_DMACTRL_AI);
1788	SPW_WRITE(&pDev->regs->dma0ctrl, dmactrl);
1789	return RTEMS_SUCCESSFUL;
1790	}
1791
1792
1793
1794	int grspw_hw_send(GRSPW_DEV pDev, unsigned int hlen, char hdr, unsigned int dlen, char *data, unsigned int options)
1795	{
1796	unsigned int dmactrl, ctrl;
1797	#ifdef DEBUG_SPACEWIRE_ONOFF
1798	unsigned int k;
1799	#endif
1800	rtems_interrupt_level level;
1801	unsigned int cur = pDev->tx_cur, bdctrl;
1802	char txh = pDev->ptr_txhbuf0 + (cur pDev->txhbufsize);
1803	char txd = pDev->ptr_txdbuf0 + (cur pDev->txdbufsize);
1804	char txh_remote = pDev->ptr_txhbuf0_remote + (cur pDev->txhbufsize);
1805	char txd_remote = pDev->ptr_txdbuf0_remote + (cur pDev->txdbufsize);
1806
1807	ctrl = SPW_READ((volatile void *)&pDev->tx[cur].ctrl);
1808
1809	if (ctrl & SPW_TXBD_EN) {
1810	return 0;
1811	}
1812
1813	memcpy(&txd[0], data, dlen);
1814	memcpy(&txh[0], hdr, hlen);
1815
1816	#ifdef DEBUG_SPACEWIRE_ONOFF
1817	if (DEBUG_SPACEWIRE_FLAGS & DBGSPW_DUMP) {
1818	for (k = 0; k < hlen; k++){
1819	if (k % 16 == 0) {
1820	printf ("\n");
1821	}
1822	printf ("%.2x(%c) ",txh[k] & 0xff,isprint(txh[k] & 0xff) ? txh[k] & 0xff : ' ');
1823	}
1824	printf ("\n");
1825	}
1826	if (DEBUG_SPACEWIRE_FLAGS & DBGSPW_DUMP) {
1827	for (k = 0; k < dlen; k++){
1828	if (k % 16 == 0) {
1829	printf ("\n");
1830	}
1831	printf ("%.2x(%c) ",txd[k] & 0xff,isprint(txd[k] & 0xff) ? txd[k] & 0xff : ' ');
1832	}
1833	printf ("\n");
1834	}
1835	#endif
1836
1837	pDev->tx[cur].addr_header = (unsigned int)txh_remote;
1838	pDev->tx[cur].len = dlen;
1839	pDev->tx[cur].addr_data = (unsigned int)txd_remote;
1840
1841	bdctrl = SPW_TXBD_IE \| SPW_TXBD_EN \| hlen;
1842	if ( options & GRSPW_PKTSEND_OPTION_HDR_CRC )
1843	bdctrl \|= SPW_TXBD_HC;
1844	if ( options & GRSPW_PKTSEND_OPTION_DATA_CRC )
1845	bdctrl \|= SPW_TXBD_DC;
1846	bdctrl \|= options & GRSPW_PKTSEND_OPTION_NOCRCLEN_MASK;
1847
1848	/* Update counters */
1849	rtems_interrupt_disable(level);
1850	if (pDev->tx_cur == (pDev->txbufcnt - 1) ) {
1851	bdctrl \|= SPW_TXBD_WR;
1852	}
1853	pDev->tx[cur].ctrl = bdctrl;
1854
1855	dmactrl = SPW_READ(&pDev->regs->dma0ctrl);
1856	SPW_WRITE(&pDev->regs->dma0ctrl, (dmactrl & SPW_PREPAREMASK_TX) \| SPW_DMACTRL_TXEN \| SPW_DMACTRL_TXIE);
1857
1858	pDev->tx_cur = (pDev->tx_cur + 1) % pDev->txbufcnt;
1859	if (pDev->tx_cur == pDev->tx_sent) {
1860	pDev->tx_all_in_use = 1;
1861	}
1862	rtems_interrupt_enable(level);
1863
1864	/* In blocking mode wait until message is sent */
1865	if (pDev->config.tx_blocking) {
1866	while ( SPW_READ(&pDev->regs->dma0ctrl) & SPW_DMACTRL_TXEN) {
1867	/* if changed to blocking mode */
1868	SPACEWIRE_DBGC(DBGSPW_TX, "Tx blocking\n");
1869	rtems_semaphore_obtain(pDev->txsp, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
1870	}
1871	}
1872	SPACEWIRE_DBGC(DBGSPW_TX, "0x%x: transmitted <%i> bytes\n", (unsigned int) pDev->regs, dlen+hlen);
1873	return hlen + dlen;
1874	}
1875
1876	static int grspw_hw_receive(GRSPW_DEV pDev, char b, int c) {
1877	unsigned int len, rxlen, ctrl;
1878	unsigned int cur;
1879	unsigned int tmp;
1880	unsigned int dump_start_len;
1881	int i;
1882	char *rxb;
1883
1884	if ( pDev->config.promiscuous \|\| pDev->config.keep_source ) {
1885	dump_start_len = 0; /* make sure address and prot can be read in promiscuous mode */
1886	} else if (pDev->config.rm_prot_id) {
1887	dump_start_len = 2; /* skip source address and protocol id */
1888	} else {
1889	dump_start_len = 1; /* default: skip only source address */
1890	}
1891
1892	rxlen = 0;
1893	cur = pDev->rxcur;
1894	rxb = pDev->ptr_rxbuf0 + (cur * pDev->rxbufsize);
1895
1896	SPACEWIRE_DBGC(DBGSPW_RX, "0x%x: waitin packet at pos %i\n", (unsigned int) pDev->regs, cur);
1897
1898	ctrl = SPW_READ((volatile void *)&pDev->rx[cur].ctrl);
1899	if (ctrl & SPW_RXBD_EN) {
1900	return rxlen;
1901	}
1902	SPACEWIRE_DBGC(DBGSPW_RX, "checking packet\n");
1903
1904	len = SPW_RXBD_LENGTH & ctrl;
1905	if (!((ctrl & SPW_RXBD_ERROR) \|\| (pDev->config.check_rmap_err && (ctrl & SPW_RXBD_RMAPERROR)))) {
1906	if (pDev->rxbufcur == -1) {
1907	SPACEWIRE_DBGC(DBGSPW_RX, "incoming packet len %i\n", len);
1908	pDev->stat.packets_received++;
1909	pDev->rxbufcur = dump_start_len;
1910	}
1911	rxlen = tmp = len - pDev->rxbufcur;
1912	SPACEWIRE_DBGC(DBGSPW_RX, "C %i\n", c);
1913	SPACEWIRE_DBGC(DBGSPW_RX, "Dump %i\n", dump_start_len);
1914	SPACEWIRE_DBGC(DBGSPW_RX, "Bufcur %i\n", pDev->rxbufcur);
1915	SPACEWIRE_DBGC(DBGSPW_RX, "Rxlen %i\n", rxlen );
1916	if (rxlen > c) {
1917	rxlen = c;
1918	}
1919	if (CPU_SPARC_HAS_SNOOPING) {
1920	/* if ( 1 ) {*/
1921	/printf("RX_MEMCPY(0x%x, 0x%x, 0x%x)\n", (unsigned int)b, (unsigned int)(rxb+pDev->rxbufcur), (unsigned int)rxlen);/
1922	memcpy(b, rxb+pDev->rxbufcur, rxlen);
1923	} else {
1924	int left = rxlen;
1925	/* Copy word wise if Aligned */
1926	if ( (((int)b & 3) == 0) && (((int)(rxb+pDev->rxbufcur) & 3) == 0) ){
1927	while(left>=32){
1928	(int )(b+0) = MEM_READ32(rxb+pDev->rxbufcur+0);
1929	(int )(b+4) = MEM_READ32(rxb+pDev->rxbufcur+4);
1930	(int )(b+8) = MEM_READ32(rxb+pDev->rxbufcur+8);
1931	(int )(b+12) = MEM_READ32(rxb+pDev->rxbufcur+12);
1932	(int )(b+16) = MEM_READ32(rxb+pDev->rxbufcur+16);
1933	(int )(b+20) = MEM_READ32(rxb+pDev->rxbufcur+20);
1934	(int )(b+24) = MEM_READ32(rxb+pDev->rxbufcur+24);
1935	(int )(b+28) = MEM_READ32(rxb+pDev->rxbufcur+28);
1936	rxb+=32;
1937	b+=32;
1938	left-=32;
1939	}
1940	while(left>=4){
1941	(int )b = MEM_READ32(rxb+pDev->rxbufcur);
1942	rxb+=4;
1943	b+=4;
1944	left-=4;
1945	}
1946	}
1947	for(i = 0; i < left; i++) {
1948	b[i] = MEM_READ8(rxb+pDev->rxbufcur+i);
1949	}
1950	}
1951
1952	pDev->rxbufcur += rxlen;
1953	if (c >= tmp) {
1954	SPACEWIRE_DBGC(DBGSPW_RX, "Next descriptor\n");
1955	grspw_rxnext(pDev);
1956	}
1957	} else {
1958	check_rx_errors(pDev, ctrl);
1959	grspw_rxnext(pDev);
1960	}
1961	return rxlen;
1962	}
1963
1964	static void grspw_rxnext(GRSPW_DEV *pDev)
1965	{
1966	unsigned int dmactrl;
1967	unsigned int cur = pDev->rxcur;
1968	unsigned int ctrl = 0;
1969	rtems_interrupt_level level;
1970
1971	rtems_interrupt_disable(level);
1972
1973	if (cur == (pDev->rxbufcnt - 1)) {
1974	pDev->rx[cur].ctrl = ctrl \| SPW_RXBD_EN \| SPW_RXBD_IE \| SPW_RXBD_WR;
1975	cur = 0;
1976	} else {
1977	pDev->rx[cur].ctrl = ctrl \| SPW_RXBD_EN \| SPW_RXBD_IE;
1978	cur++;
1979	}
1980
1981	pDev->rxcur = cur;
1982	pDev->rxbufcur = -1;
1983
1984	/* start RX */
1985	dmactrl = SPW_READ(&pDev->regs->dma0ctrl);
1986	SPW_WRITE(&pDev->regs->dma0ctrl, (dmactrl & SPW_PREPAREMASK_RX) \| SPW_DMACTRL_RD \| SPW_DMACTRL_RXEN \| SPW_DMACTRL_RXIE \| SPW_DMACTRL_NS);
1987
1988	rtems_interrupt_enable(level);
1989	}
1990
1991	static void check_rx_errors(GRSPW_DEV *pDev, int ctrl)
1992	{
1993	if (ctrl & SPW_RXBD_EEP) {
1994	pDev->stat.rx_eep_err++;
1995	}
1996	if (ctrl & SPW_RXBD_EHC) {
1997	if (pDev->config.check_rmap_err) {
1998	pDev->stat.rx_rmap_header_crc_err++;
1999	}
2000	}
2001	if (ctrl & SPW_RXBD_EDC) {
2002	if (pDev->config.check_rmap_err) {
2003	pDev->stat.rx_rmap_data_crc_err++;
2004	}
2005	}
2006	if (ctrl & SPW_RXBD_ETR) {
2007	pDev->stat.rx_truncated++;
2008	}
2009	}
2010
2011
2012	static void grspw_print_dev(struct drvmgr_dev *dev, int options)
2013	{
2014	GRSPW_DEV *pDev = dev->priv;
2015
2016	/* Print */
2017	printf("--- GRSPW %s ---\n", pDev->devName);
2018	printf(" REGS: 0x%x\n", (unsigned int)pDev->regs);
2019	printf(" IRQ: %d\n", pDev->irq);
2020	printf(" CORE VERSION: %d\n", pDev->core_ver);
2021	printf(" CTRL: 0x%x\n", pDev->regs->ctrl);
2022	printf(" STATUS: 0x%x\n", pDev->regs->status);
2023	printf(" DMA0CTRL: 0x%x\n", pDev->regs->dma0ctrl);
2024	printf(" TXBD: 0x%x\n", (unsigned int)pDev->tx);
2025	printf(" RXBD: 0x%x\n", (unsigned int)pDev->rx);
2026	}
2027
2028	void grspw_print(int options)
2029	{
2030	struct amba_drv_info *drv = &grspw_drv_info;
2031	struct drvmgr_dev *dev;
2032
2033	dev = drv->general.dev;
2034	while(dev) {
2035	grspw_print_dev(dev, options);
2036	dev = dev->next_in_drv;
2037	}
2038	}

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