Context Navigation

source: rtems/bsps/sparc/shared/pci/grpci2.c @ 56a7540

5

Last change on this file since 56a7540 was 56a7540, checked in by Daniel Hellstrom <daniel@…>, on 01/23/18 at 09:12:36
leon: substitute printf with printk in driver init
Property mode set to `100644`
File size: 26.6 KB

Line
1	/* GRLIB GRPCI2 PCI HOST driver.
2	*
3	* COPYRIGHT (c) 2011
4	* Cobham Gaisler AB.
5	*
6	* The license and distribution terms for this file may be
7	* found in found in the file LICENSE in this distribution or at
8	* http://www.rtems.org/license/LICENSE.
9	*/
10
11	/* Configures the GRPCI2 core and initialize,
12	* - the PCI Library (pci.c)
13	* - the general part of the PCI Bus driver (pci_bus.c)
14	*
15	* System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16	* default taken from Plug and Play, but may be overridden by the
17	* driver resources INTA#..INTD#. GRPCI2 handles differently depending
18	* on the design (4 different ways).
19	*
20	* GRPCI2 IRQ implementation notes
21	* -------------------------------
22	* Since the Driver Manager pci_bus layer implements IRQ by calling
23	* pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24	* root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25	* driver to use the drvmgr_interrupt_* routines since they will be
26	* accessing the same routines in the end. Otherwise the GRPCI2 driver must
27	* have used the pci_interrupt_* routines.
28	*/
29
30	#include <stdlib.h>
31	#include <stdio.h>
32	#include <string.h>
33	#include <rtems.h>
34	#include <rtems/bspIo.h>
35	#include <libcpu/byteorder.h>
36	#include <libcpu/access.h>
37	#include <pci.h>
38	#include <pci/cfg.h>
39
40	#include <drvmgr/drvmgr.h>
41	#include <drvmgr/ambapp_bus.h>
42	#include <ambapp.h>
43	#include <drvmgr/pci_bus.h>
44	#include <bsp/grpci2.h>
45
46	/* Use interrupt lock privmitives compatible with SMP defined in
47	* RTEMS 4.11.99 and higher.
48	*/
49	#if (((__RTEMS_MAJOR__ << 16) \| (__RTEMS_MINOR__ << 8) \| __RTEMS_REVISION__) >= 0x040b63)
50
51	/* map via rtems_interrupt_lock_* API: */
52	#define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock)
53	#define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name)
54	#define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level)
55	#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level)
56	#define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level)
57	#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level)
58	#define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k
59	#define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k)
60
61	#else
62
63	/* maintain single-core compatibility with older versions of RTEMS: */
64	#define SPIN_DECLARE(name)
65	#define SPIN_INIT(lock, name)
66	#define SPIN_LOCK(lock, level)
67	#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_disable(level)
68	#define SPIN_UNLOCK(lock, level)
69	#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_enable(level)
70	#define SPIN_IRQFLAGS(k) rtems_interrupt_level k
71	#define SPIN_ISR_IRQFLAGS(k)
72
73	#ifdef RTEMS_SMP
74	#error SMP mode not compatible with these interrupt lock primitives
75	#endif
76	#endif
77
78	/* If defined to 1 - byte twisting is enabled by default */
79	#define DEFAULT_BT_ENABLED 0
80
81	/* If defined to 64 - Latency timer is 64 by default */
82	#define DEFAULT_LATENCY_TIMER 64
83
84	/* Interrupt assignment. Set to other value than 0xff in order to
85	* override defaults and plug&play information
86	*/
87	#ifndef GRPCI2_INTA_SYSIRQ
88	#define GRPCI2_INTA_SYSIRQ 0xff
89	#endif
90	#ifndef GRPCI2_INTB_SYSIRQ
91	#define GRPCI2_INTB_SYSIRQ 0xff
92	#endif
93	#ifndef GRPCI2_INTC_SYSIRQ
94	#define GRPCI2_INTC_SYSIRQ 0xff
95	#endif
96	#ifndef GRPCI2_INTD_SYSIRQ
97	#define GRPCI2_INTD_SYSIRQ 0xff
98	#endif
99
100	/#define DEBUG 1/
101
102	#ifdef DEBUG
103	#define DBG(x...) printk(x)
104	#else
105	#define DBG(x...)
106	#endif
107
108	/*
109	* GRPCI2 APB Register MAP
110	*/
111	struct grpci2_regs {
112	volatile unsigned int ctrl; /* 0x00 */
113	volatile unsigned int sts_cap; /* 0x04 */
114	volatile unsigned int ppref; /* 0x08 */
115	volatile unsigned int io_map; /* 0x0C */
116	volatile unsigned int dma_ctrl; /* 0x10 */
117	volatile unsigned int dma_bdbase; /* 0x14 */
118	volatile unsigned int dma_chact; /* 0x18 */
119	int res1; /* 0x1C */
120	volatile unsigned int bars[6]; /* 0x20 */
121	int res2[2]; /* 0x38 */
122	volatile unsigned int ahbmst_map[16]; /* 0x40 */
123	};
124
125	#define CTRL_BUS_BIT 16
126
127	#define CTRL_SI (1<<27)
128	#define CTRL_PE (1<<26)
129	#define CTRL_ER (1<<25)
130	#define CTRL_EI (1<<24)
131	#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
132	#define CTRL_HOSTINT 0xf
133
134	#define STS_HOST_BIT 31
135	#define STS_MST_BIT 30
136	#define STS_TAR_BIT 29
137	#define STS_DMA_BIT 28
138	#define STS_DI_BIT 27
139	#define STS_HI_BIT 26
140	#define STS_IRQMODE_BIT 24
141	#define STS_TRACE_BIT 23
142	#define STS_CFGERRVALID_BIT 20
143	#define STS_CFGERR_BIT 19
144	#define STS_INTTYPE_BIT 12
145	#define STS_INTSTS_BIT 8
146	#define STS_FDEPTH_BIT 2
147	#define STS_FNUM_BIT 0
148
149	#define STS_HOST (1<<STS_HOST_BIT)
150	#define STS_MST (1<<STS_MST_BIT)
151	#define STS_TAR (1<<STS_TAR_BIT)
152	#define STS_DMA (1<<STS_DMA_BIT)
153	#define STS_DI (1<<STS_DI_BIT)
154	#define STS_HI (1<<STS_HI_BIT)
155	#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
156	#define STS_TRACE (1<<STS_TRACE_BIT)
157	#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
158	#define STS_CFGERR (1<<STS_CFGERR_BIT)
159	#define STS_INTTYPE (0x7f<<STS_INTTYPE_BIT)
160	#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
161	#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
162	#define STS_FNUM (0x3<<STS_FNUM_BIT)
163
164	#define STS_ITIMEOUT (1<<18)
165	#define STS_ISYSERR (1<<17)
166	#define STS_IDMA (1<<16)
167	#define STS_IDMAERR (1<<15)
168	#define STS_IMSTABRT (1<<14)
169	#define STS_ITGTABRT (1<<13)
170	#define STS_IPARERR (1<<12)
171
172	/* GRPCI2 Capability */
173	struct grpci2_cap_first {
174	unsigned int ctrl;
175	unsigned int pci2ahb_map[6];
176	unsigned int ext2ahb_map;
177	unsigned int io_map;
178	unsigned int pcibar_size[6];
179	unsigned int ahb_pref;
180	};
181	#define CAP9_CTRL_OFS 0
182	#define CAP9_BAR_OFS 0x4
183	#define CAP9_IOMAP_OFS 0x20
184	#define CAP9_BARSIZE_OFS 0x24
185	#define CAP9_AHBPREF_OFS 0x3C
186
187	/* Used internally for accessing the PCI bridge's configuration space itself */
188	#define HOST_TGT PCI_DEV(0xff, 0, 0)
189
190	struct grpci2_priv *grpci2priv = NULL;
191
192	/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
193	* to a system interrupt number.
194	*/
195	unsigned char grpci2_pci_irq_table[4] =
196	{
197	/* INTA# */ GRPCI2_INTA_SYSIRQ,
198	/* INTB# */ GRPCI2_INTB_SYSIRQ,
199	/* INTC# */ GRPCI2_INTC_SYSIRQ,
200	/* INTD# */ GRPCI2_INTD_SYSIRQ
201	};
202
203	/* Start of workspace/dynamical area */
204	extern unsigned int _end;
205	#define DMA_START ((unsigned int) &_end)
206
207	/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
208	struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
209	/* BAR0 */ {DMA_START, DMA_START, 0x10000000},
210	/* BAR1 */ {0, 0, 0},
211	/* BAR2 */ {0, 0, 0},
212	/* BAR3 */ {0, 0, 0},
213	/* BAR4 */ {0, 0, 0},
214	/* BAR5 */ {0, 0, 0},
215	};
216
217	/* Driver private data struture */
218	struct grpci2_priv {
219	struct drvmgr_dev *dev;
220	struct grpci2_regs *regs;
221	unsigned char ver;
222	char irq;
223	char irq_mode; /* IRQ Mode from CAPSTS REG */
224	char irq_dma; /* IRQ Index for DMA */
225	char bt_enabled;
226	unsigned int irq_mask;
227	unsigned int latency_timer;
228
229	struct grpci2_pcibar_cfg *barcfg;
230
231	unsigned int pci_area;
232	unsigned int pci_area_end;
233	unsigned int pci_io;
234	unsigned int pci_conf;
235	unsigned int pci_conf_end;
236
237	uint32_t devVend; /* Host PCI Device/Vendor ID */
238
239	struct drvmgr_map_entry maps_up[7];
240	struct drvmgr_map_entry maps_down[2];
241	struct pcibus_config config;
242
243	/* DMA interrupts */
244	void (dma_isr)(void data);
245	void *dma_isr_arg;
246
247	SPIN_DECLARE(devlock)
248	};
249
250	int grpci2_init1(struct drvmgr_dev *dev);
251	int grpci2_init3(struct drvmgr_dev *dev);
252	void grpci2_err_isr(void *arg);
253	void grpci2_dma_isr(void *arg);
254
255	/* GRPCI2 DRIVER */
256
257	struct drvmgr_drv_ops grpci2_ops =
258	{
259	.init = {grpci2_init1, NULL, grpci2_init3, NULL},
260	.remove = NULL,
261	.info = NULL
262	};
263
264	struct amba_dev_id grpci2_ids[] =
265	{
266	{VENDOR_GAISLER, GAISLER_GRPCI2},
267	{0, 0} /* Mark end of table */
268	};
269
270	struct amba_drv_info grpci2_info =
271	{
272	{
273	DRVMGR_OBJ_DRV, /* Driver */
274	NULL, /* Next driver */
275	NULL, /* Device list */
276	DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
277	"GRPCI2_DRV", /* Driver Name */
278	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
279	&grpci2_ops,
280	NULL, /* Funcs */
281	0, /* No devices yet */
282	sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
283	},
284	&grpci2_ids[0]
285	};
286
287	/* Defaults to do nothing - user can override this function
288	* by including the DMA DRIVER.
289	*/
290	int __attribute__((weak)) grpci2dma_init(void * regs, void isr_register( void (isr)(void ), void * arg));
291
292	int grpci2dma_init(void * regs, void isr_register( void (isr)(void ), void * arg))
293	{
294	return 0;
295	}
296
297	/* Prototype of grpci2_dma_isr_register function */
298	static void grpci2_dma_isr_register( void (isr)(void ), void * arg);
299
300	void grpci2_register_drv(void)
301	{
302	DBG("Registering GRPCI2 driver\n");
303	drvmgr_drv_register(&grpci2_info.general);
304	}
305
306	static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
307	{
308	struct grpci2_priv *priv = grpci2priv;
309	volatile uint32_t *pci_conf;
310	unsigned int tmp, devfn;
311	int retval, bus = PCI_DEV_BUS(dev);
312	SPIN_IRQFLAGS(irqflags);
313
314	if ((unsigned int)ofs & 0xffffff03) {
315	retval = PCISTS_EINVAL;
316	goto out2;
317	}
318
319	if (PCI_DEV_SLOT(dev) > 15) {
320	retval = PCISTS_MSTABRT;
321	goto out;
322	}
323
324	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
325	* we skip them.
326	*/
327	if (dev == HOST_TGT)
328	bus = devfn = 0;
329	else if (bus == 0)
330	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
331	else
332	devfn = PCI_DEV_DEVFUNC(dev);
333
334	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
335
336	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
337
338	/* Select bus */
339	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
340	/* clear old status */
341	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
342
343	tmp = *pci_conf;
344
345	/* Wait until GRPCI2 signals that CFG access is done, it should be
346	* done instantaneously unless a DMA operation is ongoing...
347	*/
348	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
349	;
350
351	if (priv->regs->sts_cap & STS_CFGERR) {
352	retval = PCISTS_MSTABRT;
353	} else {
354	/* Bus always little endian (unaffected by byte-swapping) */
355	*val = CPU_swap_u32(tmp);
356	retval = PCISTS_OK;
357	}
358
359	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
360
361	out:
362	if (retval != PCISTS_OK)
363	*val = 0xffffffff;
364
365	DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
366	PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
367
368	out2:
369	return retval;
370	}
371
372	static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
373	{
374	uint32_t v;
375	int retval;
376
377	if (ofs & 1)
378	return PCISTS_EINVAL;
379
380	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
381	val = 0xffff & (v >> (8(ofs & 0x3)));
382
383	return retval;
384	}
385
386	static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
387	{
388	uint32_t v;
389	int retval;
390
391	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
392
393	val = 0xff & (v >> (8(ofs & 3)));
394
395	return retval;
396	}
397
398	static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
399	{
400	struct grpci2_priv *priv = grpci2priv;
401	volatile uint32_t *pci_conf;
402	uint32_t value, devfn;
403	int retval, bus = PCI_DEV_BUS(dev);
404	SPIN_IRQFLAGS(irqflags);
405
406	if ((unsigned int)ofs & 0xffffff03)
407	return PCISTS_EINVAL;
408
409	if (PCI_DEV_SLOT(dev) > 15)
410	return PCISTS_MSTABRT;
411
412	value = CPU_swap_u32(val);
413
414	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
415	* we skip them.
416	*/
417	if (dev == HOST_TGT)
418	bus = devfn = 0;
419	else if (bus == 0)
420	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
421	else
422	devfn = PCI_DEV_DEVFUNC(dev);
423
424	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
425
426	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
427
428	/* Select bus */
429	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
430	/* clear old status */
431	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
432
433	*pci_conf = value;
434
435	/* Wait until GRPCI2 signals that CFG access is done, it should be
436	* done instantaneously unless a DMA operation is ongoing...
437	*/
438	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
439	;
440
441	if (priv->regs->sts_cap & STS_CFGERR)
442	retval = PCISTS_MSTABRT;
443	else
444	retval = PCISTS_OK;
445
446	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
447
448	DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
449	PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
450
451	return retval;
452	}
453
454	static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
455	{
456	uint32_t v;
457	int retval;
458
459	if (ofs & 1)
460	return PCISTS_EINVAL;
461
462	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
463	if (retval != PCISTS_OK)
464	return retval;
465
466	v = (v & ~(0xffff << (8(ofs&3)))) \| ((0xffff&val) << (8(ofs&3)));
467
468	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
469	}
470
471	static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
472	{
473	uint32_t v;
474	int retval;
475
476	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
477	if (retval != PCISTS_OK)
478	return retval;
479
480	v = (v & ~(0xff << (8(ofs&3)))) \| ((0xff&val) << (8(ofs&3)));
481
482	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
483	}
484
485	/* Return the assigned system IRQ number that corresponds to the PCI
486	* "Interrupt Pin" information from configuration space.
487	*
488	* The IRQ information is stored in the grpci2_pci_irq_table configurable
489	* by the user.
490	*
491	* Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
492	* 0xff if not assigned.
493	*/
494	static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
495	{
496	uint8_t sysIrqNr = 0; /* not assigned */
497	int irq_group;
498
499	if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
500	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
501	irq_group = PCI_DEV_SLOT(dev) & 0x3;
502	irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
503	/* Valid PCI "Interrupt Pin" number */
504	sysIrqNr = grpci2_pci_irq_table[irq_pin];
505	}
506	return sysIrqNr;
507	}
508
509	static int grpci2_translate(uint32_t *address, int type, int dir)
510	{
511	uint32_t adr, start, end;
512	struct grpci2_priv *priv = grpci2priv;
513	int i;
514
515	if (type == 1) {
516	/* I/O */
517	if (dir != 0) {
518	/* The PCI bus can not access the CPU bus from I/O
519	* because GRPCI2 core does not support I/O BARs
520	*/
521	return -1;
522	}
523
524	/* We have got a PCI IO BAR address that the CPU want to access.
525	* Check that it is within the PCI I/O window, I/O adresses
526	* are NOT mapped 1:1 with GRPCI2 driver... translation needed.
527	*/
528	adr = (uint32_t )address;
529	if (adr < 0x100 \|\| adr > 0x10000)
530	return -1;
531	*address = adr + priv->pci_io;
532	} else {
533	/* MEMIO and MEM.
534	* Memory space is mapped 1:1 so no translation is needed.
535	* Check that address is within accessible windows.
536	*/
537	adr = (uint32_t )address;
538	if (dir == 0) {
539	/* PCI BAR to AMBA-CPU address.. check that it is
540	* located within GRPCI2 PCI Memory Window
541	* adr = PCI address.
542	*/
543	if (adr < priv->pci_area \|\| adr >= priv->pci_area_end)
544	return -1;
545	} else {
546	/* We have a CPU address and want to get access to it
547	* from PCI space, typically when doing DMA into CPU
548	* RAM. The GRPCI2 core may have multiple target BARs
549	* that PCI masters can access, the BARs are user
550	* configurable in the following ways:
551	* BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
552	*
553	* The below code tries to find a BAR for which the
554	* AMBA bar may have been mapped onto, and translate
555	* the AMBA-CPU address into a PCI address using the
556	* given mapping.
557	*
558	* adr = AMBA address.
559	*/
560	for(i=0; i<6; i++) {
561	start = priv->barcfg[i].ahbadr;
562	end = priv->barcfg[i].ahbadr +
563	priv->barcfg[i].barsize;
564	if (adr >= start && adr < end) {
565	/* BAR match: Translate address */
566	*address = (adr - start) +
567	priv->barcfg[i].pciadr;
568	return 0;
569	}
570	}
571	return -1;
572	}
573	}
574
575	return 0;
576	}
577
578	extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
579	extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
580
581	/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
582	struct pci_access_drv grpci2_access_drv = {
583	.cfg =
584	{
585	grpci2_cfg_r8,
586	grpci2_cfg_r16,
587	grpci2_cfg_r32,
588	grpci2_cfg_w8,
589	grpci2_cfg_w16,
590	grpci2_cfg_w32,
591	},
592	.io =
593	{
594	_ld8,
595	_ld_le16,
596	_ld_le32,
597	_st8,
598	_st_le16,
599	_st_le32,
600	},
601	.memreg = &pci_memreg_sparc_le_ops,
602	.translate = grpci2_translate,
603	};
604
605	struct pci_io_ops grpci2_io_ops_be =
606	{
607	_ld8,
608	_ld_be16,
609	_ld_be32,
610	_st8,
611	_st_be16,
612	_st_be32,
613	};
614
615	/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
616	* Abort.
617	*/
618	void grpci2_err_isr(void *arg)
619	{
620	struct grpci2_priv *priv = arg;
621	unsigned int sts = priv->regs->sts_cap;
622
623	if (sts & (STS_IMSTABRT \| STS_ITGTABRT \| STS_IPARERR \| STS_ISYSERR \| STS_ITIMEOUT)) {
624	/* A PCI error IRQ ... Error handler unimplemented
625	* add your code here...
626	*/
627	if (sts & STS_IMSTABRT) {
628	printk("GRPCI2: unhandled Master Abort IRQ\n");
629	}
630	if (sts & STS_ITGTABRT) {
631	printk("GRPCI2: unhandled Target Abort IRQ\n");
632	}
633	if (sts & STS_IPARERR) {
634	printk("GRPCI2: unhandled Parity Error IRQ\n");
635	}
636	if (sts & STS_ISYSERR) {
637	printk("GRPCI2: unhandled System Error IRQ\n");
638	}
639	if (sts & STS_ITIMEOUT) {
640	printk("GRPCI2: unhandled PCI target access timeout IRQ\n");
641	}
642	}
643	}
644
645	/* PCI DMA Interrupt handler, called when there may be a PCI DMA interrupt.
646	*/
647	void grpci2_dma_isr(void *arg)
648	{
649	struct grpci2_priv *priv = arg;
650	unsigned int sts = (priv->regs->sts_cap & (STS_IDMAERR \| STS_IDMA));
651
652	/* Clear Interrupt if taken*/
653	if (sts != 0){
654	/* Clear IDMAERR and IDMA bits */
655	priv->regs->sts_cap = (STS_IDMAERR \| STS_IDMA);
656	/* Clear DRVMGR interrupt */
657	drvmgr_interrupt_clear(priv->dev, priv->irq_dma);
658	/* Call DMA driver ISR */
659	(priv->dma_isr)(priv->dma_isr_arg);
660	}
661	}
662
663	static int grpci2_hw_init(struct grpci2_priv *priv)
664	{
665	struct grpci2_regs *regs = priv->regs;
666	int i;
667	uint8_t capptr;
668	uint32_t data, io_map, ahbadr, pciadr, size;
669	pci_dev_t host = HOST_TGT;
670	struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
671
672	/* Reset any earlier setup */
673	regs->ctrl = 0;
674	regs->sts_cap = ~0; /* Clear Status */
675	regs->dma_ctrl = 0;
676	regs->dma_bdbase = 0;
677
678	/* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
679	regs->io_map = priv->pci_io & 0xffff0000;
680
681	/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
682	* Each AHB master has it's own mapping registers. Max 16 AHB masters.
683	*/
684	for (i=0; i<16; i++)
685	regs->ahbmst_map[i] = priv->pci_area;
686
687	/* Get the GRPCI2 Host PCI ID */
688	grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
689
690	/* Get address to first (always defined) capability structure */
691	grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
692	if (capptr == 0)
693	return -1;
694
695	/* Limit the prefetch for GRPCI2 version 0. */
696	if (priv->ver == 0)
697	grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
698
699	/* Enable/Disable Byte twisting */
700	grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
701	io_map = (io_map & ~0x1) \| (priv->bt_enabled ? 1 : 0);
702	grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
703
704	/* Setup the Host's PCI Target BARs for others to access (DMA) */
705	for (i=0; i<6; i++) {
706	/* Make sure address is properly aligned */
707	size = ~(barcfg[i].barsize-1);
708	barcfg[i].pciadr &= size;
709	barcfg[i].ahbadr &= size;
710
711	pciadr = barcfg[i].pciadr;
712	ahbadr = barcfg[i].ahbadr;
713	size \|= PCIM_BAR_MEM_PREFETCH;
714
715	grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
716	grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
717	grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
718	}
719
720	/* set as bus master and enable pci memory responses */
721	grpci2_cfg_r32(host, PCIR_COMMAND, &data);
722	data \|= (PCIM_CMD_MEMEN \| PCIM_CMD_BUSMASTEREN);
723	grpci2_cfg_w32(host, PCIR_COMMAND, data);
724
725	/* set latency timer */
726	grpci2_cfg_r32(host, PCIR_CACHELNSZ, &data);
727	data &= ~0xff00;
728	data \|= ((priv->latency_timer & 0xff) << 8);
729	grpci2_cfg_w32(host, PCIR_CACHELNSZ, data);
730
731	/* Enable Error respone (CPU-TRAP) on illegal memory access */
732	regs->ctrl = CTRL_ER \| CTRL_PE;
733
734	/* Successful */
735	return 0;
736	}
737
738	/* Initializes the GRPCI2 core and driver, must be called before calling
739	* init_pci()
740	*
741	* Return values
742	* 0 Successful initalization
743	* -1 Error during initialization, for example "PCI core not found".
744	* -2 Error PCI controller not HOST (targets not supported)
745	* -3 Error due to GRPCI2 hardware initialization
746	*/
747	static int grpci2_init(struct grpci2_priv *priv)
748	{
749	struct ambapp_apb_info *apb;
750	struct ambapp_ahb_info *ahb;
751	int pin, i, j;
752	union drvmgr_key_value *value;
753	char keyname[6];
754	struct amba_dev_info *ainfo = priv->dev->businfo;
755	struct grpci2_pcibar_cfg *barcfg;
756	unsigned int size;
757
758	/* Find PCI core from Plug&Play information */
759	apb = ainfo->info.apb_slv;
760	ahb = ainfo->info.ahb_slv;
761
762	/* Found PCI core, init private structure */
763	priv->irq = apb->irq;
764	priv->ver = apb->ver;
765	priv->regs = (struct grpci2_regs *)apb->start;
766	priv->bt_enabled = DEFAULT_BT_ENABLED;
767	priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
768	priv->latency_timer = DEFAULT_LATENCY_TIMER;
769
770	/* Initialize Spin-lock for GRPCI2 Device. */
771	SPIN_INIT(&priv->devlock, "grpci2");
772
773	/* Calculate the PCI windows
774	* AMBA->PCI Window: AHB SLAVE AREA0
775	* AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
776	* AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
777	*/
778	priv->pci_area = ahb->start[0];
779	priv->pci_area_end = ahb->start[0] + ahb->mask[0];
780	priv->pci_io = ahb->start[1];
781	priv->pci_conf = ahb->start[1] + 0x10000;
782	priv->pci_conf_end = priv->pci_conf + 0x10000;
783
784	/* On systems where PCI I/O area and configuration area is apart of the
785	* "PCI Window" the PCI Window stops at the start of the PCI I/O area
786	*/
787	if ((priv->pci_io > priv->pci_area) &&
788	(priv->pci_io < (priv->pci_area_end-1))) {
789	priv->pci_area_end = priv->pci_io;
790	}
791
792	/* Init PCI interrupt assignment table to all use the interrupt routed
793	* through the GRPCI2 core.
794	*/
795	strcpy(keyname, "INTX#");
796	for (pin=1; pin<5; pin++) {
797	if (grpci2_pci_irq_table[pin-1] == 0xff) {
798	if (priv->irq_mode < 2) {
799	/* PCI Interrupts are shared */
800	grpci2_pci_irq_table[pin-1] = priv->irq;
801	} else {
802	/* Unique IRQ per PCI INT Pin */
803	grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
804	}
805
806	/* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
807	keyname[3] = 'A' + (pin-1);
808	value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT);
809	if (value)
810	grpci2_pci_irq_table[pin-1] = value->i;
811	}
812
813	/* Remember which IRQs are enabled */
814	if (grpci2_pci_irq_table[pin-1] != 0)
815	priv->irq_mask \|= 1 << (pin-1);
816	}
817
818	/* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
819	value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT);
820	if (value)
821	priv->bt_enabled = value->i;
822
823	/* Let user Configure the 6 target BARs */
824	value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", DRVMGR_KT_POINTER);
825	if (value)
826	priv->barcfg = value->ptr;
827	else
828	priv->barcfg = grpci2_default_bar_mapping;
829
830	/* User may override DEFAULT_LATENCY_TIMER */
831	value = drvmgr_dev_key_get(priv->dev, "latencyTimer", DRVMGR_KT_INT);
832	if (value)
833	priv->latency_timer = value->i;
834
835	/* This driver only support HOST systems, we check that it can act as a
836	* PCI Master and that it is in the Host slot. */
837	if ((priv->regs->sts_cap&STS_HOST) \|\| !(priv->regs->sts_cap&STS_MST))
838	return -2; /* Target not supported */
839
840	/* Init the PCI Core */
841	if (grpci2_hw_init(priv))
842	return -3;
843
844	/* Down streams translation table */
845	priv->maps_down[0].name = "AMBA -> PCI MEM Window";
846	priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
847	priv->maps_down[0].from_adr = (void *)priv->pci_area;
848	priv->maps_down[0].to_adr = (void *)priv->pci_area;
849	/* End table */
850	priv->maps_down[1].size = 0;
851
852	/* Up streams translation table */
853	/* Setup the Host's PCI Target BARs for others to access (DMA) */
854	barcfg = priv->barcfg;
855	for (i=0,j=0; i<6; i++) {
856	size = barcfg[i].barsize;
857	if (size == 0)
858	continue;
859
860	/* Make sure address is properly aligned */
861	priv->maps_up[j].name = "Target BAR[I] -> AMBA";
862	priv->maps_up[j].size = size;
863	priv->maps_up[j].from_adr = (void *)
864	(barcfg[i].pciadr & ~(size - 1));
865	priv->maps_up[j].to_adr = (void *)
866	(barcfg[i].ahbadr & ~(size - 1));
867	j++;
868	}
869
870	/* End table */
871	priv->maps_up[j].size = 0;
872
873	return 0;
874	}
875
876	/* Called when a core is found with the AMBA device and vendor ID
877	* given in grpci2_ids[]. IRQ, Console does not work here
878	*/
879	int grpci2_init1(struct drvmgr_dev *dev)
880	{
881	int status;
882	struct grpci2_priv *priv;
883	struct pci_auto_setup grpci2_auto_cfg;
884
885	DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
886
887	if (grpci2priv) {
888	DBG("Driver only supports one PCI core\n");
889	return DRVMGR_FAIL;
890	}
891
892	if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
893	(strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
894	/* We only support GRPCI2 driver on local bus */
895	return DRVMGR_FAIL;
896	}
897
898	priv = dev->priv;
899	if (!priv)
900	return DRVMGR_NOMEM;
901
902	priv->dev = dev;
903	grpci2priv = priv;
904
905	/* Initialize GRPCI2 Hardware */
906	status = grpci2_init(priv);
907	if (status) {
908	printk("Failed to initialize grpci2 driver %d\n", status);
909	return -1;
910	}
911
912	/* Register the PCI core at the PCI layers */
913
914	if (priv->bt_enabled == 0) {
915	/* Host is Big-Endian */
916	pci_endian = PCI_BIG_ENDIAN;
917
918	memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
919	sizeof(grpci2_io_ops_be));
920	grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
921	}
922
923	if (pci_access_drv_register(&grpci2_access_drv)) {
924	/* Access routines registration failed */
925	return DRVMGR_FAIL;
926	}
927
928	/* Prepare memory MAP */
929	grpci2_auto_cfg.options = 0;
930	grpci2_auto_cfg.mem_start = 0;
931	grpci2_auto_cfg.mem_size = 0;
932	grpci2_auto_cfg.memio_start = priv->pci_area;
933	grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
934	grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
935	grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
936	grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
937	grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
938	pci_config_register(&grpci2_auto_cfg);
939
940	if (pci_config_init()) {
941	/* PCI configuration failed */
942	return DRVMGR_FAIL;
943	}
944
945	/* Initialize/Register Driver Manager PCI Bus */
946	priv->config.maps_down = &priv->maps_down[0];
947	priv->config.maps_up = &priv->maps_up[0];
948	return pcibus_register(dev, &priv->config);
949	}
950
951	int grpci2_init3(struct drvmgr_dev *dev)
952	{
953	struct grpci2_priv *priv = dev->priv;
954
955	/* Install and Enable PCI Error interrupt handler */
956	drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
957
958	/* Initialize DMA driver (if supported) */
959	if (priv->regs->sts_cap & STS_DMA){
960	grpci2dma_init((void *) &(priv->regs->dma_ctrl), grpci2_dma_isr_register);
961	}
962
963	/* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
964	* safe every PCI board have to be resetted (no IRQ generation) before
965	* Global IRQs are enabled (Init is reached or similar)
966	*/
967	priv->regs->ctrl \|= (CTRL_EI \| priv->irq_mask);
968
969	return DRVMGR_OK;
970	}
971
972	static void grpci2_dma_isr_register( void (isr)(void ), void * arg)
973	{
974	struct grpci2_priv *priv = grpci2priv;
975
976	/* Handle unregistration */
977	if (priv->dma_isr != NULL) {
978	drvmgr_interrupt_unregister(priv->dev, priv->irq_dma, grpci2_dma_isr, priv);
979	/* Uninstall user ISR */
980	priv->dma_isr = NULL;
981	priv->dma_isr_arg = NULL;
982	}
983
984	if (isr == NULL)
985	return;
986
987	/* Install user ISR */
988	priv->dma_isr_arg = arg;
989	priv->dma_isr = isr;
990
991	/* Install and Enable PCI DMA interrupt handler */
992	if (priv->irq_mode == 1) {
993	priv->irq_dma = 1;
994	} else if (priv->irq_mode == 3) {
995	priv->irq_dma = 4;
996	} else {
997	priv->irq_dma = 0;
998	}
999	drvmgr_interrupt_register(priv->dev, priv->irq_dma, "grpci2dma", grpci2_dma_isr, priv);
1000	}

Note: See TracBrowser for help on using the repository browser.

Download in other formats: