source: rtems/bsps/sparc/shared/pci/grpci2.c @ 31720925

5
Last change on this file since 31720925 was 31720925, checked in by Sebastian Huber <sebastian.huber@…>, on 12/22/18 at 06:13:44

grlib: Move header files

Update #3678.

  • Property mode set to 100644
File size: 25.4 KB
Line 
1/*  GRLIB GRPCI2 PCI HOST driver.
2 *
3 *  COPYRIGHT (c) 2011
4 *  Cobham Gaisler AB.
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11/* Configures the GRPCI2 core and initialize,
12 *  - the PCI Library (pci.c)
13 *  - the general part of the PCI Bus driver (pci_bus.c)
14 * 
15 * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16 * default taken from Plug and Play, but may be overridden by the
17 * driver resources INTA#..INTD#. GRPCI2 handles differently depending
18 * on the design (4 different ways).
19 *
20 * GRPCI2 IRQ implementation notes
21 * -------------------------------
22 * Since the Driver Manager pci_bus layer implements IRQ by calling
23 * pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24 * root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25 * driver to use the drvmgr_interrupt_* routines since they will be
26 * accessing the same routines in the end. Otherwise the GRPCI2 driver must
27 * have used the pci_interrupt_* routines.
28 */
29
30#include <stdlib.h>
31#include <stdio.h>
32#include <string.h>
33#include <rtems.h>
34#include <rtems/bspIo.h>
35#include <libcpu/byteorder.h>
36#include <libcpu/access.h>
37#include <pci.h>
38#include <pci/cfg.h>
39
40#include <drvmgr/drvmgr.h>
41#include <grlib/ambapp_bus.h>
42#include <grlib/ambapp.h>
43#include <drvmgr/pci_bus.h>
44#include <grlib/grpci2.h>
45
46#include <grlib/grlib_impl.h>
47
48/* If defined to 1 - byte twisting is enabled by default */
49#define DEFAULT_BT_ENABLED 0
50
51/* If defined to 64 - Latency timer is 64 by default */
52#define DEFAULT_LATENCY_TIMER 64
53
54/* Interrupt assignment. Set to other value than 0xff in order to
55 * override defaults and plug&play information
56 */
57#ifndef GRPCI2_INTA_SYSIRQ
58 #define GRPCI2_INTA_SYSIRQ 0xff
59#endif
60#ifndef GRPCI2_INTB_SYSIRQ
61 #define GRPCI2_INTB_SYSIRQ 0xff
62#endif
63#ifndef GRPCI2_INTC_SYSIRQ
64 #define GRPCI2_INTC_SYSIRQ 0xff
65#endif
66#ifndef GRPCI2_INTD_SYSIRQ
67 #define GRPCI2_INTD_SYSIRQ 0xff
68#endif
69
70/*#define DEBUG 1*/
71
72#ifdef DEBUG
73#define DBG(x...) printk(x)
74#else
75#define DBG(x...)
76#endif
77
78/*
79 * GRPCI2 APB Register MAP
80 */
81struct grpci2_regs {
82        volatile unsigned int ctrl;             /* 0x00 */
83        volatile unsigned int sts_cap;          /* 0x04 */
84        volatile unsigned int ppref;            /* 0x08 */
85        volatile unsigned int io_map;           /* 0x0C */
86        volatile unsigned int dma_ctrl;         /* 0x10 */
87        volatile unsigned int dma_bdbase;       /* 0x14 */
88        volatile unsigned int dma_chact;        /* 0x18 */
89        int res1;                               /* 0x1C */
90        volatile unsigned int bars[6];          /* 0x20 */
91        int res2[2];                            /* 0x38 */
92        volatile unsigned int ahbmst_map[16];   /* 0x40 */
93};
94
95#define CTRL_BUS_BIT 16
96
97#define CTRL_SI (1<<27)
98#define CTRL_PE (1<<26)
99#define CTRL_ER (1<<25)
100#define CTRL_EI (1<<24)
101#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
102#define CTRL_HOSTINT 0xf
103
104#define STS_HOST_BIT    31
105#define STS_MST_BIT     30
106#define STS_TAR_BIT     29
107#define STS_DMA_BIT     28
108#define STS_DI_BIT      27
109#define STS_HI_BIT      26
110#define STS_IRQMODE_BIT 24
111#define STS_TRACE_BIT   23
112#define STS_CFGERRVALID_BIT 20
113#define STS_CFGERR_BIT  19
114#define STS_INTTYPE_BIT 12
115#define STS_INTSTS_BIT  8
116#define STS_FDEPTH_BIT  2
117#define STS_FNUM_BIT    0
118
119#define STS_HOST        (1<<STS_HOST_BIT)
120#define STS_MST         (1<<STS_MST_BIT)
121#define STS_TAR         (1<<STS_TAR_BIT)
122#define STS_DMA         (1<<STS_DMA_BIT)
123#define STS_DI          (1<<STS_DI_BIT)
124#define STS_HI          (1<<STS_HI_BIT)
125#define STS_IRQMODE     (0x3<<STS_IRQMODE_BIT)
126#define STS_TRACE       (1<<STS_TRACE_BIT)
127#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
128#define STS_CFGERR      (1<<STS_CFGERR_BIT)
129#define STS_INTTYPE     (0x7f<<STS_INTTYPE_BIT)
130#define STS_INTSTS      (0xf<<STS_INTSTS_BIT)
131#define STS_FDEPTH      (0x7<<STS_FDEPTH_BIT)
132#define STS_FNUM        (0x3<<STS_FNUM_BIT)
133
134#define STS_ITIMEOUT    (1<<18)
135#define STS_ISYSERR     (1<<17)
136#define STS_IDMA        (1<<16)
137#define STS_IDMAERR     (1<<15)
138#define STS_IMSTABRT    (1<<14)
139#define STS_ITGTABRT    (1<<13)
140#define STS_IPARERR     (1<<12)
141
142/* GRPCI2 Capability */
143struct grpci2_cap_first {
144        unsigned int ctrl;
145        unsigned int pci2ahb_map[6];
146        unsigned int ext2ahb_map;
147        unsigned int io_map;
148        unsigned int pcibar_size[6];
149        unsigned int ahb_pref;
150};
151#define CAP9_CTRL_OFS 0
152#define CAP9_BAR_OFS 0x4
153#define CAP9_IOMAP_OFS 0x20
154#define CAP9_BARSIZE_OFS 0x24
155#define CAP9_AHBPREF_OFS 0x3C
156
157/* Used internally for accessing the PCI bridge's configuration space itself */
158#define HOST_TGT PCI_DEV(0xff, 0, 0)
159
160struct grpci2_priv *grpci2priv = NULL;
161
162/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
163 * to a system interrupt number.
164 */
165unsigned char grpci2_pci_irq_table[4] =
166{
167        /* INTA# */     GRPCI2_INTA_SYSIRQ,
168        /* INTB# */     GRPCI2_INTB_SYSIRQ,
169        /* INTC# */     GRPCI2_INTC_SYSIRQ,
170        /* INTD# */     GRPCI2_INTD_SYSIRQ
171};
172
173/* Start of workspace/dynamical area */
174extern unsigned int _end;
175#define DMA_START ((unsigned int) &_end)
176
177/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
178struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
179        /* BAR0 */ {DMA_START, DMA_START, 0x10000000},
180        /* BAR1 */ {0, 0, 0},
181        /* BAR2 */ {0, 0, 0},
182        /* BAR3 */ {0, 0, 0},
183        /* BAR4 */ {0, 0, 0},
184        /* BAR5 */ {0, 0, 0},
185};
186
187/* Driver private data struture */
188struct grpci2_priv {
189        struct drvmgr_dev               *dev;
190        struct grpci2_regs              *regs;
191        unsigned char                   ver;
192        char                            irq;
193        char                            irq_mode; /* IRQ Mode from CAPSTS REG */
194        char                            irq_dma; /* IRQ Index for DMA */
195        char                            bt_enabled;
196        unsigned int                    irq_mask;
197        unsigned int                    latency_timer;
198
199        struct grpci2_pcibar_cfg        *barcfg;
200
201        unsigned int                    pci_area;
202        unsigned int                    pci_area_end;
203        unsigned int                    pci_io;   
204        unsigned int                    pci_conf;
205        unsigned int                    pci_conf_end;
206
207        uint32_t                        devVend; /* Host PCI Device/Vendor ID */
208
209        struct drvmgr_map_entry         maps_up[7];
210        struct drvmgr_map_entry         maps_down[2];
211        struct pcibus_config            config;
212
213        /* DMA interrupts */
214        void (*dma_isr)(void *data);
215        void *dma_isr_arg;
216
217        SPIN_DECLARE(devlock)
218};
219
220int grpci2_init1(struct drvmgr_dev *dev);
221int grpci2_init3(struct drvmgr_dev *dev);
222void grpci2_err_isr(void *arg);
223void grpci2_dma_isr(void *arg);
224
225/* GRPCI2 DRIVER */
226
227struct drvmgr_drv_ops grpci2_ops =
228{
229        .init = {grpci2_init1, NULL, grpci2_init3, NULL},
230        .remove = NULL,
231        .info = NULL
232};
233
234struct amba_dev_id grpci2_ids[] =
235{
236        {VENDOR_GAISLER, GAISLER_GRPCI2},
237        {0, 0}          /* Mark end of table */
238};
239
240struct amba_drv_info grpci2_info =
241{
242        {
243                DRVMGR_OBJ_DRV,                 /* Driver */
244                NULL,                           /* Next driver */
245                NULL,                           /* Device list */
246                DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
247                "GRPCI2_DRV",                   /* Driver Name */
248                DRVMGR_BUS_TYPE_AMBAPP,         /* Bus Type */
249                &grpci2_ops,
250                NULL,                           /* Funcs */
251                0,                              /* No devices yet */
252                sizeof(struct grpci2_priv),     /* Make drvmgr alloc private */
253        },
254        &grpci2_ids[0]
255};
256
257/* Defaults to do nothing - user can override this function
258 * by including the DMA DRIVER.
259 */
260int __attribute__((weak)) grpci2dma_init(void * regs, void isr_register( void (*isr)(void *), void * arg));
261
262int grpci2dma_init(void * regs, void isr_register( void (*isr)(void *), void * arg))
263{
264        return 0;
265}
266
267/* Prototype of grpci2_dma_isr_register function */
268static void grpci2_dma_isr_register( void (*isr)(void *), void * arg);
269
270void grpci2_register_drv(void)
271{
272        DBG("Registering GRPCI2 driver\n");
273        drvmgr_drv_register(&grpci2_info.general);
274}
275
276static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
277{
278        struct grpci2_priv *priv = grpci2priv;
279        volatile uint32_t *pci_conf;
280        unsigned int tmp, devfn;
281        int retval, bus = PCI_DEV_BUS(dev);
282        SPIN_IRQFLAGS(irqflags);
283
284        if ((unsigned int)ofs & 0xffffff03) {
285                retval = PCISTS_EINVAL;
286                goto out2;
287        }
288
289        if (PCI_DEV_SLOT(dev) > 15) {
290                retval = PCISTS_MSTABRT;
291                goto out;
292        }
293
294        /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
295         * we skip them.
296         */
297        if (dev == HOST_TGT)
298                bus = devfn = 0;
299        else if (bus == 0)
300                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
301        else
302                devfn = PCI_DEV_DEVFUNC(dev);
303
304        pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
305
306        SPIN_LOCK_IRQ(&priv->devlock, irqflags);
307
308        /* Select bus */
309        priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
310        /* clear old status */
311        priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
312
313        tmp = *pci_conf;
314
315        /* Wait until GRPCI2 signals that CFG access is done, it should be
316         * done instantaneously unless a DMA operation is ongoing...
317         */
318        while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
319                ;
320
321        if (priv->regs->sts_cap & STS_CFGERR) {
322                retval = PCISTS_MSTABRT;
323        } else {
324                /* Bus always little endian (unaffected by byte-swapping) */
325                *val = CPU_swap_u32(tmp);
326                retval = PCISTS_OK;
327        }
328
329        SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
330
331out:
332        if (retval != PCISTS_OK)
333                *val = 0xffffffff;
334
335        DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x  (%d)\n",
336                PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
337
338out2:
339        return retval;
340}
341
342static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
343{
344        uint32_t v;
345        int retval;
346
347        if (ofs & 1)
348                return PCISTS_EINVAL;
349
350        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
351        *val = 0xffff & (v >> (8*(ofs & 0x3)));
352
353        return retval;
354}
355
356static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
357{
358        uint32_t v;
359        int retval;
360
361        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
362
363        *val = 0xff & (v >> (8*(ofs & 3)));
364
365        return retval;
366}
367
368static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
369{
370        struct grpci2_priv *priv = grpci2priv;
371        volatile uint32_t *pci_conf;
372        uint32_t value, devfn;
373        int retval, bus = PCI_DEV_BUS(dev);
374        SPIN_IRQFLAGS(irqflags);
375
376        if ((unsigned int)ofs & 0xffffff03)
377                return PCISTS_EINVAL;
378
379        if (PCI_DEV_SLOT(dev) > 15)
380                return PCISTS_MSTABRT;
381
382        value = CPU_swap_u32(val);
383
384        /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
385         * we skip them.
386         */
387        if (dev == HOST_TGT)
388                bus = devfn = 0;
389        else if (bus == 0)
390                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
391        else
392                devfn = PCI_DEV_DEVFUNC(dev);
393
394        pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
395
396        SPIN_LOCK_IRQ(&priv->devlock, irqflags);
397
398        /* Select bus */
399        priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
400        /* clear old status */
401        priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
402
403        *pci_conf = value;
404
405        /* Wait until GRPCI2 signals that CFG access is done, it should be
406         * done instantaneously unless a DMA operation is ongoing...
407         */
408        while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
409                ;
410
411        if (priv->regs->sts_cap & STS_CFGERR)
412                retval = PCISTS_MSTABRT;
413        else
414                retval = PCISTS_OK;
415
416        SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
417
418        DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x  (%d)\n",
419                PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
420
421        return retval;
422}
423
424static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
425{
426        uint32_t v;
427        int retval;
428
429        if (ofs & 1)
430                return PCISTS_EINVAL;
431
432        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
433        if (retval != PCISTS_OK)
434                return retval;
435
436        v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
437
438        return grpci2_cfg_w32(dev, ofs & ~0x3, v);
439}
440
441static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
442{
443        uint32_t v;
444        int retval;
445
446        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
447        if (retval != PCISTS_OK)
448                return retval;
449
450        v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
451
452        return grpci2_cfg_w32(dev, ofs & ~0x3, v);
453}
454
455/* Return the assigned system IRQ number that corresponds to the PCI
456 * "Interrupt Pin" information from configuration space.
457 *
458 * The IRQ information is stored in the grpci2_pci_irq_table configurable
459 * by the user.
460 *
461 * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
462 * 0xff if not assigned.
463 */
464static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
465{
466        uint8_t sysIrqNr = 0; /* not assigned */
467        int irq_group;
468
469        if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
470                /* Use default IRQ decoding on PCI BUS0 according slot numbering */
471                irq_group = PCI_DEV_SLOT(dev) & 0x3;
472                irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
473                /* Valid PCI "Interrupt Pin" number */
474                sysIrqNr = grpci2_pci_irq_table[irq_pin];
475        }
476        return sysIrqNr;
477}
478
479static int grpci2_translate(uint32_t *address, int type, int dir)
480{
481        uint32_t adr, start, end;
482        struct grpci2_priv *priv = grpci2priv;
483        int i;
484
485        if (type == 1) {
486                /* I/O */
487                if (dir != 0) {
488                        /* The PCI bus can not access the CPU bus from I/O
489                         * because GRPCI2 core does not support I/O BARs
490                         */
491                        return -1;
492                }
493
494                /* We have got a PCI IO BAR address that the CPU want to access.
495                 * Check that it is within the PCI I/O window, I/O adresses
496                 * are NOT mapped 1:1 with GRPCI2 driver... translation needed.
497                 */
498                adr = *(uint32_t *)address;
499                if (adr < 0x100 || adr > 0x10000)
500                        return -1;
501                *address = adr + priv->pci_io;
502        } else {
503                /* MEMIO and MEM.
504                 * Memory space is mapped 1:1 so no translation is needed.
505                 * Check that address is within accessible windows.
506                 */
507                adr = *(uint32_t *)address;
508                if (dir == 0) {
509                        /* PCI BAR to AMBA-CPU address.. check that it is
510                         * located within GRPCI2 PCI Memory Window
511                         * adr = PCI address.
512                         */
513                        if (adr < priv->pci_area || adr >= priv->pci_area_end)
514                                return -1;
515                } else {
516                        /* We have a CPU address and want to get access to it
517                         * from PCI space, typically when doing DMA into CPU
518                         * RAM. The GRPCI2 core may have multiple target BARs
519                         * that PCI masters can access, the BARs are user
520                         * configurable in the following ways:
521                         *  BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
522                         *
523                         * The below code tries to find a BAR for which the
524                         * AMBA bar may have been mapped onto, and translate
525                         * the AMBA-CPU address into a PCI address using the
526                         * given mapping.
527                         *
528                         * adr = AMBA address.
529                         */
530                        for(i=0; i<6; i++) {
531                                start = priv->barcfg[i].ahbadr;
532                                end = priv->barcfg[i].ahbadr +
533                                        priv->barcfg[i].barsize;
534                                if (adr >= start && adr < end) {
535                                        /* BAR match: Translate address */
536                                        *address = (adr - start) +
537                                                priv->barcfg[i].pciadr;
538                                        return 0;
539                                }
540                        }
541                        return -1;
542                }
543        }
544
545        return 0;
546}
547
548extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
549extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
550
551/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
552struct pci_access_drv grpci2_access_drv = {
553        .cfg =
554        {
555                grpci2_cfg_r8,
556                grpci2_cfg_r16,
557                grpci2_cfg_r32,
558                grpci2_cfg_w8,
559                grpci2_cfg_w16,
560                grpci2_cfg_w32,
561        },
562        .io =
563        {
564                _ld8,
565                _ld_le16,
566                _ld_le32,
567                _st8,
568                _st_le16,
569                _st_le32,
570        },
571        .memreg = &pci_memreg_sparc_le_ops,
572        .translate = grpci2_translate,
573};
574
575struct pci_io_ops grpci2_io_ops_be =
576{
577        _ld8,
578        _ld_be16,
579        _ld_be32,
580        _st8,
581        _st_be16,
582        _st_be32,
583};
584
585/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
586 * Abort.
587 */
588void grpci2_err_isr(void *arg)
589{
590        struct grpci2_priv *priv = arg;
591        unsigned int sts = priv->regs->sts_cap;
592
593        if (sts & (STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR | STS_ISYSERR | STS_ITIMEOUT)) {
594                /* A PCI error IRQ ... Error handler unimplemented
595                 * add your code here...
596                 */
597                if (sts & STS_IMSTABRT) {
598                        printk("GRPCI2: unhandled Master Abort IRQ\n");
599                }
600                if (sts & STS_ITGTABRT) {
601                        printk("GRPCI2: unhandled Target Abort IRQ\n");
602                }
603                if (sts & STS_IPARERR) {
604                        printk("GRPCI2: unhandled Parity Error IRQ\n");
605                }
606                if (sts & STS_ISYSERR) {
607                        printk("GRPCI2: unhandled System Error IRQ\n");
608                }
609                if (sts & STS_ITIMEOUT) {
610                        printk("GRPCI2: unhandled PCI target access timeout IRQ\n");
611                }
612        }
613}
614
615/* PCI DMA Interrupt handler, called when there may be a PCI DMA interrupt.
616 */
617void grpci2_dma_isr(void *arg)
618{
619        struct grpci2_priv *priv = arg;
620        unsigned int sts = (priv->regs->sts_cap & (STS_IDMAERR | STS_IDMA));
621
622        /* Clear Interrupt if taken*/
623        if (sts != 0){
624                /* Clear IDMAERR and IDMA bits */
625                priv->regs->sts_cap = (STS_IDMAERR | STS_IDMA);
626                /* Clear DRVMGR interrupt */
627                drvmgr_interrupt_clear(priv->dev, priv->irq_dma);
628                /* Call DMA driver ISR */
629                (priv->dma_isr)(priv->dma_isr_arg);
630        }
631}
632
633static int grpci2_hw_init(struct grpci2_priv *priv)
634{
635        struct grpci2_regs *regs = priv->regs;
636        int i;
637        uint8_t capptr;
638        uint32_t data, io_map, ahbadr, pciadr, size;
639        pci_dev_t host = HOST_TGT;
640        struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
641
642        /* Reset any earlier setup */
643        regs->ctrl = 0;
644        regs->sts_cap = ~0; /* Clear Status */
645        regs->dma_ctrl = 0;
646        regs->dma_bdbase = 0;
647
648        /* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
649        regs->io_map = priv->pci_io & 0xffff0000;
650
651        /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
652         * Each AHB master has it's own mapping registers. Max 16 AHB masters.
653         */
654        for (i=0; i<16; i++)
655                regs->ahbmst_map[i] = priv->pci_area;
656
657        /* Get the GRPCI2 Host PCI ID */
658        grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
659
660        /* Get address to first (always defined) capability structure */
661        grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
662        if (capptr == 0)
663                return -1;
664
665        /* Limit the prefetch for GRPCI2 version 0. */
666        if (priv->ver == 0)
667                grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
668
669        /* Enable/Disable Byte twisting */
670        grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
671        io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
672        grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
673
674        /* Setup the Host's PCI Target BARs for others to access (DMA) */
675        for (i=0; i<6; i++) {
676                /* Make sure address is properly aligned */
677                size = ~(barcfg[i].barsize-1);
678                barcfg[i].pciadr &= size;
679                barcfg[i].ahbadr &= size;
680
681                pciadr = barcfg[i].pciadr;
682                ahbadr = barcfg[i].ahbadr;
683                size |= PCIM_BAR_MEM_PREFETCH;
684
685                grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
686                grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
687                grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
688        }
689
690        /* set as bus master and enable pci memory responses */ 
691        grpci2_cfg_r32(host, PCIR_COMMAND, &data);
692        data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
693        grpci2_cfg_w32(host, PCIR_COMMAND, data);
694
695        /* set latency timer */
696        grpci2_cfg_r32(host, PCIR_CACHELNSZ, &data);
697        data &= ~0xff00;
698        data |= ((priv->latency_timer & 0xff) << 8);
699        grpci2_cfg_w32(host, PCIR_CACHELNSZ, data);
700
701        /* Enable Error respone (CPU-TRAP) on illegal memory access */
702        regs->ctrl = CTRL_ER | CTRL_PE;
703
704        /* Successful */
705        return 0;
706}
707
708/* Initializes the GRPCI2 core and driver, must be called before calling
709 * init_pci()
710 *
711 * Return values
712 *  0             Successful initalization
713 *  -1            Error during initialization, for example "PCI core not found".
714 *  -2            Error PCI controller not HOST (targets not supported)
715 *  -3            Error due to GRPCI2 hardware initialization
716 */
717static int grpci2_init(struct grpci2_priv *priv)
718{
719        struct ambapp_apb_info *apb;
720        struct ambapp_ahb_info *ahb;
721        int pin, i, j;
722        union drvmgr_key_value *value;
723        char keyname[6];
724        struct amba_dev_info *ainfo = priv->dev->businfo;
725        struct grpci2_pcibar_cfg *barcfg;
726        unsigned int size;
727
728        /* Find PCI core from Plug&Play information */
729        apb = ainfo->info.apb_slv;
730        ahb = ainfo->info.ahb_slv;
731
732        /* Found PCI core, init private structure */
733        priv->irq = apb->irq;
734        priv->ver = apb->ver;
735        priv->regs = (struct grpci2_regs *)apb->start;
736        priv->bt_enabled = DEFAULT_BT_ENABLED;
737        priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
738        priv->latency_timer = DEFAULT_LATENCY_TIMER;
739
740        /* Initialize Spin-lock for GRPCI2 Device. */
741        SPIN_INIT(&priv->devlock, "grpci2");
742
743        /* Calculate the PCI windows
744         *  AMBA->PCI Window:                       AHB SLAVE AREA0
745         *  AMBA->PCI I/O cycles Window:            AHB SLAVE AREA1 Lower half
746         *  AMBA->PCI Configuration cycles Window:  AHB SLAVE AREA1 Upper half
747         */
748        priv->pci_area     = ahb->start[0];
749        priv->pci_area_end = ahb->start[0] + ahb->mask[0];
750        priv->pci_io       = ahb->start[1];
751        priv->pci_conf     = ahb->start[1] + 0x10000;
752        priv->pci_conf_end = priv->pci_conf + 0x10000;
753
754        /* On systems where PCI I/O area and configuration area is apart of the
755         * "PCI Window" the PCI Window stops at the start of the PCI I/O area
756         */
757        if ((priv->pci_io > priv->pci_area) &&
758            (priv->pci_io < (priv->pci_area_end-1))) {
759                priv->pci_area_end = priv->pci_io;
760        }
761
762        /* Init PCI interrupt assignment table to all use the interrupt routed
763         * through the GRPCI2 core.
764         */
765        strcpy(keyname, "INTX#");
766        for (pin=1; pin<5; pin++) {
767                if (grpci2_pci_irq_table[pin-1] == 0xff) {
768                        if (priv->irq_mode < 2) {
769                                /* PCI Interrupts are shared */
770                                grpci2_pci_irq_table[pin-1] = priv->irq;
771                        } else {
772                                /* Unique IRQ per PCI INT Pin */
773                                grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
774                        }
775
776                        /* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
777                        keyname[3] = 'A' + (pin-1);
778                        value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT);
779                        if (value)
780                                grpci2_pci_irq_table[pin-1] = value->i;
781                }
782
783                /* Remember which IRQs are enabled */
784                if (grpci2_pci_irq_table[pin-1] != 0)
785                        priv->irq_mask |= 1 << (pin-1);
786        }
787
788        /* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
789        value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT);
790        if (value)
791                priv->bt_enabled = value->i;
792
793        /* Let user Configure the 6 target BARs */
794        value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", DRVMGR_KT_POINTER);
795        if (value)
796                priv->barcfg = value->ptr;
797        else
798                priv->barcfg = grpci2_default_bar_mapping;
799
800        /* User may override DEFAULT_LATENCY_TIMER */
801        value = drvmgr_dev_key_get(priv->dev, "latencyTimer", DRVMGR_KT_INT);
802        if (value)
803                priv->latency_timer = value->i;
804
805        /* This driver only support HOST systems, we check that it can act as a
806         * PCI Master and that it is in the Host slot. */
807        if ((priv->regs->sts_cap&STS_HOST) || !(priv->regs->sts_cap&STS_MST))
808                return -2; /* Target not supported */
809
810        /* Init the PCI Core */
811        if (grpci2_hw_init(priv))
812                return -3;
813
814        /* Down streams translation table */
815        priv->maps_down[0].name = "AMBA -> PCI MEM Window";
816        priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
817        priv->maps_down[0].from_adr = (void *)priv->pci_area;
818        priv->maps_down[0].to_adr = (void *)priv->pci_area;
819        /* End table */
820        priv->maps_down[1].size = 0;
821
822        /* Up streams translation table */
823        /* Setup the Host's PCI Target BARs for others to access (DMA) */
824        barcfg = priv->barcfg;
825        for (i=0,j=0; i<6; i++) {
826                size = barcfg[i].barsize;
827                if (size == 0)
828                        continue;
829
830                /* Make sure address is properly aligned */
831                priv->maps_up[j].name = "Target BAR[I] -> AMBA";
832                priv->maps_up[j].size = size;
833                priv->maps_up[j].from_adr = (void *)
834                                        (barcfg[i].pciadr & ~(size - 1));
835                priv->maps_up[j].to_adr = (void *)
836                                        (barcfg[i].ahbadr & ~(size - 1));
837                j++;
838        }
839
840        /* End table */
841        priv->maps_up[j].size = 0;
842
843        return 0;
844}
845
846/* Called when a core is found with the AMBA device and vendor ID
847 * given in grpci2_ids[]. IRQ, Console does not work here
848 */
849int grpci2_init1(struct drvmgr_dev *dev)
850{
851        int status;
852        struct grpci2_priv *priv;
853        struct pci_auto_setup grpci2_auto_cfg;
854
855        DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
856
857        if (grpci2priv) {
858                DBG("Driver only supports one PCI core\n");
859                return DRVMGR_FAIL;
860        }
861
862        if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
863            (strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
864                /* We only support GRPCI2 driver on local bus */
865                return DRVMGR_FAIL;
866        }
867
868        priv = dev->priv;
869        if (!priv)
870                return DRVMGR_NOMEM;
871
872        priv->dev = dev;
873        grpci2priv = priv;
874
875        /* Initialize GRPCI2 Hardware */
876        status = grpci2_init(priv);
877        if (status) {
878                printk("Failed to initialize grpci2 driver %d\n", status);
879                return -1;
880        }
881
882        /* Register the PCI core at the PCI layers */
883
884        if (priv->bt_enabled == 0) {
885                /* Host is Big-Endian */
886                pci_endian = PCI_BIG_ENDIAN;
887
888                memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
889                                                sizeof(grpci2_io_ops_be));
890                grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
891        }
892
893        if (pci_access_drv_register(&grpci2_access_drv)) {
894                /* Access routines registration failed */
895                return DRVMGR_FAIL;
896        }
897
898        /* Prepare memory MAP */
899        grpci2_auto_cfg.options = 0;
900        grpci2_auto_cfg.mem_start = 0;
901        grpci2_auto_cfg.mem_size = 0;
902        grpci2_auto_cfg.memio_start = priv->pci_area;
903        grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
904        grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
905        grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
906        grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
907        grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
908        pci_config_register(&grpci2_auto_cfg);
909
910        if (pci_config_init()) {
911                /* PCI configuration failed */
912                return DRVMGR_FAIL;
913        }
914
915        /* Initialize/Register Driver Manager PCI Bus */
916        priv->config.maps_down = &priv->maps_down[0];
917        priv->config.maps_up = &priv->maps_up[0];
918        return pcibus_register(dev, &priv->config);
919}
920
921int grpci2_init3(struct drvmgr_dev *dev)
922{
923        struct grpci2_priv *priv = dev->priv;
924
925        /* Install and Enable PCI Error interrupt handler */
926        drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
927
928        /* Initialize DMA driver (if supported) */
929        if (priv->regs->sts_cap & STS_DMA){
930                grpci2dma_init((void *) &(priv->regs->dma_ctrl), grpci2_dma_isr_register);
931        }
932
933        /* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
934         * safe every PCI board have to be resetted (no IRQ generation) before
935         * Global IRQs are enabled (Init is reached or similar)
936         */
937        priv->regs->ctrl |= (CTRL_EI | priv->irq_mask);
938
939        return DRVMGR_OK;
940}
941
942static void grpci2_dma_isr_register( void (*isr)(void *), void * arg)
943{
944        struct grpci2_priv *priv = grpci2priv;
945
946        /* Handle unregistration */
947        if (priv->dma_isr != NULL) {
948                drvmgr_interrupt_unregister(priv->dev, priv->irq_dma, grpci2_dma_isr, priv);
949                /* Uninstall user ISR */
950                priv->dma_isr = NULL;
951                priv->dma_isr_arg = NULL;
952        }
953
954        if (isr == NULL)
955                return;
956
957        /* Install user ISR */
958        priv->dma_isr_arg = arg;
959        priv->dma_isr = isr;
960
961        /* Install and Enable PCI DMA interrupt handler */
962        if (priv->irq_mode == 1) {
963                priv->irq_dma = 1;
964        } else if (priv->irq_mode == 3) {
965                priv->irq_dma = 4;
966        } else {
967                priv->irq_dma = 0;
968        }
969        drvmgr_interrupt_register(priv->dev, priv->irq_dma, "grpci2dma", grpci2_dma_isr, priv);
970}
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