1 | /* GRLIB GRPCI PCI HOST driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2008. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * Configures the GRPCI core and initialize, |
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7 | * - the PCI Library (pci.c) |
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8 | * - the general part of the PCI Bus driver (pci_bus.c) |
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9 | * |
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10 | * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by |
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11 | * default taken from Plug and Play, but may be overridden by the |
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12 | * driver resources INTA#..INTD#. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #include <stdlib.h> |
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20 | #include <stdio.h> |
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21 | #include <string.h> |
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22 | #include <rtems/bspIo.h> |
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23 | #include <libcpu/byteorder.h> |
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24 | #include <libcpu/access.h> |
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25 | #include <pci.h> |
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26 | #include <pci/cfg.h> |
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27 | |
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28 | #include <drvmgr/drvmgr.h> |
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29 | #include <drvmgr/ambapp_bus.h> |
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30 | #include <ambapp.h> |
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31 | #include <drvmgr/pci_bus.h> |
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32 | #include <bsp/grpci.h> |
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33 | |
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34 | #define DMAPCI_ADDR 0x80000500 |
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35 | |
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36 | /* Configuration options */ |
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37 | #define SYSTEM_MAINMEM_START 0x40000000 |
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38 | |
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39 | /* If defined to 1 - byte twisting is enabled by default */ |
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40 | #define DEFAULT_BT_ENABLED 0 |
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41 | |
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42 | /* Interrupt assignment. Set to other value than 0xff in order to |
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43 | * override defaults and plug&play information |
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44 | */ |
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45 | #ifndef GRPCI_INTA_SYSIRQ |
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46 | #define GRPCI_INTA_SYSIRQ 0xff |
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47 | #endif |
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48 | #ifndef GRPCI_INTB_SYSIRQ |
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49 | #define GRPCI_INTB_SYSIRQ 0xff |
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50 | #endif |
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51 | #ifndef GRPCI_INTC_SYSIRQ |
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52 | #define GRPCI_INTC_SYSIRQ 0xff |
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53 | #endif |
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54 | #ifndef GRPCI_INTD_SYSIRQ |
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55 | #define GRPCI_INTD_SYSIRQ 0xff |
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56 | #endif |
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57 | |
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58 | #define PAGE0_BTEN_BIT 0 |
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59 | #define PAGE0_BTEN (1<<PAGE0_BTEN_BIT) |
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60 | |
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61 | #define CFGSTAT_HOST_BIT 13 |
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62 | #define CFGSTAT_HOST (1<<CFGSTAT_HOST_BIT) |
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63 | |
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64 | /*#define DEBUG 1*/ |
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65 | |
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66 | #ifdef DEBUG |
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67 | #define DBG(x...) printk(x) |
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68 | #else |
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69 | #define DBG(x...) |
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70 | #endif |
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71 | |
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72 | /* |
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73 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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74 | */ |
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75 | struct grpci_regs { |
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76 | volatile unsigned int cfg_stat; |
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77 | volatile unsigned int bar0; |
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78 | volatile unsigned int page0; |
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79 | volatile unsigned int bar1; |
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80 | volatile unsigned int page1; |
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81 | volatile unsigned int iomap; |
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82 | volatile unsigned int stat_cmd; |
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83 | volatile unsigned int irq; |
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84 | }; |
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85 | |
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86 | #define HOST_TGT PCI_DEV(0xff, 0, 0) |
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87 | |
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88 | struct grpci_priv *grpcipriv = NULL; |
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89 | static int grpci_minor = 0; |
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90 | static unsigned int *pcidma = (unsigned int *)DMAPCI_ADDR; |
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91 | |
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92 | /* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#) |
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93 | * to a system interrupt number. |
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94 | */ |
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95 | unsigned char grpci_pci_irq_table[4] = |
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96 | { |
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97 | /* INTA# */ GRPCI_INTA_SYSIRQ, |
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98 | /* INTB# */ GRPCI_INTB_SYSIRQ, |
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99 | /* INTC# */ GRPCI_INTC_SYSIRQ, |
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100 | /* INTD# */ GRPCI_INTD_SYSIRQ |
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101 | }; |
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102 | |
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103 | /* Driver private data struture */ |
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104 | struct grpci_priv { |
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105 | struct drvmgr_dev *dev; |
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106 | struct grpci_regs *regs; |
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107 | int irq; |
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108 | int minor; |
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109 | |
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110 | uint32_t bar1_pci_adr; |
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111 | uint32_t bar1_size; |
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112 | |
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113 | int bt_enabled; |
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114 | unsigned int pci_area; |
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115 | unsigned int pci_area_end; |
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116 | unsigned int pci_io; |
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117 | unsigned int pci_conf; |
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118 | unsigned int pci_conf_end; |
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119 | |
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120 | uint32_t devVend; /* Host PCI Vendor/Device ID */ |
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121 | |
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122 | struct drvmgr_map_entry maps_up[2]; |
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123 | struct drvmgr_map_entry maps_down[2]; |
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124 | struct pcibus_config config; |
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125 | }; |
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126 | |
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127 | int grpci_init1(struct drvmgr_dev *dev); |
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128 | |
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129 | /* GRPCI DRIVER */ |
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130 | |
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131 | struct drvmgr_drv_ops grpci_ops = |
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132 | { |
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133 | .init = {grpci_init1, NULL, NULL, NULL}, |
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134 | .remove = NULL, |
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135 | .info = NULL |
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136 | }; |
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137 | |
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138 | struct amba_dev_id grpci_ids[] = |
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139 | { |
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140 | {VENDOR_GAISLER, GAISLER_PCIFBRG}, |
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141 | {0, 0} /* Mark end of table */ |
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142 | }; |
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143 | |
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144 | struct amba_drv_info grpci_info = |
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145 | { |
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146 | { |
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147 | DRVMGR_OBJ_DRV, /* Driver */ |
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148 | NULL, /* Next driver */ |
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149 | NULL, /* Device list */ |
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150 | DRIVER_AMBAPP_GAISLER_GRPCI_ID, /* Driver ID */ |
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151 | "GRPCI_DRV", /* Driver Name */ |
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152 | DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */ |
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153 | &grpci_ops, |
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154 | NULL, /* Funcs */ |
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155 | 0, /* No devices yet */ |
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156 | sizeof(struct grpci_priv), /* Make drvmgr alloc private */ |
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157 | }, |
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158 | &grpci_ids[0] |
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159 | }; |
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160 | |
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161 | void grpci_register_drv(void) |
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162 | { |
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163 | DBG("Registering GRPCI driver\n"); |
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164 | drvmgr_drv_register(&grpci_info.general); |
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165 | } |
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166 | |
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167 | static int grpci_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val) |
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168 | { |
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169 | struct grpci_priv *priv = grpcipriv; |
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170 | volatile uint32_t *pci_conf; |
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171 | uint32_t devfn; |
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172 | int retval; |
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173 | int bus = PCI_DEV_BUS(dev); |
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174 | |
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175 | if (ofs & 3) |
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176 | return PCISTS_EINVAL; |
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177 | |
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178 | if (PCI_DEV_SLOT(dev) > 15) { |
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179 | *val = 0xffffffff; |
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180 | return PCISTS_OK; |
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181 | } |
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182 | |
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183 | /* GRPCI can access "non-standard" devices on bus0 (on AD11.AD16), |
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184 | * but we skip them. |
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185 | */ |
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186 | if (dev == HOST_TGT) |
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187 | bus = devfn = 0; |
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188 | else if (bus == 0) |
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189 | devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0); |
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190 | else |
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191 | devfn = PCI_DEV_DEVFUNC(dev); |
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192 | |
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193 | /* Select bus */ |
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194 | priv->regs->cfg_stat = (priv->regs->cfg_stat & ~(0xf<<23)) | (bus<<23); |
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195 | |
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196 | pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs); |
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197 | |
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198 | if (priv->bt_enabled) { |
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199 | *val = CPU_swap_u32(*pci_conf); |
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200 | } else { |
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201 | *val = *pci_conf; |
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202 | } |
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203 | |
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204 | if (priv->regs->cfg_stat & 0x100) { |
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205 | *val = 0xffffffff; |
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206 | retval = PCISTS_MSTABRT; |
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207 | } else |
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208 | retval = PCISTS_OK; |
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209 | |
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210 | DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n", |
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211 | PCI_DEV_EXPAND(dev), ofs, pci_conf, *val); |
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212 | |
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213 | return retval; |
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214 | } |
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215 | |
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216 | |
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217 | static int grpci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val) |
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218 | { |
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219 | uint32_t v; |
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220 | int retval; |
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221 | |
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222 | if (ofs & 1) |
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223 | return PCISTS_EINVAL; |
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224 | |
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225 | retval = grpci_cfg_r32(dev, ofs & ~0x3, &v); |
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226 | *val = 0xffff & (v >> (8*(ofs & 0x3))); |
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227 | |
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228 | return retval; |
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229 | } |
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230 | |
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231 | static int grpci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val) |
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232 | { |
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233 | uint32_t v; |
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234 | int retval; |
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235 | |
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236 | retval = grpci_cfg_r32(dev, ofs & ~0x3, &v); |
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237 | |
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238 | *val = 0xff & (v >> (8*(ofs & 3))); |
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239 | |
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240 | return retval; |
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241 | } |
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242 | |
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243 | static int grpci_cfg_w32(pci_dev_t dev, int ofs, uint32_t val) |
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244 | { |
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245 | struct grpci_priv *priv = grpcipriv; |
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246 | volatile uint32_t *pci_conf; |
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247 | uint32_t value, devfn = PCI_DEV_DEVFUNC(dev); |
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248 | int bus = PCI_DEV_BUS(dev); |
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249 | |
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250 | if (ofs & 0x3) |
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251 | return PCISTS_EINVAL; |
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252 | |
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253 | if (PCI_DEV_SLOT(dev) > 15) |
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254 | return PCISTS_MSTABRT; |
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255 | |
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256 | /* GRPCI can access "non-standard" devices on bus0 (on AD11.AD16), |
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257 | * but we skip them. |
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258 | */ |
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259 | if (dev == HOST_TGT) |
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260 | bus = devfn = 0; |
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261 | else if (bus == 0) |
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262 | devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0); |
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263 | else |
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264 | devfn = PCI_DEV_DEVFUNC(dev); |
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265 | |
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266 | /* Select bus */ |
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267 | priv->regs->cfg_stat = (priv->regs->cfg_stat & ~(0xf<<23)) | (bus<<23); |
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268 | |
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269 | pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs); |
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270 | |
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271 | if ( priv->bt_enabled ) { |
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272 | value = CPU_swap_u32(val); |
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273 | } else { |
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274 | value = val; |
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275 | } |
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276 | |
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277 | *pci_conf = value; |
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278 | |
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279 | DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n", |
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280 | PCI_DEV_EXPAND(dev), ofs, pci_conf, value); |
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281 | |
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282 | return PCISTS_OK; |
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283 | } |
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284 | |
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285 | static int grpci_cfg_w16(pci_dev_t dev, int ofs, uint16_t val) |
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286 | { |
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287 | uint32_t v; |
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288 | int retval; |
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289 | |
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290 | if (ofs & 1) |
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291 | return PCISTS_EINVAL; |
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292 | |
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293 | retval = grpci_cfg_r32(dev, ofs & ~0x3, &v); |
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294 | if (retval != PCISTS_OK) |
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295 | return retval; |
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296 | |
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297 | v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3))); |
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298 | |
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299 | return grpci_cfg_w32(dev, ofs & ~0x3, v); |
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300 | } |
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301 | |
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302 | static int grpci_cfg_w8(pci_dev_t dev, int ofs, uint8_t val) |
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303 | { |
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304 | uint32_t v; |
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305 | int retval; |
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306 | |
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307 | retval = grpci_cfg_r32(dev, ofs & ~0x3, &v); |
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308 | if (retval != PCISTS_OK) |
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309 | return retval; |
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310 | |
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311 | v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3))); |
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312 | |
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313 | return grpci_cfg_w32(dev, ofs & ~0x3, v); |
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314 | } |
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315 | |
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316 | /* Return the assigned system IRQ number that corresponds to the PCI |
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317 | * "Interrupt Pin" information from configuration space. |
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318 | * |
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319 | * The IRQ information is stored in the grpci_pci_irq_table configurable |
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320 | * by the user. |
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321 | * |
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322 | * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns |
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323 | * 0xff if not assigned. |
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324 | */ |
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325 | static uint8_t grpci_bus0_irq_map(pci_dev_t dev, int irq_pin) |
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326 | { |
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327 | uint8_t sysIrqNr = 0; /* not assigned */ |
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328 | int irq_group; |
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329 | |
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330 | if ( (irq_pin >= 1) && (irq_pin <= 4) ) { |
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331 | /* Use default IRQ decoding on PCI BUS0 according slot numbering */ |
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332 | irq_group = PCI_DEV_SLOT(dev) & 0x3; |
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333 | irq_pin = ((irq_pin - 1) + irq_group) & 0x3; |
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334 | /* Valid PCI "Interrupt Pin" number */ |
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335 | sysIrqNr = grpci_pci_irq_table[irq_pin]; |
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336 | } |
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337 | return sysIrqNr; |
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338 | } |
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339 | |
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340 | static int grpci_translate(uint32_t *address, int type, int dir) |
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341 | { |
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342 | uint32_t adr; |
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343 | struct grpci_priv *priv = grpcipriv; |
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344 | |
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345 | if (type == 1) { |
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346 | /* I/O */ |
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347 | if (dir != 0) { |
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348 | /* The PCI bus can not access the CPU bus from I/O |
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349 | * because GRPCI core does not support I/O BARs |
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350 | */ |
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351 | return -1; |
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352 | } |
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353 | |
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354 | /* We have got a PCI BAR address that the CPU want to access... |
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355 | * Check that it is within the PCI I/O window, I/O adresses |
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356 | * are mapped 1:1 with GRPCI driver... no translation needed. |
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357 | */ |
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358 | adr = *(uint32_t *)address; |
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359 | if (adr < priv->pci_io || adr >= priv->pci_conf) |
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360 | return -1; |
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361 | } else { |
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362 | /* MEMIO and MEM. |
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363 | * Memory space is mapped 1:1 so no translation is needed. |
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364 | * Check that address is within accessible windows. |
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365 | */ |
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366 | adr = *(uint32_t *)address; |
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367 | if (dir == 0) { |
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368 | /* PCI BAR to AMBA-CPU address.. check that it is |
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369 | * located within GRPCI PCI Memory Window |
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370 | * adr = PCI address. |
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371 | */ |
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372 | if (adr < priv->pci_area || adr >= priv->pci_area_end) |
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373 | return -1; |
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374 | } else { |
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375 | /* We have a CPU address and want to get access to it |
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376 | * from PCI space, typically when doing DMA into CPU |
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377 | * RAM. The GRPCI core has two target BARs that PCI |
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378 | * masters can access, we check here that the address |
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379 | * is accessible from PCI. |
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380 | * adr = AMBA address. |
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381 | */ |
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382 | if (adr < priv->bar1_pci_adr || |
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383 | adr >= (priv->bar1_pci_adr + priv->bar1_size)) |
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384 | return -1; |
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385 | } |
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386 | } |
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387 | |
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388 | return 0; |
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389 | } |
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390 | |
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391 | extern struct pci_memreg_ops pci_memreg_sparc_le_ops; |
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392 | extern struct pci_memreg_ops pci_memreg_sparc_be_ops; |
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393 | |
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394 | /* GRPCI PCI access routines, default to Little-endian PCI Bus */ |
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395 | struct pci_access_drv grpci_access_drv = { |
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396 | .cfg = |
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397 | { |
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398 | grpci_cfg_r8, |
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399 | grpci_cfg_r16, |
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400 | grpci_cfg_r32, |
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401 | grpci_cfg_w8, |
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402 | grpci_cfg_w16, |
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403 | grpci_cfg_w32, |
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404 | }, |
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405 | .io = |
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406 | { |
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407 | _ld8, |
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408 | _ld_le16, |
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409 | _ld_le32, |
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410 | _st8, |
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411 | _st_le16, |
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412 | _st_le32, |
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413 | }, |
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414 | .memreg = &pci_memreg_sparc_le_ops, |
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415 | .translate = grpci_translate, |
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416 | }; |
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417 | |
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418 | struct pci_io_ops grpci_io_ops_be = |
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419 | { |
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420 | _ld8, |
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421 | _ld_be16, |
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422 | _ld_be32, |
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423 | _st8, |
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424 | _st_be16, |
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425 | _st_be32, |
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426 | }; |
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427 | |
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428 | static int grpci_hw_init(struct grpci_priv *priv) |
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429 | { |
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430 | volatile unsigned int *mbar0, *page0; |
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431 | uint32_t data, addr, mbar0size; |
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432 | pci_dev_t host = HOST_TGT; |
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433 | |
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434 | mbar0 = (volatile unsigned int *)priv->pci_area; |
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435 | |
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436 | if ( !priv->bt_enabled && ((priv->regs->page0 & PAGE0_BTEN) == PAGE0_BTEN) ) { |
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437 | /* Byte twisting is on, turn it off */ |
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438 | grpci_cfg_w32(host, PCIR_BAR(0), 0xffffffff); |
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439 | grpci_cfg_r32(host, PCIR_BAR(0), &addr); |
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440 | /* Setup bar0 to nonzero value */ |
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441 | grpci_cfg_w32(host, PCIR_BAR(0), |
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442 | CPU_swap_u32(0x80000000)); |
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443 | /* page0 is accessed through upper half of bar0 */ |
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444 | addr = (~CPU_swap_u32(addr)+1)>>1; |
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445 | mbar0size = addr*2; |
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446 | DBG("GRPCI: Size of MBAR0: 0x%x, MBAR0: 0x%x(lower) 0x%x(upper)\n",mbar0size,((unsigned int)mbar0),((unsigned int)mbar0)+mbar0size/2); |
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447 | page0 = &mbar0[mbar0size/8]; |
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448 | DBG("GRPCI: PAGE0 reg address: 0x%x (0x%x)\n",((unsigned int)mbar0)+mbar0size/2,page0); |
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449 | priv->regs->cfg_stat = (priv->regs->cfg_stat & (~0xf0000000)) | 0x80000000; /* Setup mmap reg so we can reach bar0 */ |
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450 | *page0 = 0<<PAGE0_BTEN_BIT; /* Disable bytetwisting ... */ |
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451 | } |
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452 | |
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453 | /* Get the GRPCI Host PCI ID */ |
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454 | grpci_cfg_r32(host, PCIR_VENDOR, &priv->devVend); |
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455 | |
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456 | /* set 1:1 mapping between AHB -> PCI memory */ |
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457 | priv->regs->cfg_stat = (priv->regs->cfg_stat & 0x0fffffff) | priv->pci_area; |
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458 | |
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459 | /* determine size of target BAR1 */ |
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460 | grpci_cfg_w32(host, PCIR_BAR(1), 0xffffffff); |
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461 | grpci_cfg_r32(host, PCIR_BAR(1), &addr); |
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462 | priv->bar1_size = (~(addr & ~0xf)) + 1; |
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463 | |
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464 | /* and map system RAM at pci address 0x40000000 */ |
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465 | priv->bar1_pci_adr &= ~(priv->bar1_size - 1); /* Fix alignment of BAR1 */ |
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466 | grpci_cfg_w32(host, PCIR_BAR(1), priv->bar1_pci_adr); |
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467 | priv->regs->page1 = priv->bar1_pci_adr; |
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468 | |
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469 | /* Translate I/O accesses 1:1 */ |
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470 | priv->regs->iomap = priv->pci_io & 0xffff0000; |
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471 | |
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472 | /* Setup Latency Timer and cache line size. Default cache line |
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473 | * size will result in poor performance (256 word fetches), 0xff |
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474 | * will set it according to the max size of the PCI FIFO. |
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475 | */ |
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476 | grpci_cfg_w8(host, PCIR_CACHELNSZ, 0xff); |
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477 | grpci_cfg_w8(host, PCIR_LATTIMER, 0x40); |
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478 | |
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479 | /* set as bus master and enable pci memory responses */ |
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480 | grpci_cfg_r32(host, PCIR_COMMAND, &data); |
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481 | data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); |
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482 | grpci_cfg_w32(host, PCIR_COMMAND, data); |
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483 | |
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484 | /* unmask all PCI interrupts at PCI Core, not all GRPCI cores support |
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485 | * this |
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486 | */ |
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487 | priv->regs->irq = 0xf0000; |
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488 | |
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489 | /* Successful */ |
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490 | return 0; |
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491 | } |
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492 | |
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493 | /* Initializes the GRPCI core and driver, must be called before calling init_pci() |
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494 | * |
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495 | * Return values |
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496 | * 0 Successful initalization |
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497 | * -1 Error during initialization, for example "PCI core not found". |
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498 | * -2 Error PCI controller not HOST (targets not supported) |
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499 | * -3 Error due to GRPCI hardware initialization |
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500 | * -4 Error registering driver to PCI layer |
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501 | */ |
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502 | static int grpci_init(struct grpci_priv *priv) |
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503 | { |
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504 | struct ambapp_apb_info *apb; |
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505 | struct ambapp_ahb_info *ahb; |
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506 | int pin; |
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507 | union drvmgr_key_value *value; |
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508 | char keyname[6]; |
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509 | struct amba_dev_info *ainfo = priv->dev->businfo; |
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510 | |
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511 | /* Find PCI core from Plug&Play information */ |
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512 | apb = ainfo->info.apb_slv; |
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513 | ahb = ainfo->info.ahb_slv; |
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514 | |
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515 | /* Found PCI core, init private structure */ |
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516 | priv->irq = apb->irq; |
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517 | priv->regs = (struct grpci_regs *)apb->start; |
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518 | priv->bt_enabled = DEFAULT_BT_ENABLED; |
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519 | |
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520 | /* Calculate the PCI windows |
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521 | * AMBA->PCI Window: AHB SLAVE AREA0 |
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522 | * AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half |
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523 | * AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half |
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524 | */ |
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525 | priv->pci_area = ahb->start[0]; |
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526 | priv->pci_area_end = ahb->start[0] + ahb->mask[0]; |
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527 | priv->pci_io = ahb->start[1]; |
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528 | priv->pci_conf = ahb->start[1] + (ahb->mask[1] >> 1); |
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529 | priv->pci_conf_end = ahb->start[1] + ahb->mask[1]; |
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530 | |
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531 | /* On systems where PCI I/O area and configuration area is apart of the "PCI Window" |
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532 | * the PCI Window stops at the start of the PCI I/O area |
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533 | */ |
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534 | if ( (priv->pci_io > priv->pci_area) && (priv->pci_io < (priv->pci_area_end-1)) ) { |
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535 | priv->pci_area_end = priv->pci_io; |
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536 | } |
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537 | |
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538 | /* Init PCI interrupt assignment table to all use the interrupt routed through |
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539 | * the GRPCI core. |
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540 | */ |
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541 | strcpy(keyname, "INTX#"); |
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542 | for (pin=1; pin<5; pin++) { |
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543 | if ( grpci_pci_irq_table[pin-1] == 0xff ) { |
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544 | grpci_pci_irq_table[pin-1] = priv->irq; |
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545 | |
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546 | /* User may override Both hardcoded IRQ setup and Plug & Play IRQ */ |
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547 | keyname[3] = 'A' + (pin-1); |
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548 | value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT); |
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549 | if ( value ) |
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550 | grpci_pci_irq_table[pin-1] = value->i; |
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551 | } |
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552 | } |
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553 | |
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554 | /* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */ |
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555 | value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT); |
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556 | if ( value ) |
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557 | priv->bt_enabled = value->i; |
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558 | |
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559 | /* Use GRPCI target BAR1 to map CPU RAM to PCI, this is to make it |
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560 | * possible for PCI peripherals to do DMA directly to CPU memory. |
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561 | */ |
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562 | value = drvmgr_dev_key_get(priv->dev, "tgtbar1", DRVMGR_KT_INT); |
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563 | if (value) |
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564 | priv->bar1_pci_adr = value->i; |
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565 | else |
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566 | priv->bar1_pci_adr = SYSTEM_MAINMEM_START; /* default */ |
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567 | |
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568 | /* This driver only support HOST systems, we check for HOST */ |
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569 | if ( !(priv->regs->cfg_stat & CFGSTAT_HOST) ) { |
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570 | /* Target not supported */ |
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571 | return -2; |
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572 | } |
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573 | |
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574 | /* Init the PCI Core */ |
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575 | if ( grpci_hw_init(priv) ) { |
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576 | return -3; |
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577 | } |
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578 | |
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579 | /* Down streams translation table */ |
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580 | priv->maps_down[0].name = "AMBA -> PCI MEM Window"; |
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581 | priv->maps_down[0].size = priv->pci_area_end - priv->pci_area; |
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582 | priv->maps_down[0].from_adr = (void *)priv->pci_area; |
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583 | priv->maps_down[0].to_adr = (void *)priv->pci_area; |
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584 | /* End table */ |
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585 | priv->maps_down[1].size = 0; |
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586 | |
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587 | /* Up streams translation table */ |
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588 | priv->maps_up[0].name = "Target BAR1 -> AMBA"; |
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589 | priv->maps_up[0].size = priv->bar1_size; |
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590 | priv->maps_up[0].from_adr = (void *)priv->bar1_pci_adr; |
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591 | priv->maps_up[0].to_adr = (void *)priv->bar1_pci_adr; |
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592 | /* End table */ |
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593 | priv->maps_up[1].size = 0; |
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594 | |
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595 | return 0; |
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596 | } |
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597 | |
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598 | /* Called when a core is found with the AMBA device and vendor ID |
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599 | * given in grpci_ids[]. IRQ, Console does not work here |
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600 | */ |
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601 | int grpci_init1(struct drvmgr_dev *dev) |
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602 | { |
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603 | int status; |
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604 | struct grpci_priv *priv; |
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605 | struct pci_auto_setup grpci_auto_cfg; |
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606 | |
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607 | DBG("GRPCI[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name); |
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608 | |
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609 | if ( grpci_minor != 0 ) { |
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610 | DBG("Driver only supports one PCI core\n"); |
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611 | return DRVMGR_FAIL; |
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612 | } |
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613 | |
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614 | if ( (strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) && |
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615 | (strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0) ) { |
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616 | /* We only support GRPCI driver on local bus */ |
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617 | return DRVMGR_FAIL; |
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618 | } |
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619 | |
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620 | priv = dev->priv; |
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621 | if ( !priv ) |
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622 | return DRVMGR_NOMEM; |
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623 | |
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624 | priv->dev = dev; |
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625 | priv->minor = grpci_minor++; |
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626 | |
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627 | grpcipriv = priv; |
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628 | status = grpci_init(priv); |
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629 | if (status) { |
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630 | printk("Failed to initialize grpci driver %d\n", status); |
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631 | return DRVMGR_FAIL; |
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632 | } |
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633 | |
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634 | |
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635 | /* Register the PCI core at the PCI layers */ |
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636 | |
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637 | if (priv->bt_enabled == 0) { |
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638 | /* Host is Big-Endian */ |
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639 | pci_endian = PCI_BIG_ENDIAN; |
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640 | |
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641 | memcpy(&grpci_access_drv.io, &grpci_io_ops_be, |
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642 | sizeof(grpci_io_ops_be)); |
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643 | grpci_access_drv.memreg = &pci_memreg_sparc_be_ops; |
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644 | } |
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645 | |
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646 | if (pci_access_drv_register(&grpci_access_drv)) { |
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647 | /* Access routines registration failed */ |
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648 | return DRVMGR_FAIL; |
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649 | } |
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650 | |
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651 | /* Prepare memory MAP */ |
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652 | grpci_auto_cfg.options = 0; |
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653 | grpci_auto_cfg.mem_start = 0; |
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654 | grpci_auto_cfg.mem_size = 0; |
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655 | grpci_auto_cfg.memio_start = priv->pci_area; |
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656 | grpci_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area; |
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657 | grpci_auto_cfg.io_start = priv->pci_io; |
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658 | grpci_auto_cfg.io_size = priv->pci_conf - priv->pci_io; |
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659 | grpci_auto_cfg.irq_map = grpci_bus0_irq_map; |
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660 | grpci_auto_cfg.irq_route = NULL; /* use standard routing */ |
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661 | pci_config_register(&grpci_auto_cfg); |
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662 | |
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663 | if (pci_config_init()) { |
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664 | /* PCI configuration failed */ |
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665 | return DRVMGR_FAIL; |
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666 | } |
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667 | |
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668 | priv->config.maps_down = &priv->maps_down[0]; |
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669 | priv->config.maps_up = &priv->maps_up[0]; |
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670 | return pcibus_register(dev, &priv->config); |
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671 | } |
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672 | |
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673 | /* DMA functions which uses GRPCIs optional DMA controller (len in words) */ |
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674 | int grpci_dma_to_pci( |
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675 | unsigned int ahb_addr, |
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676 | unsigned int pci_addr, |
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677 | unsigned int len) |
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678 | { |
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679 | int ret = 0; |
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680 | |
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681 | pcidma[0] = 0x82; |
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682 | pcidma[1] = ahb_addr; |
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683 | pcidma[2] = pci_addr; |
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684 | pcidma[3] = len; |
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685 | pcidma[0] = 0x83; |
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686 | |
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687 | while ( (pcidma[0] & 0x4) == 0) |
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688 | ; |
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689 | |
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690 | if (pcidma[0] & 0x8) { /* error */ |
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691 | ret = -1; |
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692 | } |
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693 | |
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694 | pcidma[0] |= 0xC; |
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695 | return ret; |
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696 | |
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697 | } |
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698 | |
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699 | int grpci_dma_from_pci( |
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700 | unsigned int ahb_addr, |
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701 | unsigned int pci_addr, |
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702 | unsigned int len) |
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703 | { |
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704 | int ret = 0; |
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705 | |
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706 | pcidma[0] = 0x80; |
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707 | pcidma[1] = ahb_addr; |
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708 | pcidma[2] = pci_addr; |
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709 | pcidma[3] = len; |
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710 | pcidma[0] = 0x81; |
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711 | |
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712 | while ( (pcidma[0] & 0x4) == 0) |
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713 | ; |
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714 | |
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715 | if (pcidma[0] & 0x8) { /* error */ |
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716 | ret = -1; |
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717 | } |
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718 | |
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719 | pcidma[0] |= 0xC; |
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720 | return ret; |
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721 | |
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722 | } |
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