1 | /* GR-RASTA-ADCDAC PCI Target driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2008. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * Configures the GR-RASTA-ADCDAC interface PCI board. |
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7 | * This driver provides a AMBA PnP bus by using the general part |
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8 | * of the AMBA PnP bus driver (ambapp_bus.c). |
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9 | * |
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10 | * Driver resources for the AMBA PnP bus provided can be set using |
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11 | * gr_rasta_adcdac_set_resources(). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.org/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #include <stdio.h> |
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19 | #include <stdlib.h> |
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20 | #include <string.h> |
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21 | #include <sys/types.h> |
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22 | #include <sys/stat.h> |
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23 | |
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24 | #include <bsp.h> |
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25 | #include <rtems/bspIo.h> |
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26 | #include <pci.h> |
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27 | |
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28 | #include <ambapp.h> |
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29 | #include <grlib.h> |
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30 | #include <drvmgr/drvmgr.h> |
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31 | #include <drvmgr/ambapp_bus.h> |
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32 | #include <drvmgr/pci_bus.h> |
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33 | #include <drvmgr/bspcommon.h> |
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34 | #include <bsp/genirq.h> |
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35 | |
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36 | #include <bsp/gr_rasta_adcdac.h> |
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37 | |
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38 | #include <grlib_impl.h> |
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39 | |
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40 | /*#define DEBUG 1*/ |
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41 | |
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42 | #ifdef DEBUG |
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43 | #define DBG(x...) printk(x) |
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44 | #else |
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45 | #define DBG(x...) |
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46 | #endif |
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47 | |
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48 | /* Determines which PCI address the AHB masters will access, it should be |
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49 | * set so that the masters can access the CPU RAM. Default is base of CPU RAM, |
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50 | * CPU RAM is mapped 1:1 to PCI space. |
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51 | */ |
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52 | extern unsigned int _RAM_START; |
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53 | #define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000) |
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54 | |
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55 | /* PCI ID */ |
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56 | #define PCIID_VENDOR_GAISLER 0x1AC8 |
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57 | #define PCIID_DEVICE_GR_RASTA_ADCDAC 0x0014 |
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58 | |
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59 | int gr_rasta_adcdac_init1(struct drvmgr_dev *dev); |
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60 | int gr_rasta_adcdac_init2(struct drvmgr_dev *dev); |
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61 | void gr_rasta_adcdac_isr (void *arg); |
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62 | |
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63 | struct grpci_regs { |
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64 | volatile unsigned int cfg_stat; |
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65 | volatile unsigned int bar0; |
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66 | volatile unsigned int page0; |
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67 | volatile unsigned int bar1; |
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68 | volatile unsigned int page1; |
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69 | volatile unsigned int iomap; |
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70 | volatile unsigned int stat_cmd; |
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71 | }; |
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72 | |
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73 | struct gr_rasta_adcdac_ver { |
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74 | const unsigned int amba_freq_hz; /* The frequency */ |
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75 | const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */ |
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76 | }; |
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77 | |
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78 | /* Private data structure for driver */ |
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79 | struct gr_rasta_adcdac_priv { |
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80 | /* Driver management */ |
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81 | struct drvmgr_dev *dev; |
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82 | char prefix[20]; |
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83 | SPIN_DECLARE(devlock); |
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84 | |
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85 | /* PCI */ |
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86 | pci_dev_t pcidev; |
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87 | struct pci_dev_info *devinfo; |
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88 | uint32_t ahbmst2pci_map; |
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89 | |
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90 | /* IRQ */ |
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91 | genirq_t genirq; |
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92 | |
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93 | /* GR-RASTA-ADCDAC */ |
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94 | struct gr_rasta_adcdac_ver *version; |
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95 | struct irqmp_regs *irq; |
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96 | struct grpci_regs *grpci; |
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97 | struct drvmgr_map_entry bus_maps_down[3]; |
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98 | struct drvmgr_map_entry bus_maps_up[2]; |
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99 | |
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100 | /* AMBA Plug&Play information on GR-RASTA-ADCDAC */ |
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101 | struct ambapp_bus abus; |
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102 | struct ambapp_mmap amba_maps[4]; |
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103 | struct ambapp_config config; |
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104 | }; |
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105 | |
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106 | struct gr_rasta_adcdac_ver gr_rasta_adcdac_ver0 = { |
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107 | .amba_freq_hz = 50000000, |
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108 | .amba_ioarea = 0x80100000, |
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109 | }; |
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110 | |
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111 | int ambapp_rasta_adcdac_int_register( |
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112 | struct drvmgr_dev *dev, |
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113 | int irq, |
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114 | const char *info, |
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115 | drvmgr_isr handler, |
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116 | void *arg); |
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117 | int ambapp_rasta_adcdac_int_unregister( |
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118 | struct drvmgr_dev *dev, |
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119 | int irq, |
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120 | drvmgr_isr isr, |
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121 | void *arg); |
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122 | int ambapp_rasta_adcdac_int_unmask( |
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123 | struct drvmgr_dev *dev, |
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124 | int irq); |
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125 | int ambapp_rasta_adcdac_int_mask( |
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126 | struct drvmgr_dev *dev, |
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127 | int irq); |
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128 | int ambapp_rasta_adcdac_int_clear( |
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129 | struct drvmgr_dev *dev, |
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130 | int irq); |
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131 | int ambapp_rasta_adcdac_get_params( |
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132 | struct drvmgr_dev *dev, |
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133 | struct drvmgr_bus_params *params); |
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134 | |
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135 | struct ambapp_ops ambapp_rasta_adcdac_ops = { |
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136 | .int_register = ambapp_rasta_adcdac_int_register, |
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137 | .int_unregister = ambapp_rasta_adcdac_int_unregister, |
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138 | .int_unmask = ambapp_rasta_adcdac_int_unmask, |
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139 | .int_mask = ambapp_rasta_adcdac_int_mask, |
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140 | .int_clear = ambapp_rasta_adcdac_int_clear, |
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141 | .get_params = ambapp_rasta_adcdac_get_params |
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142 | }; |
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143 | |
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144 | struct drvmgr_drv_ops gr_rasta_adcdac_ops = |
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145 | { .init = {gr_rasta_adcdac_init1, gr_rasta_adcdac_init2, NULL, NULL}, |
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146 | .remove = NULL, |
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147 | .info = NULL |
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148 | }; |
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149 | |
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150 | struct pci_dev_id_match gr_rasta_adcdac_ids[] = |
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151 | { |
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152 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC), |
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153 | PCIID_END_TABLE /* Mark end of table */ |
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154 | }; |
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155 | |
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156 | struct pci_drv_info gr_rasta_adcdac_info = |
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157 | { |
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158 | { |
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159 | DRVMGR_OBJ_DRV, /* Driver */ |
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160 | NULL, /* Next driver */ |
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161 | NULL, /* Device list */ |
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162 | DRIVER_PCI_GAISLER_RASTAADCDAC_ID,/* Driver ID */ |
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163 | "GR-RASTA-ADCDAC_DRV", /* Driver Name */ |
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164 | DRVMGR_BUS_TYPE_PCI, /* Bus Type */ |
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165 | &gr_rasta_adcdac_ops, |
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166 | NULL, /* Funcs */ |
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167 | 0, /* No devices yet */ |
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168 | 0, |
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169 | }, |
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170 | &gr_rasta_adcdac_ids[0] |
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171 | }; |
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172 | |
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173 | /* Driver resources configuration for the AMBA bus on the GR-RASTA-ADCDAC board. |
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174 | * It is declared weak so that the user may override it from the project file, |
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175 | * if the default settings are not enough. |
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176 | * |
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177 | * The configuration consists of an array of configuration pointers, each |
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178 | * pointer determine the configuration of one GR-RASTA-ADCDAC board. Pointer |
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179 | * zero is for board0, pointer 1 for board1 and so on. |
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180 | * |
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181 | * The array must end with a NULL pointer. |
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182 | */ |
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183 | struct drvmgr_bus_res *gr_rasta_adcdac_resources[] __attribute__((weak)) = |
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184 | { |
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185 | NULL |
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186 | }; |
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187 | |
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188 | void gr_rasta_adcdac_register_drv(void) |
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189 | { |
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190 | DBG("Registering GR-RASTA-ADCDAC PCI driver\n"); |
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191 | drvmgr_drv_register(&gr_rasta_adcdac_info.general); |
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192 | } |
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193 | |
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194 | void gr_rasta_adcdac_isr (void *arg) |
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195 | { |
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196 | struct gr_rasta_adcdac_priv *priv = arg; |
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197 | unsigned int status, tmp; |
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198 | int irq; |
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199 | SPIN_ISR_IRQFLAGS(irqflags); |
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200 | |
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201 | tmp = status = priv->irq->ipend; |
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202 | |
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203 | /* DBG("GR-RASTA-ADCDAC: IRQ 0x%x\n",status); */ |
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204 | |
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205 | SPIN_LOCK(&priv->devlock, irqflags); |
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206 | for(irq=0; irq<16; irq++) { |
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207 | if ( status & (1<<irq) ) { |
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208 | genirq_doirq(priv->genirq, irq); |
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209 | priv->irq->iclear = (1<<irq); |
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210 | status &= ~(1<<irq); |
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211 | if ( status == 0 ) |
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212 | break; |
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213 | } |
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214 | } |
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215 | SPIN_UNLOCK(&priv->devlock, irqflags); |
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216 | |
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217 | /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */ |
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218 | if ( tmp ) |
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219 | drvmgr_interrupt_clear(priv->dev, 0); |
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220 | |
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221 | DBG("RASTA-ADCDAC-IRQ: 0x%x\n", tmp); |
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222 | } |
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223 | |
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224 | static int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv) |
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225 | { |
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226 | uint32_t data; |
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227 | unsigned int *page0 = NULL; |
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228 | struct ambapp_dev *tmp; |
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229 | struct ambapp_ahb_info *ahb; |
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230 | struct pci_dev_info *devinfo = priv->devinfo; |
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231 | uint32_t bar0, bar0_size; |
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232 | |
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233 | /* Select version of GR-RASTA-ADCDAC board */ |
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234 | switch (devinfo->rev) { |
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235 | case 0: |
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236 | priv->version = &gr_rasta_adcdac_ver0; |
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237 | break; |
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238 | default: |
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239 | return -2; |
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240 | } |
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241 | |
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242 | bar0 = devinfo->resources[0].address; |
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243 | bar0_size = devinfo->resources[0].size; |
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244 | page0 = (unsigned int *)(bar0 + bar0_size/2); |
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245 | |
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246 | /* Point PAGE0 to start of Plug and Play information */ |
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247 | *page0 = priv->version->amba_ioarea & 0xf0000000; |
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248 | |
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249 | /* set parity error response */ |
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250 | pci_cfg_r32(priv->pcidev, PCIR_COMMAND, &data); |
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251 | pci_cfg_w32(priv->pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN)); |
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252 | |
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253 | /* Setup cache line size. Default cache line size will result in |
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254 | * poor performance (256 word fetches), 0xff will set it according |
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255 | * to the max size of the PCI FIFO. |
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256 | */ |
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257 | pci_cfg_w8(priv->pcidev, PCIR_CACHELNSZ, 0xff); |
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258 | |
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259 | /* Scan AMBA Plug&Play */ |
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260 | |
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261 | /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ |
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262 | priv->amba_maps[0].size = bar0_size/2; |
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263 | priv->amba_maps[0].local_adr = bar0; |
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264 | priv->amba_maps[0].remote_adr = 0x80000000; |
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265 | |
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266 | /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */ |
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267 | priv->amba_maps[1].size = devinfo->resources[1].size; |
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268 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
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269 | priv->amba_maps[1].remote_adr = 0x40000000; |
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270 | |
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271 | /* Addresses not matching with map be untouched */ |
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272 | priv->amba_maps[2].size = 0xfffffff0; |
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273 | priv->amba_maps[2].local_adr = 0; |
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274 | priv->amba_maps[2].remote_adr = 0; |
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275 | |
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276 | /* Mark end of table */ |
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277 | priv->amba_maps[3].size=0; |
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278 | priv->amba_maps[3].local_adr = 0; |
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279 | priv->amba_maps[3].remote_adr = 0; |
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280 | |
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281 | /* Start AMBA PnP scan at first AHB bus */ |
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282 | /*ambapp_scan(priv->bar0 + (priv->version->amba_ioarea & ~0xf0000000), |
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283 | NULL, &priv->amba_maps[0], NULL, &priv->abus.root, NULL);*/ |
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284 | ambapp_scan(&priv->abus, |
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285 | bar0 + (priv->version->amba_ioarea & ~0xf0000000), |
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286 | NULL, &priv->amba_maps[0]); |
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287 | |
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288 | /* Initialize Frequency of AMBA bus */ |
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289 | ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz); |
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290 | |
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291 | /* Point PAGE0 to start of APB area */ |
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292 | *page0 = 0x80000000; |
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293 | |
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294 | /* Find GRPCI controller */ |
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295 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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296 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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297 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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298 | ambapp_find_by_idx, NULL); |
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299 | if ( !tmp ) { |
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300 | return -3; |
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301 | } |
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302 | priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start; |
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303 | |
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304 | /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over |
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305 | * the PCI window. |
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306 | */ |
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307 | priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) | |
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308 | (priv->ahbmst2pci_map & 0xf0000000); |
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309 | priv->grpci->page1 = 0x40000000; |
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310 | |
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311 | /* Find IRQ controller */ |
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312 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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313 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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314 | VENDOR_GAISLER, GAISLER_IRQMP, |
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315 | ambapp_find_by_idx, NULL); |
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316 | if ( !tmp ) { |
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317 | return -4; |
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318 | } |
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319 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
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320 | /* Set up GR-RASTA-ADCDAC irq controller */ |
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321 | priv->irq->iclear = 0xffff; |
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322 | priv->irq->ilevel = 0; |
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323 | priv->irq->mask[0] = 0; |
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324 | |
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325 | /* DOWN streams translation table */ |
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326 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
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327 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
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328 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
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329 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
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330 | |
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331 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
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332 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
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333 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
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334 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
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335 | |
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336 | /* Mark end of translation table */ |
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337 | priv->bus_maps_down[2].size = 0; |
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338 | |
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339 | /* Find GRPCI controller AHB Slave interface */ |
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340 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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341 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
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342 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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343 | ambapp_find_by_idx, NULL); |
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344 | if ( !tmp ) { |
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345 | return -5; |
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346 | } |
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347 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
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348 | |
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349 | /* UP streams translation table */ |
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350 | priv->bus_maps_up[0].name = "AMBA GRPCI Window"; |
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351 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-ADCDAC board */ |
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352 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
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353 | priv->bus_maps_up[0].to_adr = (void *) |
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354 | (priv->ahbmst2pci_map & 0xf0000000); |
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355 | |
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356 | /* Mark end of translation table */ |
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357 | priv->bus_maps_up[1].size = 0; |
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358 | |
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359 | /* Successfully registered the RASTA board */ |
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360 | return 0; |
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361 | } |
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362 | |
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363 | static int gr_rasta_adcdac_hw_init2(struct gr_rasta_adcdac_priv *priv) |
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364 | { |
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365 | /* Enable DMA by enabling PCI target as master */ |
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366 | pci_master_enable(priv->pcidev); |
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367 | |
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368 | return DRVMGR_OK; |
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369 | } |
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370 | |
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371 | /* Called when a PCI target is found with the PCI device and vendor ID |
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372 | * given in gr_rasta_adcdac_ids[]. |
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373 | */ |
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374 | int gr_rasta_adcdac_init1(struct drvmgr_dev *dev) |
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375 | { |
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376 | struct gr_rasta_adcdac_priv *priv; |
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377 | struct pci_dev_info *devinfo; |
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378 | int status; |
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379 | uint32_t bar0, bar1, bar0_size, bar1_size; |
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380 | union drvmgr_key_value *value; |
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381 | int resources_cnt; |
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382 | |
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383 | priv = malloc(sizeof(struct gr_rasta_adcdac_priv)); |
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384 | if ( !priv ) |
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385 | return DRVMGR_NOMEM; |
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386 | |
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387 | memset(priv, 0, sizeof(*priv)); |
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388 | dev->priv = priv; |
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389 | priv->dev = dev; |
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390 | |
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391 | /* Determine number of configurations */ |
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392 | resources_cnt = get_resarray_count(gr_rasta_adcdac_resources); |
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393 | |
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394 | /* Generate Device prefix */ |
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395 | |
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396 | strcpy(priv->prefix, "/dev/rastaadcdac0"); |
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397 | priv->prefix[16] += dev->minor_drv; |
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398 | mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO); |
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399 | priv->prefix[17] = '/'; |
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400 | priv->prefix[18] = '\0'; |
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401 | |
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402 | priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo; |
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403 | priv->pcidev = devinfo->pcidev; |
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404 | bar0 = devinfo->resources[0].address; |
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405 | bar0_size = devinfo->resources[0].size; |
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406 | bar1 = devinfo->resources[1].address; |
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407 | bar1_size = devinfo->resources[1].size; |
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408 | printk("\n\n--- GR-RASTA-ADCDAC[%d] ---\n", dev->minor_drv); |
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409 | printk(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n", |
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410 | PCI_DEV_EXPAND(priv->pcidev)); |
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411 | printk(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n", |
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412 | devinfo->id.vendor, devinfo->id.device); |
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413 | printk(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
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414 | printk(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
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415 | printk(" IRQ: %d\n\n\n", devinfo->irq); |
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416 | |
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417 | /* all neccessary space assigned to GR-RASTA-ADCDAC target? */ |
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418 | if ((bar0_size == 0) || (bar1_size == 0)) |
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419 | return DRVMGR_ENORES; |
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420 | |
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421 | /* Initialize spin-lock for this PCI perihperal device. This is to |
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422 | * protect the Interrupt Controller Registers. The genirq layer is |
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423 | * protecting its own internals and ISR dispatching. |
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424 | */ |
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425 | SPIN_INIT(&priv->devlock, priv->prefix); |
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426 | |
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427 | /* Let user override which PCI address the AHB masters of the |
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428 | * RASTA-ADCDAC board access when doing DMA to CPU RAM. The AHB masters |
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429 | * access the PCI Window of the AMBA bus, the MSB 4-bits of that address |
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430 | * is translated according this config option before the address |
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431 | * goes out on the PCI bus. |
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432 | * Only the 4 MSB bits have an effect; |
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433 | */ |
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434 | value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", DRVMGR_KT_INT); |
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435 | if (value) |
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436 | priv->ahbmst2pci_map = value->i; |
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437 | else |
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438 | priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */ |
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439 | |
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440 | priv->genirq = genirq_init(16); |
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441 | if ( priv->genirq == NULL ) { |
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442 | free(priv); |
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443 | dev->priv = NULL; |
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444 | return DRVMGR_FAIL; |
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445 | } |
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446 | |
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447 | if ( (status = gr_rasta_adcdac_hw_init1(priv)) != 0 ) { |
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448 | genirq_destroy(priv->genirq); |
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449 | free(priv); |
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450 | dev->priv = NULL; |
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451 | printk(" Failed to initialize GR-RASTA-ADCDAC HW: %d\n", status); |
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452 | return DRVMGR_FAIL; |
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453 | } |
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454 | |
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455 | /* Init amba bus */ |
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456 | priv->config.abus = &priv->abus; |
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457 | priv->config.ops = &ambapp_rasta_adcdac_ops; |
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458 | priv->config.maps_up = &priv->bus_maps_up[0]; |
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459 | priv->config.maps_down = &priv->bus_maps_down[0]; |
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460 | if ( priv->dev->minor_drv < resources_cnt ) { |
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461 | priv->config.resources = gr_rasta_adcdac_resources[priv->dev->minor_drv]; |
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462 | } else { |
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463 | priv->config.resources = NULL; |
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464 | } |
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465 | |
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466 | /* Create and register AMBA PnP bus. */ |
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467 | return ambapp_bus_register(dev, &priv->config); |
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468 | } |
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469 | |
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470 | int gr_rasta_adcdac_init2(struct drvmgr_dev *dev) |
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471 | { |
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472 | struct gr_rasta_adcdac_priv *priv = dev->priv; |
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473 | |
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474 | /* Clear any old interrupt requests */ |
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475 | drvmgr_interrupt_clear(dev, 0); |
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476 | |
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477 | /* Enable System IRQ so that GR-RASTA-ADCDAC PCI target interrupt |
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478 | * goes through. |
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479 | * |
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480 | * It is important to enable it in stage init2. If interrupts were |
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481 | * enabled in init1 this might hang the system when more than one |
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482 | * PCI board is connected, this is because PCI interrupts might |
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483 | * be shared and PCI board 2 have not initialized and might |
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484 | * therefore drive interrupt already when entering init1(). |
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485 | */ |
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486 | drvmgr_interrupt_register( |
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487 | dev, |
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488 | 0, |
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489 | "gr_rasta_adcdac", |
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490 | gr_rasta_adcdac_isr, |
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491 | (void *)priv); |
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492 | |
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493 | return gr_rasta_adcdac_hw_init2(priv); |
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494 | } |
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495 | |
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496 | int ambapp_rasta_adcdac_int_register( |
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497 | struct drvmgr_dev *dev, |
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498 | int irq, |
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499 | const char *info, |
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500 | drvmgr_isr handler, |
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501 | void *arg) |
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502 | { |
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503 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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504 | SPIN_IRQFLAGS(irqflags); |
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505 | int status; |
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506 | void *h; |
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507 | |
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508 | h = genirq_alloc_handler(handler, arg); |
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509 | if ( h == NULL ) |
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510 | return DRVMGR_FAIL; |
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511 | |
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512 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
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513 | |
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514 | status = genirq_register(priv->genirq, irq, h); |
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515 | if ( status == 0 ) { |
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516 | /* Clear IRQ for first registered handler */ |
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517 | priv->irq->iclear = (1<<irq); |
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518 | } else if ( status == 1 ) |
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519 | status = 0; |
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520 | |
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521 | if (status != 0) { |
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522 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
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523 | genirq_free_handler(h); |
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524 | return DRVMGR_FAIL; |
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525 | } |
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526 | |
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527 | status = genirq_enable(priv->genirq, irq, handler, arg); |
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528 | if ( status == 0 ) { |
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529 | /* Enable IRQ for first enabled handler only */ |
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530 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
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531 | } else if ( status == 1 ) |
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532 | status = 0; |
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533 | |
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534 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
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535 | |
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536 | return status; |
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537 | } |
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538 | |
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539 | int ambapp_rasta_adcdac_int_unregister( |
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540 | struct drvmgr_dev *dev, |
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541 | int irq, |
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542 | drvmgr_isr isr, |
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543 | void *arg) |
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544 | { |
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545 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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546 | SPIN_IRQFLAGS(irqflags); |
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547 | int status; |
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548 | void *handler; |
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549 | |
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550 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
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551 | |
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552 | status = genirq_disable(priv->genirq, irq, isr, arg); |
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553 | if ( status == 0 ) { |
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554 | /* Disable IRQ only when no enabled handler exists */ |
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555 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
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556 | } |
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557 | |
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558 | handler = genirq_unregister(priv->genirq, irq, isr, arg); |
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559 | if ( handler == NULL ) |
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560 | status = DRVMGR_FAIL; |
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561 | else |
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562 | status = DRVMGR_OK; |
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563 | |
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564 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
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565 | |
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566 | if (handler) |
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567 | genirq_free_handler(handler); |
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568 | |
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569 | return status; |
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570 | } |
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571 | |
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572 | int ambapp_rasta_adcdac_int_unmask( |
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573 | struct drvmgr_dev *dev, |
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574 | int irq) |
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575 | { |
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576 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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577 | SPIN_IRQFLAGS(irqflags); |
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578 | |
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579 | DBG("RASTA-ADCDAC IRQ %d: unmask\n", irq); |
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580 | |
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581 | if ( genirq_check(priv->genirq, irq) ) |
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582 | return DRVMGR_EINVAL; |
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583 | |
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584 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
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585 | |
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586 | /* Enable IRQ for first enabled handler only */ |
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587 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
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588 | |
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589 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
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590 | |
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591 | return DRVMGR_OK; |
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592 | } |
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593 | |
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594 | int ambapp_rasta_adcdac_int_mask( |
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595 | struct drvmgr_dev *dev, |
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596 | int irq) |
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597 | { |
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598 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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599 | SPIN_IRQFLAGS(irqflags); |
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600 | |
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601 | DBG("RASTA-ADCDAC IRQ %d: mask\n", irq); |
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602 | |
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603 | if ( genirq_check(priv->genirq, irq) ) |
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604 | return DRVMGR_EINVAL; |
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605 | |
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606 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
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607 | |
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608 | /* Disable/mask IRQ */ |
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609 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
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610 | |
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611 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
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612 | |
---|
613 | return DRVMGR_OK; |
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614 | } |
---|
615 | |
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616 | int ambapp_rasta_adcdac_int_clear( |
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617 | struct drvmgr_dev *dev, |
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618 | int irq) |
---|
619 | { |
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620 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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621 | |
---|
622 | if ( genirq_check(priv->genirq, irq) ) |
---|
623 | return DRVMGR_FAIL; |
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624 | |
---|
625 | priv->irq->iclear = (1<<irq); |
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626 | |
---|
627 | return DRVMGR_OK; |
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628 | } |
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629 | |
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630 | int ambapp_rasta_adcdac_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
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631 | { |
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632 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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633 | |
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634 | /* Device name prefix pointer, skip /dev */ |
---|
635 | params->dev_prefix = &priv->prefix[5]; |
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636 | |
---|
637 | return 0; |
---|
638 | } |
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639 | |
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640 | void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options) |
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641 | { |
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642 | struct gr_rasta_adcdac_priv *priv = dev->priv; |
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643 | struct pci_dev_info *devinfo = priv->devinfo; |
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644 | uint32_t bar0, bar1, bar0_size, bar1_size; |
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645 | |
---|
646 | /* Print */ |
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647 | printf("--- GR-RASTA-ADCDAC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n", |
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648 | PCI_DEV_EXPAND(priv->pcidev)); |
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649 | |
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650 | bar0 = devinfo->resources[0].address; |
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651 | bar0_size = devinfo->resources[0].size; |
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652 | bar1 = devinfo->resources[1].address; |
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653 | bar1_size = devinfo->resources[1].size; |
---|
654 | |
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655 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
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656 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
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657 | printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq); |
---|
658 | printf(" IRQ: %d\n", devinfo->irq); |
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659 | printf(" PCI REVISION: %d\n", devinfo->rev); |
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660 | printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz); |
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661 | printf(" IMASK: 0x%08x\n", priv->irq->mask[0]); |
---|
662 | printf(" IPEND: 0x%08x\n", priv->irq->ipend); |
---|
663 | |
---|
664 | /* Print amba config */ |
---|
665 | if ( options & RASTA_ADCDAC_OPTIONS_AMBA ) { |
---|
666 | ambapp_print(&priv->abus, 10); |
---|
667 | } |
---|
668 | #if 0 |
---|
669 | /* Print IRQ handlers and their arguments */ |
---|
670 | if ( options & RASTA_ADCDAC_OPTIONS_IRQ ) { |
---|
671 | int i; |
---|
672 | for(i=0; i<16; i++) { |
---|
673 | printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n", |
---|
674 | i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg); |
---|
675 | } |
---|
676 | } |
---|
677 | #endif |
---|
678 | } |
---|
679 | |
---|
680 | void gr_rasta_adcdac_print(int options) |
---|
681 | { |
---|
682 | struct pci_drv_info *drv = &gr_rasta_adcdac_info; |
---|
683 | struct drvmgr_dev *dev; |
---|
684 | |
---|
685 | dev = drv->general.dev; |
---|
686 | while(dev) { |
---|
687 | gr_rasta_adcdac_print_dev(dev, options); |
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688 | dev = dev->next_in_drv; |
---|
689 | } |
---|
690 | } |
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