[e67b2b8d] | 1 | /* GR-RASTA-ADCDAC PCI Target driver. |
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| 2 | * |
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| 3 | * COPYRIGHT (c) 2008. |
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| 4 | * Cobham Gaisler AB. |
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| 5 | * |
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| 6 | * Configures the GR-RASTA-ADCDAC interface PCI board. |
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| 7 | * This driver provides a AMBA PnP bus by using the general part |
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| 8 | * of the AMBA PnP bus driver (ambapp_bus.c). |
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| 9 | * |
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| 10 | * Driver resources for the AMBA PnP bus provided can be set using |
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| 11 | * gr_rasta_adcdac_set_resources(). |
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| 12 | * |
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| 13 | * The license and distribution terms for this file may be |
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| 14 | * found in found in the file LICENSE in this distribution or at |
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[4a7d1026] | 15 | * http://www.rtems.org/license/LICENSE. |
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[e67b2b8d] | 16 | */ |
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| 17 | |
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| 18 | #include <stdio.h> |
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| 19 | #include <stdlib.h> |
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| 20 | #include <string.h> |
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| 21 | #include <sys/types.h> |
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| 22 | #include <sys/stat.h> |
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| 23 | |
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| 24 | #include <bsp.h> |
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| 25 | #include <rtems/bspIo.h> |
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| 26 | #include <pci.h> |
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| 27 | |
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| 28 | #include <ambapp.h> |
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| 29 | #include <grlib.h> |
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| 30 | #include <drvmgr/drvmgr.h> |
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| 31 | #include <drvmgr/ambapp_bus.h> |
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| 32 | #include <drvmgr/pci_bus.h> |
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[03037b4] | 33 | #include <drvmgr/bspcommon.h> |
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[5823bae8] | 34 | #include <bsp/genirq.h> |
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[e67b2b8d] | 35 | |
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[5823bae8] | 36 | #include <bsp/gr_rasta_adcdac.h> |
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[e67b2b8d] | 37 | |
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[a7267241] | 38 | #include <grlib_impl.h> |
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[ce76b9d2] | 39 | |
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[e67b2b8d] | 40 | /*#define DEBUG 1*/ |
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| 41 | |
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| 42 | #ifdef DEBUG |
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| 43 | #define DBG(x...) printk(x) |
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| 44 | #else |
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| 45 | #define DBG(x...) |
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| 46 | #endif |
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| 47 | |
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| 48 | /* Determines which PCI address the AHB masters will access, it should be |
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| 49 | * set so that the masters can access the CPU RAM. Default is base of CPU RAM, |
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| 50 | * CPU RAM is mapped 1:1 to PCI space. |
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| 51 | */ |
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| 52 | extern unsigned int _RAM_START; |
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| 53 | #define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000) |
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| 54 | |
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| 55 | /* PCI ID */ |
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| 56 | #define PCIID_VENDOR_GAISLER 0x1AC8 |
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| 57 | #define PCIID_DEVICE_GR_RASTA_ADCDAC 0x0014 |
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| 58 | |
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| 59 | int gr_rasta_adcdac_init1(struct drvmgr_dev *dev); |
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| 60 | int gr_rasta_adcdac_init2(struct drvmgr_dev *dev); |
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[03037b4] | 61 | void gr_rasta_adcdac_isr (void *arg); |
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[e67b2b8d] | 62 | |
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| 63 | struct grpci_regs { |
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| 64 | volatile unsigned int cfg_stat; |
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| 65 | volatile unsigned int bar0; |
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| 66 | volatile unsigned int page0; |
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| 67 | volatile unsigned int bar1; |
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| 68 | volatile unsigned int page1; |
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| 69 | volatile unsigned int iomap; |
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| 70 | volatile unsigned int stat_cmd; |
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| 71 | }; |
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| 72 | |
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| 73 | struct gr_rasta_adcdac_ver { |
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| 74 | const unsigned int amba_freq_hz; /* The frequency */ |
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| 75 | const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */ |
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| 76 | }; |
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| 77 | |
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| 78 | /* Private data structure for driver */ |
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| 79 | struct gr_rasta_adcdac_priv { |
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| 80 | /* Driver management */ |
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[ce76b9d2] | 81 | struct drvmgr_dev *dev; |
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[e67b2b8d] | 82 | char prefix[20]; |
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[ce76b9d2] | 83 | SPIN_DECLARE(devlock); |
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[e67b2b8d] | 84 | |
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| 85 | /* PCI */ |
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| 86 | pci_dev_t pcidev; |
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| 87 | struct pci_dev_info *devinfo; |
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| 88 | uint32_t ahbmst2pci_map; |
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| 89 | |
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| 90 | /* IRQ */ |
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| 91 | genirq_t genirq; |
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| 92 | |
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| 93 | /* GR-RASTA-ADCDAC */ |
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| 94 | struct gr_rasta_adcdac_ver *version; |
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| 95 | struct irqmp_regs *irq; |
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| 96 | struct grpci_regs *grpci; |
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| 97 | struct drvmgr_map_entry bus_maps_down[3]; |
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| 98 | struct drvmgr_map_entry bus_maps_up[2]; |
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| 99 | |
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| 100 | /* AMBA Plug&Play information on GR-RASTA-ADCDAC */ |
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| 101 | struct ambapp_bus abus; |
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| 102 | struct ambapp_mmap amba_maps[4]; |
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| 103 | struct ambapp_config config; |
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| 104 | }; |
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| 105 | |
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| 106 | struct gr_rasta_adcdac_ver gr_rasta_adcdac_ver0 = { |
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| 107 | .amba_freq_hz = 50000000, |
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| 108 | .amba_ioarea = 0x80100000, |
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| 109 | }; |
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| 110 | |
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| 111 | int ambapp_rasta_adcdac_int_register( |
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| 112 | struct drvmgr_dev *dev, |
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| 113 | int irq, |
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| 114 | const char *info, |
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| 115 | drvmgr_isr handler, |
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| 116 | void *arg); |
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| 117 | int ambapp_rasta_adcdac_int_unregister( |
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| 118 | struct drvmgr_dev *dev, |
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| 119 | int irq, |
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| 120 | drvmgr_isr isr, |
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| 121 | void *arg); |
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| 122 | int ambapp_rasta_adcdac_int_unmask( |
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| 123 | struct drvmgr_dev *dev, |
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| 124 | int irq); |
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| 125 | int ambapp_rasta_adcdac_int_mask( |
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| 126 | struct drvmgr_dev *dev, |
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| 127 | int irq); |
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| 128 | int ambapp_rasta_adcdac_int_clear( |
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| 129 | struct drvmgr_dev *dev, |
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| 130 | int irq); |
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| 131 | int ambapp_rasta_adcdac_get_params( |
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| 132 | struct drvmgr_dev *dev, |
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| 133 | struct drvmgr_bus_params *params); |
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| 134 | |
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| 135 | struct ambapp_ops ambapp_rasta_adcdac_ops = { |
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| 136 | .int_register = ambapp_rasta_adcdac_int_register, |
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| 137 | .int_unregister = ambapp_rasta_adcdac_int_unregister, |
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| 138 | .int_unmask = ambapp_rasta_adcdac_int_unmask, |
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| 139 | .int_mask = ambapp_rasta_adcdac_int_mask, |
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| 140 | .int_clear = ambapp_rasta_adcdac_int_clear, |
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| 141 | .get_params = ambapp_rasta_adcdac_get_params |
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| 142 | }; |
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| 143 | |
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| 144 | struct drvmgr_drv_ops gr_rasta_adcdac_ops = |
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| 145 | { .init = {gr_rasta_adcdac_init1, gr_rasta_adcdac_init2, NULL, NULL}, |
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| 146 | .remove = NULL, |
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| 147 | .info = NULL |
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| 148 | }; |
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| 149 | |
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| 150 | struct pci_dev_id_match gr_rasta_adcdac_ids[] = |
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| 151 | { |
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| 152 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC), |
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| 153 | PCIID_END_TABLE /* Mark end of table */ |
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| 154 | }; |
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| 155 | |
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| 156 | struct pci_drv_info gr_rasta_adcdac_info = |
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| 157 | { |
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| 158 | { |
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| 159 | DRVMGR_OBJ_DRV, /* Driver */ |
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| 160 | NULL, /* Next driver */ |
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| 161 | NULL, /* Device list */ |
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| 162 | DRIVER_PCI_GAISLER_RASTAADCDAC_ID,/* Driver ID */ |
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| 163 | "GR-RASTA-ADCDAC_DRV", /* Driver Name */ |
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| 164 | DRVMGR_BUS_TYPE_PCI, /* Bus Type */ |
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| 165 | &gr_rasta_adcdac_ops, |
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| 166 | NULL, /* Funcs */ |
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| 167 | 0, /* No devices yet */ |
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| 168 | 0, |
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| 169 | }, |
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| 170 | &gr_rasta_adcdac_ids[0] |
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| 171 | }; |
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| 172 | |
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| 173 | /* Driver resources configuration for the AMBA bus on the GR-RASTA-ADCDAC board. |
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| 174 | * It is declared weak so that the user may override it from the project file, |
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| 175 | * if the default settings are not enough. |
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| 176 | * |
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| 177 | * The configuration consists of an array of configuration pointers, each |
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| 178 | * pointer determine the configuration of one GR-RASTA-ADCDAC board. Pointer |
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| 179 | * zero is for board0, pointer 1 for board1 and so on. |
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| 180 | * |
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| 181 | * The array must end with a NULL pointer. |
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| 182 | */ |
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| 183 | struct drvmgr_bus_res *gr_rasta_adcdac_resources[] __attribute__((weak)) = |
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| 184 | { |
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| 185 | NULL |
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| 186 | }; |
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| 187 | |
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| 188 | void gr_rasta_adcdac_register_drv(void) |
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| 189 | { |
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| 190 | DBG("Registering GR-RASTA-ADCDAC PCI driver\n"); |
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| 191 | drvmgr_drv_register(&gr_rasta_adcdac_info.general); |
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| 192 | } |
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| 193 | |
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| 194 | void gr_rasta_adcdac_isr (void *arg) |
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| 195 | { |
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| 196 | struct gr_rasta_adcdac_priv *priv = arg; |
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| 197 | unsigned int status, tmp; |
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| 198 | int irq; |
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[ce76b9d2] | 199 | SPIN_ISR_IRQFLAGS(irqflags); |
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| 200 | |
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[e67b2b8d] | 201 | tmp = status = priv->irq->ipend; |
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| 202 | |
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| 203 | /* DBG("GR-RASTA-ADCDAC: IRQ 0x%x\n",status); */ |
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| 204 | |
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[ce76b9d2] | 205 | SPIN_LOCK(&priv->devlock, irqflags); |
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[e67b2b8d] | 206 | for(irq=0; irq<16; irq++) { |
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| 207 | if ( status & (1<<irq) ) { |
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| 208 | genirq_doirq(priv->genirq, irq); |
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| 209 | priv->irq->iclear = (1<<irq); |
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| 210 | status &= ~(1<<irq); |
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| 211 | if ( status == 0 ) |
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| 212 | break; |
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| 213 | } |
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| 214 | } |
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[ce76b9d2] | 215 | SPIN_UNLOCK(&priv->devlock, irqflags); |
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[e67b2b8d] | 216 | |
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| 217 | /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */ |
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| 218 | if ( tmp ) |
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| 219 | drvmgr_interrupt_clear(priv->dev, 0); |
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| 220 | |
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| 221 | DBG("RASTA-ADCDAC-IRQ: 0x%x\n", tmp); |
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| 222 | } |
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| 223 | |
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[03037b4] | 224 | static int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv) |
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[e67b2b8d] | 225 | { |
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| 226 | uint32_t data; |
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| 227 | unsigned int *page0 = NULL; |
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| 228 | struct ambapp_dev *tmp; |
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| 229 | struct ambapp_ahb_info *ahb; |
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| 230 | struct pci_dev_info *devinfo = priv->devinfo; |
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| 231 | uint32_t bar0, bar0_size; |
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| 232 | |
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| 233 | /* Select version of GR-RASTA-ADCDAC board */ |
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| 234 | switch (devinfo->rev) { |
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| 235 | case 0: |
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| 236 | priv->version = &gr_rasta_adcdac_ver0; |
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| 237 | break; |
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| 238 | default: |
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| 239 | return -2; |
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| 240 | } |
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| 241 | |
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| 242 | bar0 = devinfo->resources[0].address; |
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| 243 | bar0_size = devinfo->resources[0].size; |
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| 244 | page0 = (unsigned int *)(bar0 + bar0_size/2); |
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| 245 | |
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| 246 | /* Point PAGE0 to start of Plug and Play information */ |
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| 247 | *page0 = priv->version->amba_ioarea & 0xf0000000; |
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| 248 | |
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| 249 | /* set parity error response */ |
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[8b29637c] | 250 | pci_cfg_r32(priv->pcidev, PCIR_COMMAND, &data); |
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| 251 | pci_cfg_w32(priv->pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN)); |
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[e67b2b8d] | 252 | |
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[819de55b] | 253 | /* Setup cache line size. Default cache line size will result in |
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| 254 | * poor performance (256 word fetches), 0xff will set it according |
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| 255 | * to the max size of the PCI FIFO. |
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| 256 | */ |
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[8b29637c] | 257 | pci_cfg_w8(priv->pcidev, PCIR_CACHELNSZ, 0xff); |
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[819de55b] | 258 | |
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[e67b2b8d] | 259 | /* Scan AMBA Plug&Play */ |
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| 260 | |
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| 261 | /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ |
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| 262 | priv->amba_maps[0].size = bar0_size/2; |
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| 263 | priv->amba_maps[0].local_adr = bar0; |
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| 264 | priv->amba_maps[0].remote_adr = 0x80000000; |
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| 265 | |
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| 266 | /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */ |
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| 267 | priv->amba_maps[1].size = devinfo->resources[1].size; |
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| 268 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
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| 269 | priv->amba_maps[1].remote_adr = 0x40000000; |
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| 270 | |
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| 271 | /* Addresses not matching with map be untouched */ |
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| 272 | priv->amba_maps[2].size = 0xfffffff0; |
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| 273 | priv->amba_maps[2].local_adr = 0; |
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| 274 | priv->amba_maps[2].remote_adr = 0; |
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| 275 | |
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| 276 | /* Mark end of table */ |
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| 277 | priv->amba_maps[3].size=0; |
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| 278 | priv->amba_maps[3].local_adr = 0; |
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| 279 | priv->amba_maps[3].remote_adr = 0; |
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| 280 | |
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| 281 | /* Start AMBA PnP scan at first AHB bus */ |
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| 282 | /*ambapp_scan(priv->bar0 + (priv->version->amba_ioarea & ~0xf0000000), |
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| 283 | NULL, &priv->amba_maps[0], NULL, &priv->abus.root, NULL);*/ |
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| 284 | ambapp_scan(&priv->abus, |
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| 285 | bar0 + (priv->version->amba_ioarea & ~0xf0000000), |
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| 286 | NULL, &priv->amba_maps[0]); |
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| 287 | |
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| 288 | /* Initialize Frequency of AMBA bus */ |
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| 289 | ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz); |
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| 290 | |
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| 291 | /* Point PAGE0 to start of APB area */ |
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| 292 | *page0 = 0x80000000; |
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| 293 | |
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| 294 | /* Find GRPCI controller */ |
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[03037b4] | 295 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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[e67b2b8d] | 296 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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| 297 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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| 298 | ambapp_find_by_idx, NULL); |
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| 299 | if ( !tmp ) { |
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| 300 | return -3; |
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| 301 | } |
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| 302 | priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start; |
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| 303 | |
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| 304 | /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over |
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| 305 | * the PCI window. |
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| 306 | */ |
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| 307 | priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) | |
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| 308 | (priv->ahbmst2pci_map & 0xf0000000); |
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| 309 | priv->grpci->page1 = 0x40000000; |
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| 310 | |
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| 311 | /* Find IRQ controller */ |
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[03037b4] | 312 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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[e67b2b8d] | 313 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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| 314 | VENDOR_GAISLER, GAISLER_IRQMP, |
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| 315 | ambapp_find_by_idx, NULL); |
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| 316 | if ( !tmp ) { |
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| 317 | return -4; |
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| 318 | } |
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| 319 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
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| 320 | /* Set up GR-RASTA-ADCDAC irq controller */ |
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| 321 | priv->irq->iclear = 0xffff; |
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| 322 | priv->irq->ilevel = 0; |
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| 323 | priv->irq->mask[0] = 0; |
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| 324 | |
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| 325 | /* DOWN streams translation table */ |
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| 326 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
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| 327 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
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| 328 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
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| 329 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
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| 330 | |
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| 331 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
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| 332 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
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| 333 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
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| 334 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
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| 335 | |
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| 336 | /* Mark end of translation table */ |
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| 337 | priv->bus_maps_down[2].size = 0; |
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| 338 | |
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| 339 | /* Find GRPCI controller AHB Slave interface */ |
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[03037b4] | 340 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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[e67b2b8d] | 341 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
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| 342 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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| 343 | ambapp_find_by_idx, NULL); |
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| 344 | if ( !tmp ) { |
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| 345 | return -5; |
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| 346 | } |
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| 347 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
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| 348 | |
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| 349 | /* UP streams translation table */ |
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| 350 | priv->bus_maps_up[0].name = "AMBA GRPCI Window"; |
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| 351 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-ADCDAC board */ |
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| 352 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
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| 353 | priv->bus_maps_up[0].to_adr = (void *) |
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| 354 | (priv->ahbmst2pci_map & 0xf0000000); |
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| 355 | |
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| 356 | /* Mark end of translation table */ |
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| 357 | priv->bus_maps_up[1].size = 0; |
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| 358 | |
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| 359 | /* Successfully registered the RASTA board */ |
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| 360 | return 0; |
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| 361 | } |
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| 362 | |
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[03037b4] | 363 | static int gr_rasta_adcdac_hw_init2(struct gr_rasta_adcdac_priv *priv) |
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[e67b2b8d] | 364 | { |
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| 365 | /* Enable DMA by enabling PCI target as master */ |
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| 366 | pci_master_enable(priv->pcidev); |
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| 367 | |
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| 368 | return DRVMGR_OK; |
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| 369 | } |
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| 370 | |
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| 371 | /* Called when a PCI target is found with the PCI device and vendor ID |
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| 372 | * given in gr_rasta_adcdac_ids[]. |
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| 373 | */ |
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| 374 | int gr_rasta_adcdac_init1(struct drvmgr_dev *dev) |
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| 375 | { |
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| 376 | struct gr_rasta_adcdac_priv *priv; |
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| 377 | struct pci_dev_info *devinfo; |
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| 378 | int status; |
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| 379 | uint32_t bar0, bar1, bar0_size, bar1_size; |
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| 380 | union drvmgr_key_value *value; |
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[03037b4] | 381 | int resources_cnt; |
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[e67b2b8d] | 382 | |
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[11f3b9a] | 383 | priv = grlib_calloc(1, sizeof(*priv)); |
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[e67b2b8d] | 384 | if ( !priv ) |
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| 385 | return DRVMGR_NOMEM; |
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| 386 | |
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| 387 | dev->priv = priv; |
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| 388 | priv->dev = dev; |
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| 389 | |
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| 390 | /* Determine number of configurations */ |
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[03037b4] | 391 | resources_cnt = get_resarray_count(gr_rasta_adcdac_resources); |
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[e67b2b8d] | 392 | |
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| 393 | /* Generate Device prefix */ |
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| 394 | |
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| 395 | strcpy(priv->prefix, "/dev/rastaadcdac0"); |
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| 396 | priv->prefix[16] += dev->minor_drv; |
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| 397 | mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO); |
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| 398 | priv->prefix[17] = '/'; |
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| 399 | priv->prefix[18] = '\0'; |
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| 400 | |
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| 401 | priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo; |
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| 402 | priv->pcidev = devinfo->pcidev; |
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| 403 | bar0 = devinfo->resources[0].address; |
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| 404 | bar0_size = devinfo->resources[0].size; |
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| 405 | bar1 = devinfo->resources[1].address; |
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| 406 | bar1_size = devinfo->resources[1].size; |
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[56a7540] | 407 | printk("\n\n--- GR-RASTA-ADCDAC[%d] ---\n", dev->minor_drv); |
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| 408 | printk(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n", |
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[e67b2b8d] | 409 | PCI_DEV_EXPAND(priv->pcidev)); |
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[56a7540] | 410 | printk(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n", |
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[e67b2b8d] | 411 | devinfo->id.vendor, devinfo->id.device); |
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[56a7540] | 412 | printk(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
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| 413 | printk(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
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| 414 | printk(" IRQ: %d\n\n\n", devinfo->irq); |
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[e67b2b8d] | 415 | |
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| 416 | /* all neccessary space assigned to GR-RASTA-ADCDAC target? */ |
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| 417 | if ((bar0_size == 0) || (bar1_size == 0)) |
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| 418 | return DRVMGR_ENORES; |
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| 419 | |
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[ce76b9d2] | 420 | /* Initialize spin-lock for this PCI perihperal device. This is to |
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| 421 | * protect the Interrupt Controller Registers. The genirq layer is |
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| 422 | * protecting its own internals and ISR dispatching. |
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| 423 | */ |
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| 424 | SPIN_INIT(&priv->devlock, priv->prefix); |
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| 425 | |
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[e67b2b8d] | 426 | /* Let user override which PCI address the AHB masters of the |
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| 427 | * RASTA-ADCDAC board access when doing DMA to CPU RAM. The AHB masters |
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| 428 | * access the PCI Window of the AMBA bus, the MSB 4-bits of that address |
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| 429 | * is translated according this config option before the address |
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| 430 | * goes out on the PCI bus. |
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| 431 | * Only the 4 MSB bits have an effect; |
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| 432 | */ |
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[4d3e70f4] | 433 | value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", DRVMGR_KT_INT); |
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[e67b2b8d] | 434 | if (value) |
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| 435 | priv->ahbmst2pci_map = value->i; |
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| 436 | else |
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| 437 | priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */ |
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| 438 | |
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| 439 | priv->genirq = genirq_init(16); |
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| 440 | if ( priv->genirq == NULL ) { |
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| 441 | free(priv); |
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| 442 | dev->priv = NULL; |
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| 443 | return DRVMGR_FAIL; |
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| 444 | } |
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| 445 | |
---|
| 446 | if ( (status = gr_rasta_adcdac_hw_init1(priv)) != 0 ) { |
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| 447 | genirq_destroy(priv->genirq); |
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| 448 | free(priv); |
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| 449 | dev->priv = NULL; |
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[56a7540] | 450 | printk(" Failed to initialize GR-RASTA-ADCDAC HW: %d\n", status); |
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[e67b2b8d] | 451 | return DRVMGR_FAIL; |
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| 452 | } |
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| 453 | |
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| 454 | /* Init amba bus */ |
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| 455 | priv->config.abus = &priv->abus; |
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| 456 | priv->config.ops = &ambapp_rasta_adcdac_ops; |
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| 457 | priv->config.maps_up = &priv->bus_maps_up[0]; |
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| 458 | priv->config.maps_down = &priv->bus_maps_down[0]; |
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[03037b4] | 459 | if ( priv->dev->minor_drv < resources_cnt ) { |
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[e67b2b8d] | 460 | priv->config.resources = gr_rasta_adcdac_resources[priv->dev->minor_drv]; |
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| 461 | } else { |
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| 462 | priv->config.resources = NULL; |
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| 463 | } |
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| 464 | |
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| 465 | /* Create and register AMBA PnP bus. */ |
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| 466 | return ambapp_bus_register(dev, &priv->config); |
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| 467 | } |
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| 468 | |
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| 469 | int gr_rasta_adcdac_init2(struct drvmgr_dev *dev) |
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| 470 | { |
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| 471 | struct gr_rasta_adcdac_priv *priv = dev->priv; |
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| 472 | |
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| 473 | /* Clear any old interrupt requests */ |
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| 474 | drvmgr_interrupt_clear(dev, 0); |
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| 475 | |
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| 476 | /* Enable System IRQ so that GR-RASTA-ADCDAC PCI target interrupt |
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| 477 | * goes through. |
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| 478 | * |
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| 479 | * It is important to enable it in stage init2. If interrupts were |
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| 480 | * enabled in init1 this might hang the system when more than one |
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| 481 | * PCI board is connected, this is because PCI interrupts might |
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| 482 | * be shared and PCI board 2 have not initialized and might |
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| 483 | * therefore drive interrupt already when entering init1(). |
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| 484 | */ |
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| 485 | drvmgr_interrupt_register( |
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| 486 | dev, |
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| 487 | 0, |
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| 488 | "gr_rasta_adcdac", |
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| 489 | gr_rasta_adcdac_isr, |
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| 490 | (void *)priv); |
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| 491 | |
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| 492 | return gr_rasta_adcdac_hw_init2(priv); |
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| 493 | } |
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| 494 | |
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| 495 | int ambapp_rasta_adcdac_int_register( |
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| 496 | struct drvmgr_dev *dev, |
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| 497 | int irq, |
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| 498 | const char *info, |
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| 499 | drvmgr_isr handler, |
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| 500 | void *arg) |
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| 501 | { |
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| 502 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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[ce76b9d2] | 503 | SPIN_IRQFLAGS(irqflags); |
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[e67b2b8d] | 504 | int status; |
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[ce76b9d2] | 505 | void *h; |
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[e67b2b8d] | 506 | |
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[ce76b9d2] | 507 | h = genirq_alloc_handler(handler, arg); |
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| 508 | if ( h == NULL ) |
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| 509 | return DRVMGR_FAIL; |
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[e67b2b8d] | 510 | |
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[ce76b9d2] | 511 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
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| 512 | |
---|
| 513 | status = genirq_register(priv->genirq, irq, h); |
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[e67b2b8d] | 514 | if ( status == 0 ) { |
---|
| 515 | /* Clear IRQ for first registered handler */ |
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| 516 | priv->irq->iclear = (1<<irq); |
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| 517 | } else if ( status == 1 ) |
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| 518 | status = 0; |
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| 519 | |
---|
| 520 | if (status != 0) { |
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[ce76b9d2] | 521 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
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| 522 | genirq_free_handler(h); |
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[e67b2b8d] | 523 | return DRVMGR_FAIL; |
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| 524 | } |
---|
| 525 | |
---|
| 526 | status = genirq_enable(priv->genirq, irq, handler, arg); |
---|
| 527 | if ( status == 0 ) { |
---|
| 528 | /* Enable IRQ for first enabled handler only */ |
---|
| 529 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
| 530 | } else if ( status == 1 ) |
---|
| 531 | status = 0; |
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| 532 | |
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[ce76b9d2] | 533 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
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[e67b2b8d] | 534 | |
---|
| 535 | return status; |
---|
| 536 | } |
---|
| 537 | |
---|
| 538 | int ambapp_rasta_adcdac_int_unregister( |
---|
| 539 | struct drvmgr_dev *dev, |
---|
| 540 | int irq, |
---|
| 541 | drvmgr_isr isr, |
---|
| 542 | void *arg) |
---|
| 543 | { |
---|
| 544 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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[ce76b9d2] | 545 | SPIN_IRQFLAGS(irqflags); |
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[e67b2b8d] | 546 | int status; |
---|
[ce76b9d2] | 547 | void *handler; |
---|
[e67b2b8d] | 548 | |
---|
[ce76b9d2] | 549 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
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[e67b2b8d] | 550 | |
---|
| 551 | status = genirq_disable(priv->genirq, irq, isr, arg); |
---|
| 552 | if ( status == 0 ) { |
---|
| 553 | /* Disable IRQ only when no enabled handler exists */ |
---|
| 554 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
| 555 | } |
---|
| 556 | |
---|
[ce76b9d2] | 557 | handler = genirq_unregister(priv->genirq, irq, isr, arg); |
---|
| 558 | if ( handler == NULL ) |
---|
[e67b2b8d] | 559 | status = DRVMGR_FAIL; |
---|
[ce76b9d2] | 560 | else |
---|
| 561 | status = DRVMGR_OK; |
---|
| 562 | |
---|
| 563 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
[e67b2b8d] | 564 | |
---|
[ce76b9d2] | 565 | if (handler) |
---|
| 566 | genirq_free_handler(handler); |
---|
[e67b2b8d] | 567 | |
---|
| 568 | return status; |
---|
| 569 | } |
---|
| 570 | |
---|
| 571 | int ambapp_rasta_adcdac_int_unmask( |
---|
| 572 | struct drvmgr_dev *dev, |
---|
| 573 | int irq) |
---|
| 574 | { |
---|
| 575 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
---|
[ce76b9d2] | 576 | SPIN_IRQFLAGS(irqflags); |
---|
[e67b2b8d] | 577 | |
---|
| 578 | DBG("RASTA-ADCDAC IRQ %d: unmask\n", irq); |
---|
| 579 | |
---|
| 580 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 581 | return DRVMGR_EINVAL; |
---|
| 582 | |
---|
[ce76b9d2] | 583 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
[e67b2b8d] | 584 | |
---|
| 585 | /* Enable IRQ for first enabled handler only */ |
---|
| 586 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
| 587 | |
---|
[ce76b9d2] | 588 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
[e67b2b8d] | 589 | |
---|
| 590 | return DRVMGR_OK; |
---|
| 591 | } |
---|
| 592 | |
---|
| 593 | int ambapp_rasta_adcdac_int_mask( |
---|
| 594 | struct drvmgr_dev *dev, |
---|
| 595 | int irq) |
---|
| 596 | { |
---|
| 597 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
---|
[ce76b9d2] | 598 | SPIN_IRQFLAGS(irqflags); |
---|
[e67b2b8d] | 599 | |
---|
| 600 | DBG("RASTA-ADCDAC IRQ %d: mask\n", irq); |
---|
| 601 | |
---|
| 602 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 603 | return DRVMGR_EINVAL; |
---|
| 604 | |
---|
[ce76b9d2] | 605 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
[e67b2b8d] | 606 | |
---|
| 607 | /* Disable/mask IRQ */ |
---|
| 608 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
| 609 | |
---|
[ce76b9d2] | 610 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
[e67b2b8d] | 611 | |
---|
| 612 | return DRVMGR_OK; |
---|
| 613 | } |
---|
| 614 | |
---|
| 615 | int ambapp_rasta_adcdac_int_clear( |
---|
| 616 | struct drvmgr_dev *dev, |
---|
| 617 | int irq) |
---|
| 618 | { |
---|
| 619 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
---|
| 620 | |
---|
| 621 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 622 | return DRVMGR_FAIL; |
---|
| 623 | |
---|
| 624 | priv->irq->iclear = (1<<irq); |
---|
| 625 | |
---|
| 626 | return DRVMGR_OK; |
---|
| 627 | } |
---|
| 628 | |
---|
| 629 | int ambapp_rasta_adcdac_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
---|
| 630 | { |
---|
| 631 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
---|
| 632 | |
---|
| 633 | /* Device name prefix pointer, skip /dev */ |
---|
| 634 | params->dev_prefix = &priv->prefix[5]; |
---|
| 635 | |
---|
| 636 | return 0; |
---|
| 637 | } |
---|
| 638 | |
---|
| 639 | void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options) |
---|
| 640 | { |
---|
| 641 | struct gr_rasta_adcdac_priv *priv = dev->priv; |
---|
| 642 | struct pci_dev_info *devinfo = priv->devinfo; |
---|
| 643 | uint32_t bar0, bar1, bar0_size, bar1_size; |
---|
| 644 | |
---|
| 645 | /* Print */ |
---|
| 646 | printf("--- GR-RASTA-ADCDAC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n", |
---|
| 647 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
| 648 | |
---|
| 649 | bar0 = devinfo->resources[0].address; |
---|
| 650 | bar0_size = devinfo->resources[0].size; |
---|
| 651 | bar1 = devinfo->resources[1].address; |
---|
| 652 | bar1_size = devinfo->resources[1].size; |
---|
| 653 | |
---|
| 654 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
---|
| 655 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
---|
| 656 | printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq); |
---|
| 657 | printf(" IRQ: %d\n", devinfo->irq); |
---|
| 658 | printf(" PCI REVISION: %d\n", devinfo->rev); |
---|
| 659 | printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz); |
---|
| 660 | printf(" IMASK: 0x%08x\n", priv->irq->mask[0]); |
---|
| 661 | printf(" IPEND: 0x%08x\n", priv->irq->ipend); |
---|
| 662 | |
---|
| 663 | /* Print amba config */ |
---|
| 664 | if ( options & RASTA_ADCDAC_OPTIONS_AMBA ) { |
---|
| 665 | ambapp_print(&priv->abus, 10); |
---|
| 666 | } |
---|
| 667 | #if 0 |
---|
| 668 | /* Print IRQ handlers and their arguments */ |
---|
| 669 | if ( options & RASTA_ADCDAC_OPTIONS_IRQ ) { |
---|
| 670 | int i; |
---|
| 671 | for(i=0; i<16; i++) { |
---|
| 672 | printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n", |
---|
| 673 | i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg); |
---|
| 674 | } |
---|
| 675 | } |
---|
| 676 | #endif |
---|
| 677 | } |
---|
| 678 | |
---|
| 679 | void gr_rasta_adcdac_print(int options) |
---|
| 680 | { |
---|
| 681 | struct pci_drv_info *drv = &gr_rasta_adcdac_info; |
---|
| 682 | struct drvmgr_dev *dev; |
---|
| 683 | |
---|
| 684 | dev = drv->general.dev; |
---|
| 685 | while(dev) { |
---|
| 686 | gr_rasta_adcdac_print_dev(dev, options); |
---|
| 687 | dev = dev->next_in_drv; |
---|
| 688 | } |
---|
| 689 | } |
---|