[ffd8002d] | 1 | /* GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver |
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| 2 | * |
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| 3 | * COPYRIGHT (c) 2013. |
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| 4 | * Cobham Gaisler AB. |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in found in the file LICENSE in this distribution or at |
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[4a7d1026] | 8 | * http://www.rtems.org/license/LICENSE. |
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[ffd8002d] | 9 | * |
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| 10 | * Configures the GR-CPIC-LEON4-N2X interface PCI board in peripheral |
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| 11 | * mode. This driver provides a AMBA PnP bus by using the general part |
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| 12 | * of the AMBA PnP bus driver (ambapp_bus.c). |
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| 13 | * |
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| 14 | * |
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| 15 | * Driver resource options: |
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| 16 | * NAME DEFAULT VALUE |
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| 17 | * ahbmst2pci _RAM_START AMBA->PCI translation PCI base address |
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| 18 | * ambaFreq 200000000 (200MHz) AMBA system frequency of LEON4-N2X |
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| 19 | * cgEnMask 0x1f (all) Clock gating enable mask |
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| 20 | * |
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| 21 | * TODO/UNTESTED |
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| 22 | * Interrupt testing |
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| 23 | * bar0 RESOURCE 0x00000000 L2-Cache SDRAM memory |
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| 24 | * bar1 RESOURCE 0xf0000000 L2-Cache registers |
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| 25 | */ |
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| 26 | |
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[c05d7a9d] | 27 | #include <inttypes.h> |
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[ffd8002d] | 28 | #include <stdio.h> |
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| 29 | #include <stdlib.h> |
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| 30 | #include <string.h> |
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| 31 | #include <sys/types.h> |
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| 32 | #include <sys/stat.h> |
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| 33 | |
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| 34 | #include <bsp.h> |
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| 35 | #include <rtems/bspIo.h> |
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| 36 | #include <pci.h> |
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| 37 | |
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| 38 | #include <ambapp.h> |
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| 39 | #include <grlib.h> |
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| 40 | #include <drvmgr/drvmgr.h> |
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| 41 | #include <drvmgr/ambapp_bus.h> |
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| 42 | #include <drvmgr/pci_bus.h> |
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[ef7a009] | 43 | #include <drvmgr/bspcommon.h> |
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[5823bae8] | 44 | #include <bsp/genirq.h> |
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[ffd8002d] | 45 | |
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[5823bae8] | 46 | #include <bsp/gr_leon4_n2x.h> |
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[ffd8002d] | 47 | |
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[a7267241] | 48 | #include <grlib_impl.h> |
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[ce76b9d2] | 49 | |
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[ffd8002d] | 50 | /* Determines which PCI address the AHB masters on the LEON-N2X board will |
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| 51 | * access when accessing the AHB to PCI window, it should be set so that the |
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| 52 | * masters can access the HOST RAM. |
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| 53 | * Default is base of HOST RAM, HOST RAM is mapped 1:1 to PCI memory space. |
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| 54 | */ |
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| 55 | extern unsigned int _RAM_START; |
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| 56 | #define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xc0000000) |
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| 57 | |
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| 58 | #define GRPCI2_BAR0_TO_AHB_MAP 0x04 |
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| 59 | #define GRPCI2_BAR1_TO_AHB_MAP 0x08 |
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| 60 | #define GRPCI2_BAR2_TO_AHB_MAP 0x0c |
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| 61 | #define GRPCI2_PCI_CONFIG 0x20 |
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| 62 | #define CAP9_AHBPREF_OFS 0x3c |
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| 63 | |
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| 64 | /* #define DEBUG 1 */ |
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| 65 | |
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| 66 | #ifdef DEBUG |
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| 67 | #define DBG(x...) printk(x) |
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| 68 | #else |
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| 69 | #define DBG(x...) |
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| 70 | #endif |
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| 71 | |
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| 72 | int gr_cpci_leon4_n2x_init1(struct drvmgr_dev *dev); |
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| 73 | int gr_cpci_leon4_n2x_init2(struct drvmgr_dev *dev); |
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[ef7a009] | 74 | void gr_cpci_leon4_n2x_isr(void *arg); |
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[ffd8002d] | 75 | |
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| 76 | struct grpci2_regs { |
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| 77 | volatile unsigned int ctrl; /* 0x00 */ |
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| 78 | volatile unsigned int sts_cap; /* 0x04 */ |
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| 79 | volatile unsigned int ppref; /* 0x08 */ |
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| 80 | volatile unsigned int io_map; /* 0x0C */ |
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| 81 | volatile unsigned int dma_ctrl; /* 0x10 */ |
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| 82 | volatile unsigned int dma_bdbase; /* 0x14 */ |
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| 83 | volatile unsigned int dma_chact; /* 0x18 */ |
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| 84 | int res1; /* 0x1C */ |
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| 85 | volatile unsigned int bars[6]; /* 0x20 */ |
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| 86 | int res2[2]; /* 0x38 */ |
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| 87 | volatile unsigned int ahbmst_map[16]; /* 0x40 */ |
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| 88 | }; |
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| 89 | |
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| 90 | /* Clock gating unit register layout */ |
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| 91 | struct l4n2x_grcg_regs { |
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| 92 | volatile unsigned int unlock; |
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| 93 | volatile unsigned int enable; |
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| 94 | volatile unsigned int reset; |
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| 95 | volatile unsigned int cpu_fpu; |
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| 96 | }; |
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| 97 | #define CG_MASK 0x1f |
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| 98 | |
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| 99 | /* Private data structure for driver */ |
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| 100 | struct gr_cpci_leon4_n2x_priv { |
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| 101 | /* Driver management */ |
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| 102 | struct drvmgr_dev *dev; |
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| 103 | char prefix[20]; |
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[ce76b9d2] | 104 | SPIN_DECLARE(devlock); |
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[ffd8002d] | 105 | |
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| 106 | /* PCI */ |
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| 107 | pci_dev_t pcidev; |
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| 108 | struct pci_dev_info *devinfo; |
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| 109 | uint32_t ahbmst2pci_map; |
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| 110 | |
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| 111 | /* IRQ */ |
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| 112 | int eirq; |
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| 113 | genirq_t genirq; |
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| 114 | |
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| 115 | /* GR-CPCI-LEON4-N2X */ |
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| 116 | unsigned int amba_freq_hz; |
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| 117 | unsigned int cg_en_mask; /* Enabled cores */ |
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| 118 | struct irqmp_regs *irq; |
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| 119 | struct l4n2x_grcg_regs *cg; /* Clock-gating unit */ |
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| 120 | struct grpci2_regs *grpci2; |
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| 121 | struct drvmgr_map_entry bus_maps_up[2]; |
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| 122 | struct drvmgr_map_entry bus_maps_down[4]; |
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| 123 | |
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| 124 | /* AMBA Plug&Play information on GR-CPCI-LEON4-N2X */ |
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| 125 | struct ambapp_bus abus; |
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| 126 | struct ambapp_mmap amba_maps[5]; |
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| 127 | struct ambapp_config config; |
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| 128 | }; |
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| 129 | |
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| 130 | int ambapp_leon4_n2x_int_register( |
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| 131 | struct drvmgr_dev *dev, |
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| 132 | int irq, |
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| 133 | const char *info, |
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| 134 | drvmgr_isr handler, |
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| 135 | void *arg); |
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| 136 | int ambapp_leon4_n2x_int_unregister( |
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| 137 | struct drvmgr_dev *dev, |
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| 138 | int irq, |
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| 139 | drvmgr_isr handler, |
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| 140 | void *arg); |
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| 141 | int ambapp_leon4_n2x_int_unmask( |
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| 142 | struct drvmgr_dev *dev, |
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| 143 | int irq); |
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| 144 | int ambapp_leon4_n2x_int_mask( |
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| 145 | struct drvmgr_dev *dev, |
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| 146 | int irq); |
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| 147 | int ambapp_leon4_n2x_int_clear( |
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| 148 | struct drvmgr_dev *dev, |
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| 149 | int irq); |
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| 150 | int ambapp_leon4_n2x_get_params( |
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| 151 | struct drvmgr_dev *dev, |
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| 152 | struct drvmgr_bus_params *params); |
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| 153 | |
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| 154 | static struct ambapp_ops ambapp_leon4_n2x_ops = { |
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| 155 | .int_register = ambapp_leon4_n2x_int_register, |
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| 156 | .int_unregister = ambapp_leon4_n2x_int_unregister, |
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| 157 | .int_unmask = ambapp_leon4_n2x_int_unmask, |
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| 158 | .int_mask = ambapp_leon4_n2x_int_mask, |
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| 159 | .int_clear = ambapp_leon4_n2x_int_clear, |
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| 160 | .get_params = ambapp_leon4_n2x_get_params |
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| 161 | }; |
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| 162 | |
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| 163 | struct drvmgr_drv_ops gr_cpci_leon4_n2x_ops = |
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| 164 | { |
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| 165 | .init = {gr_cpci_leon4_n2x_init1, gr_cpci_leon4_n2x_init2, NULL, NULL}, |
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| 166 | .remove = NULL, |
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| 167 | .info = NULL |
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| 168 | }; |
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| 169 | |
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| 170 | struct pci_dev_id_match gr_cpci_leon4_n2x_ids[] = |
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| 171 | { |
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| 172 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_LEON4_N2X), |
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[ab907e8e] | 173 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_NGMP_PROTO), |
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[ffd8002d] | 174 | PCIID_END_TABLE /* Mark end of table */ |
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| 175 | }; |
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| 176 | |
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| 177 | struct pci_drv_info gr_cpci_leon4_n2x_info = |
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| 178 | { |
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| 179 | { |
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| 180 | DRVMGR_OBJ_DRV, /* Driver */ |
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| 181 | NULL, /* Next driver */ |
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| 182 | NULL, /* Device list */ |
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| 183 | DRIVER_PCI_GAISLER_LEON4_N2X_ID,/* Driver ID */ |
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| 184 | "GR-CPCI-LEON4-N2X", /* Driver Name */ |
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| 185 | DRVMGR_BUS_TYPE_PCI, /* Bus Type */ |
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| 186 | &gr_cpci_leon4_n2x_ops, |
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| 187 | NULL, /* Funcs */ |
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| 188 | 0, /* No devices yet */ |
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| 189 | sizeof(struct gr_cpci_leon4_n2x_priv), |
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| 190 | }, |
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| 191 | &gr_cpci_leon4_n2x_ids[0] |
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| 192 | }; |
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| 193 | |
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| 194 | /* Driver resources configuration for the AMBA bus on the GR-CPCI-LEON4-N2X board. |
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| 195 | * It is declared weak so that the user may override it from the project file, |
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| 196 | * if the default settings are not enough. |
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| 197 | * |
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| 198 | * The configuration consists of an array of configuration pointers, each |
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| 199 | * pointer determine the configuration of one GR-CPCI-LEON4-N2X board. Pointer |
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| 200 | * zero is for board0, pointer 1 for board1 and so on. |
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| 201 | * |
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| 202 | * The array must end with a NULL pointer. |
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| 203 | */ |
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| 204 | struct drvmgr_bus_res *gr_leon4_n2x_resources[] __attribute__((weak)) = |
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| 205 | { |
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| 206 | NULL |
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| 207 | }; |
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| 208 | |
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| 209 | void gr_cpci_leon4_n2x_register_drv(void) |
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| 210 | { |
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| 211 | DBG("Registering GR-CPCI-LEON4-N2X PCI driver\n"); |
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| 212 | drvmgr_drv_register(&gr_cpci_leon4_n2x_info.general); |
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| 213 | } |
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| 214 | |
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| 215 | void gr_cpci_leon4_n2x_isr(void *arg) |
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| 216 | { |
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| 217 | struct gr_cpci_leon4_n2x_priv *priv = arg; |
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| 218 | unsigned int status, tmp; |
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| 219 | int irq, eirq; |
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[ce76b9d2] | 220 | SPIN_ISR_IRQFLAGS(irqflags); |
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| 221 | |
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[ffd8002d] | 222 | tmp = status = priv->irq->ipend; |
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| 223 | |
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| 224 | /* DBG("GR-CPCI-LEON4-N2X: IRQ 0x%x\n",status); */ |
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| 225 | |
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[ce76b9d2] | 226 | SPIN_LOCK(&priv->devlock, irqflags); |
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[ffd8002d] | 227 | for(irq = 0; irq < 32; irq++) { |
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| 228 | if (status & (1 << irq)) { |
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| 229 | if (irq == priv->eirq) { |
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| 230 | while ((eirq = priv->irq->intid[0] & 0x1f)) { |
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| 231 | if ((eirq & 0x10) == 0) |
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| 232 | continue; |
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| 233 | genirq_doirq(priv->genirq, eirq); |
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| 234 | priv->irq->iclear = (1 << eirq); |
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| 235 | } |
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| 236 | } else { |
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| 237 | genirq_doirq(priv->genirq, irq); |
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| 238 | } |
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| 239 | priv->irq->iclear = (1 << irq); |
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| 240 | status &= ~(1 << irq); |
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| 241 | if ( status == 0 ) |
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| 242 | break; |
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| 243 | } |
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| 244 | } |
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[ce76b9d2] | 245 | SPIN_UNLOCK(&priv->devlock, irqflags); |
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[ffd8002d] | 246 | |
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| 247 | /* ACK interrupt, this is because PCI is Level, so the IRQ Controller |
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| 248 | * still drives the IRQ |
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| 249 | */ |
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| 250 | if ( tmp ) |
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| 251 | drvmgr_interrupt_clear(priv->dev, 0); |
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| 252 | |
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[73b06e64] | 253 | DBG("GR-CPCI-LEON4-N2X-IRQ: 0x%x\n", tmp); |
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[ffd8002d] | 254 | } |
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| 255 | |
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[ef7a009] | 256 | static int gr_cpci_leon4_n2x_hw_init1(struct gr_cpci_leon4_n2x_priv *priv) |
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[ffd8002d] | 257 | { |
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| 258 | int i; |
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| 259 | uint32_t data; |
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| 260 | unsigned int ctrl; |
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| 261 | uint8_t tmp2; |
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| 262 | struct ambapp_dev *tmp; |
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| 263 | struct ambapp_ahb_info *ahb; |
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| 264 | uint8_t cap_ptr; |
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| 265 | pci_dev_t pcidev = priv->pcidev; |
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| 266 | struct pci_dev_info *devinfo = priv->devinfo; |
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| 267 | unsigned int cgmask, enabled; |
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| 268 | |
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| 269 | /* Check capabilities list bit and read its pointer */ |
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[9b292ea] | 270 | pci_cfg_r8(pcidev, PCIR_STATUS, &tmp2); |
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[ffd8002d] | 271 | if (!((tmp2 >> 4) & 1)) { |
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| 272 | /* Capabilities list not available which it should be in the GRPCI2 */ |
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| 273 | return -2; |
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| 274 | } |
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[9b292ea] | 275 | pci_cfg_r8(pcidev, PCIR_CAP_PTR, &cap_ptr); |
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[ffd8002d] | 276 | |
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| 277 | /* Workarounds depends on PCI revision of GR-CPCI-LEON4-N2X board */ |
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| 278 | switch (devinfo->rev) { |
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| 279 | case 0: |
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| 280 | /* Limit the AMBA prefetch for GRPCI2 version 0. */ |
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| 281 | pci_cfg_w32(pcidev, cap_ptr+CAP9_AHBPREF_OFS, 0); |
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| 282 | default: |
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| 283 | break; |
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| 284 | } |
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| 285 | |
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| 286 | /* Set AHB address mappings for target PCI bars |
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| 287 | * BAR0 maps to 0x00000000-0x07ffffff 128MB (SDRAM/DDR2 memory) |
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| 288 | * BAR1 maps to 0xf0000000-0xf7ffffff 128MB (L2-Cache regs/diagnostics) |
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| 289 | * BAR2 maps to 0xff800000-0xffffffff 8MB (PnP, I/O regs) |
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| 290 | */ |
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| 291 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR0_TO_AHB_MAP, 0x00000000); |
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| 292 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR1_TO_AHB_MAP, 0xf0000000); |
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| 293 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR2_TO_AHB_MAP, 0xff800000); |
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| 294 | |
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| 295 | /* Set PCI bus to be big endian */ |
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| 296 | pci_cfg_r32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, &data); |
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| 297 | data = data & 0xFFFFFFFE; |
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| 298 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, data); |
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| 299 | |
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| 300 | #if 0 |
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| 301 | /* set parity error response */ |
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[9b292ea] | 302 | pci_cfg_r32(pcidev, PCIR_COMMAND, &data); |
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| 303 | pci_cfg_w32(pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN)); |
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[ffd8002d] | 304 | #endif |
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| 305 | |
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| 306 | /* Scan AMBA Plug&Play */ |
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| 307 | |
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| 308 | /* AMBA MAP bar0 (in leon4-n2x) ==> 0x00000000 (remote amba address) */ |
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| 309 | priv->amba_maps[0].size = devinfo->resources[0].size; |
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| 310 | priv->amba_maps[0].local_adr = devinfo->resources[0].address; |
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| 311 | priv->amba_maps[0].remote_adr = 0x00000000; |
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| 312 | |
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| 313 | priv->amba_maps[1].size = devinfo->resources[1].size; |
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| 314 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
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| 315 | priv->amba_maps[1].remote_adr = 0xf0000000; |
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| 316 | |
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| 317 | priv->amba_maps[2].size = devinfo->resources[2].size; |
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| 318 | priv->amba_maps[2].local_adr = devinfo->resources[2].address; |
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| 319 | priv->amba_maps[2].remote_adr = 0xff800000; |
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| 320 | |
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| 321 | /* Addresses not matching with map be untouched */ |
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| 322 | priv->amba_maps[3].size = 0xfffffff0; |
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| 323 | priv->amba_maps[3].local_adr = 0; |
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| 324 | priv->amba_maps[3].remote_adr = 0; |
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| 325 | |
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| 326 | /* Mark end of table */ |
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| 327 | priv->amba_maps[4].size=0; |
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| 328 | |
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| 329 | /* Start AMBA PnP scan at first AHB bus */ |
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| 330 | ambapp_scan( |
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| 331 | &priv->abus, |
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| 332 | devinfo->resources[2].address + 0x00700000, |
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| 333 | NULL, |
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| 334 | &priv->amba_maps[0]); |
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| 335 | |
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| 336 | /* Initialize Frequency of AMBA bus */ |
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| 337 | ambapp_freq_init(&priv->abus, NULL, priv->amba_freq_hz); |
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| 338 | |
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| 339 | /* Find IRQ controller, Clear all current IRQs */ |
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| 340 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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| 341 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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| 342 | VENDOR_GAISLER, GAISLER_IRQMP, |
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| 343 | ambapp_find_by_idx, NULL); |
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| 344 | if ( !tmp ) { |
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| 345 | return -4; |
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| 346 | } |
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| 347 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
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| 348 | /* Set up GR-CPCI-LEON4-N2X irq controller |
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| 349 | * Interrupts are routed from IRQCtrl0, we leave the configuration |
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| 350 | * for the other CPUs, as the board's CPUs may be running something. |
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| 351 | * We assume IRQCtrl has been set up properly, or at least the reset |
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| 352 | * values shuold work with this code.. |
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| 353 | */ |
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| 354 | priv->irq->mask[0] = 0; |
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| 355 | priv->irq->iforce = 0; |
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| 356 | priv->irq->force[0] = 0; |
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| 357 | priv->irq->ilevel = 0; |
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| 358 | priv->irq->ipend = 0; |
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| 359 | priv->irq->iclear = 0xffffffff; |
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| 360 | priv->irq->ilevel = 0; |
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| 361 | /* Get extended Interrupt controller IRQ number */ |
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| 362 | priv->eirq = (priv->irq->mpstat >> 16) & 0xf; |
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| 363 | |
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[ab907e8e] | 364 | /* Find first Clock-Gating unit, enable/disable the requested cores. |
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| 365 | * It is optional in order to support FPGA prototypes. |
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| 366 | */ |
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| 367 | priv->cg = NULL; |
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[ffd8002d] | 368 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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| 369 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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| 370 | VENDOR_GAISLER, GAISLER_CLKGATE, |
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| 371 | ambapp_find_by_idx, NULL); |
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[ab907e8e] | 372 | if (tmp) |
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| 373 | priv->cg = (struct l4n2x_grcg_regs *)DEV_TO_APB(tmp)->start; |
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| 374 | |
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[ffd8002d] | 375 | /* Do reset and enable sequence only if not already enabled */ |
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| 376 | if (priv->cg && ((enabled = priv->cg->enable) != priv->cg_en_mask)) { |
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| 377 | /* First disable already enabled cores */ |
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| 378 | cgmask = ~priv->cg_en_mask & enabled; |
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| 379 | if (cgmask) { |
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| 380 | priv->cg->unlock = cgmask; |
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| 381 | priv->cg->enable = enabled = ~cgmask & enabled; |
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| 382 | priv->cg->unlock = 0; |
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| 383 | } |
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| 384 | /* Enable disabled cores */ |
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| 385 | cgmask = priv->cg_en_mask & ~enabled; |
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| 386 | if (cgmask) { |
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| 387 | priv->cg->unlock = cgmask; |
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| 388 | priv->cg->reset |= cgmask; |
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| 389 | priv->cg->enable = cgmask | enabled; |
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| 390 | priv->cg->reset &= ~cgmask; |
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| 391 | priv->cg->unlock = 0; |
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| 392 | } |
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| 393 | } |
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| 394 | |
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| 395 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
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| 396 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
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| 397 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
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| 398 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
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| 399 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
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| 400 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
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| 401 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
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| 402 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
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| 403 | priv->bus_maps_down[2].name = "PCI BAR2 -> AMBA"; |
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| 404 | priv->bus_maps_down[2].size = priv->amba_maps[2].size; |
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| 405 | priv->bus_maps_down[2].from_adr = (void *)priv->amba_maps[2].local_adr; |
---|
| 406 | priv->bus_maps_down[2].to_adr = (void *)priv->amba_maps[2].remote_adr; |
---|
| 407 | priv->bus_maps_down[3].size = 0; |
---|
| 408 | |
---|
| 409 | /* Find GRPCI2 controller AHB Slave interface */ |
---|
[ef7a009] | 410 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
---|
[ffd8002d] | 411 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
---|
| 412 | VENDOR_GAISLER, GAISLER_GRPCI2, |
---|
| 413 | ambapp_find_by_idx, NULL); |
---|
| 414 | if ( !tmp ) { |
---|
| 415 | return -6; |
---|
| 416 | } |
---|
| 417 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
---|
| 418 | priv->bus_maps_up[0].name = "AMBA GRPCI2 Window"; |
---|
| 419 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-CPCI-LEON4-N2X board */ |
---|
| 420 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
---|
| 421 | priv->bus_maps_up[0].to_adr = (void *) |
---|
| 422 | (priv->ahbmst2pci_map & ~(ahb->mask[0]-1)); |
---|
| 423 | priv->bus_maps_up[1].size = 0; |
---|
| 424 | |
---|
| 425 | /* Find GRPCI2 controller APB Slave interface */ |
---|
[ef7a009] | 426 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
---|
[ffd8002d] | 427 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
---|
| 428 | VENDOR_GAISLER, GAISLER_GRPCI2, |
---|
| 429 | ambapp_find_by_idx, NULL); |
---|
| 430 | if ( !tmp ) { |
---|
| 431 | return -7; |
---|
| 432 | } |
---|
| 433 | priv->grpci2 = (struct grpci2_regs *) |
---|
| 434 | ((struct ambapp_apb_info *)tmp->devinfo)->start; |
---|
| 435 | |
---|
| 436 | /* Workarounds depends on PCI revision of GR-CPCI-LEON4-N2X board */ |
---|
| 437 | switch (devinfo->rev) { |
---|
| 438 | case 0: |
---|
| 439 | /* Limit the PCI master prefetch for GRPCI2 version 0. |
---|
| 440 | * This fix is required only when PCI Host bridge is |
---|
| 441 | * GRPCI2 rev 0. |
---|
| 442 | */ |
---|
| 443 | priv->grpci2->ppref = 0xffff0000; |
---|
| 444 | default: |
---|
| 445 | break; |
---|
| 446 | } |
---|
| 447 | |
---|
| 448 | /* Set AHB to PCI mapping for all AMBA AHB masters */ |
---|
| 449 | for(i = 0; i < 16; i++) { |
---|
| 450 | priv->grpci2->ahbmst_map[i] = priv->ahbmst2pci_map & |
---|
| 451 | ~(ahb->mask[0]-1); |
---|
| 452 | } |
---|
| 453 | |
---|
| 454 | /* Make sure dirq(0) sampling is enabled */ |
---|
| 455 | ctrl = priv->grpci2->ctrl; |
---|
| 456 | ctrl = (ctrl & 0xFFFFFF0F) | (1 << 4); |
---|
| 457 | priv->grpci2->ctrl = ctrl; |
---|
| 458 | |
---|
| 459 | /* Successfully registered the LEON4-N2X board */ |
---|
| 460 | return 0; |
---|
| 461 | } |
---|
| 462 | |
---|
[ef7a009] | 463 | static int gr_cpci_leon4_n2x_hw_init2(struct gr_cpci_leon4_n2x_priv *priv) |
---|
[ffd8002d] | 464 | { |
---|
| 465 | /* Enable DMA by enabling PCI target as master */ |
---|
| 466 | pci_master_enable(priv->pcidev); |
---|
| 467 | |
---|
| 468 | return DRVMGR_OK; |
---|
| 469 | } |
---|
| 470 | |
---|
| 471 | /* Called when a PCI target is found with the PCI device and vendor ID |
---|
| 472 | * given in gr_cpci_leon4_n2x_ids[]. |
---|
| 473 | */ |
---|
| 474 | int gr_cpci_leon4_n2x_init1(struct drvmgr_dev *dev) |
---|
| 475 | { |
---|
| 476 | struct gr_cpci_leon4_n2x_priv *priv; |
---|
| 477 | struct pci_dev_info *devinfo; |
---|
| 478 | int status, i; |
---|
| 479 | union drvmgr_key_value *value; |
---|
[ef7a009] | 480 | int resources_cnt; |
---|
[ffd8002d] | 481 | |
---|
| 482 | priv = dev->priv; |
---|
| 483 | if (!priv) |
---|
| 484 | return DRVMGR_NOMEM; |
---|
| 485 | |
---|
| 486 | memset(priv, 0, sizeof(*priv)); |
---|
| 487 | dev->priv = priv; |
---|
| 488 | priv->dev = dev; |
---|
| 489 | |
---|
| 490 | /* Determine number of configurations */ |
---|
[ef7a009] | 491 | resources_cnt = get_resarray_count(gr_leon4_n2x_resources); |
---|
[ffd8002d] | 492 | |
---|
| 493 | /* Generate Device prefix */ |
---|
| 494 | |
---|
| 495 | strcpy(priv->prefix, "/dev/leon4n2x0"); |
---|
| 496 | priv->prefix[13] += dev->minor_drv; |
---|
| 497 | mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO); |
---|
| 498 | priv->prefix[14] = '/'; |
---|
| 499 | priv->prefix[15] = '\0'; |
---|
| 500 | |
---|
| 501 | priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo; |
---|
| 502 | priv->pcidev = devinfo->pcidev; |
---|
[56a7540] | 503 | printk("\n\n--- GR-CPCI-LEON4-N2X[%d] ---\n", dev->minor_drv); |
---|
| 504 | printk(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n", |
---|
[ffd8002d] | 505 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
[56a7540] | 506 | printk(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n", |
---|
[ffd8002d] | 507 | devinfo->id.vendor, devinfo->id.device); |
---|
| 508 | for (i = 0; i < 3; i++) { |
---|
[c05d7a9d] | 509 | printk(" PCI BAR[%d]: 0x%08" PRIx32 " - 0x%08" PRIx32 "\n", |
---|
[ffd8002d] | 510 | i, devinfo->resources[i].address, |
---|
| 511 | devinfo->resources[i].address + |
---|
| 512 | (devinfo->resources[i].size - 1)); |
---|
| 513 | /* all neccessary space assigned to GR-CPCI-LEON4-N2X target? */ |
---|
| 514 | if (devinfo->resources[i].size == 0) |
---|
| 515 | return DRVMGR_ENORES; |
---|
| 516 | } |
---|
[56a7540] | 517 | printk(" IRQ: %d\n\n\n", devinfo->irq); |
---|
[ffd8002d] | 518 | |
---|
[ce76b9d2] | 519 | /* Initialize spin-lock for this PCI perihperal device. This is to |
---|
| 520 | * protect the Interrupt Controller Registers. The genirq layer is |
---|
| 521 | * protecting its own internals and ISR dispatching. |
---|
| 522 | */ |
---|
| 523 | SPIN_INIT(&priv->devlock, priv->prefix); |
---|
| 524 | |
---|
[ffd8002d] | 525 | /* Let user override which PCI address the AHB masters of the |
---|
| 526 | * LEON4-N2X board access when doing DMA to HOST RAM. The AHB masters |
---|
| 527 | * access the PCI Window of the AMBA bus, the MSB 2-bits of that address |
---|
| 528 | * is translated according this config option before the address goes |
---|
| 529 | * out on the PCI bus. |
---|
| 530 | * |
---|
| 531 | * Only the 2 MSB bits have an effect. |
---|
| 532 | */ |
---|
[4d3e70f4] | 533 | value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", DRVMGR_KT_INT); |
---|
[ffd8002d] | 534 | if (value) |
---|
| 535 | priv->ahbmst2pci_map = value->i; |
---|
| 536 | else |
---|
| 537 | priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */ |
---|
| 538 | |
---|
| 539 | /* Let user override the default AMBA system frequency of the |
---|
| 540 | * CPU-bus of the remote GR-CPCI-LEON4-N2X. Default is 200MHz. |
---|
| 541 | */ |
---|
[4d3e70f4] | 542 | value = drvmgr_dev_key_get(priv->dev, "ambaFreq", DRVMGR_KT_INT); |
---|
[ffd8002d] | 543 | if (value) |
---|
| 544 | priv->amba_freq_hz = value->i; |
---|
| 545 | else |
---|
| 546 | priv->amba_freq_hz = 200000000; /* default */ |
---|
| 547 | |
---|
| 548 | /* Let user determine clock-gating unit configuration. The default |
---|
| 549 | * is to turn all cores on (disable gating). PCI is always turned ON. |
---|
| 550 | */ |
---|
[4d3e70f4] | 551 | value = drvmgr_dev_key_get(priv->dev, "cgEnMask", DRVMGR_KT_INT); |
---|
[ffd8002d] | 552 | if (value) |
---|
| 553 | priv->cg_en_mask = (value->i & CG_MASK) | 0x08; |
---|
| 554 | else |
---|
| 555 | priv->cg_en_mask = CG_MASK; /* default all ON */ |
---|
| 556 | |
---|
| 557 | priv->genirq = genirq_init(32); |
---|
| 558 | if (priv->genirq == NULL) |
---|
| 559 | return DRVMGR_FAIL; |
---|
| 560 | |
---|
| 561 | if ((status = gr_cpci_leon4_n2x_hw_init1(priv)) != 0) { |
---|
| 562 | genirq_destroy(priv->genirq); |
---|
[56a7540] | 563 | printk(" Failed to initialize GR-CPCI-LEON4-N2X HW: %d\n", status); |
---|
[ffd8002d] | 564 | return DRVMGR_FAIL; |
---|
| 565 | } |
---|
| 566 | |
---|
| 567 | /* Init amba bus */ |
---|
| 568 | priv->config.abus = &priv->abus; |
---|
| 569 | priv->config.ops = &ambapp_leon4_n2x_ops; |
---|
| 570 | priv->config.maps_up = &priv->bus_maps_up[0]; |
---|
| 571 | priv->config.maps_down = &priv->bus_maps_down[0]; |
---|
[ef7a009] | 572 | if ( priv->dev->minor_drv < resources_cnt ) { |
---|
[ffd8002d] | 573 | priv->config.resources = gr_leon4_n2x_resources[priv->dev->minor_drv]; |
---|
| 574 | } else { |
---|
| 575 | priv->config.resources = NULL; |
---|
| 576 | } |
---|
| 577 | |
---|
| 578 | /* Create and register AMBA PnP bus. */ |
---|
| 579 | return ambapp_bus_register(dev, &priv->config); |
---|
| 580 | } |
---|
| 581 | |
---|
| 582 | int gr_cpci_leon4_n2x_init2(struct drvmgr_dev *dev) |
---|
| 583 | { |
---|
| 584 | struct gr_cpci_leon4_n2x_priv *priv = dev->priv; |
---|
| 585 | |
---|
| 586 | /* Clear any old interrupt requests */ |
---|
| 587 | drvmgr_interrupt_clear(dev, 0); |
---|
| 588 | |
---|
| 589 | /* Enable System IRQ so that GR-CPCI-LEON4-N2X PCI target interrupt |
---|
| 590 | * goes through. |
---|
| 591 | * |
---|
| 592 | * It is important to enable it in stage init2. If interrupts were |
---|
| 593 | * enabled in init1 this might hang the system when more than one |
---|
| 594 | * PCI board is connected, this is because PCI interrupts might |
---|
| 595 | * be shared and PCI board 2 have not initialized and |
---|
| 596 | * might therefore drive interrupt already when entering init1(). |
---|
| 597 | */ |
---|
| 598 | drvmgr_interrupt_register( |
---|
| 599 | dev, |
---|
| 600 | 0, |
---|
| 601 | "gr_cpci_leon4_n2x", |
---|
| 602 | gr_cpci_leon4_n2x_isr, |
---|
| 603 | (void *)priv); |
---|
| 604 | |
---|
| 605 | return gr_cpci_leon4_n2x_hw_init2(priv); |
---|
| 606 | } |
---|
| 607 | |
---|
| 608 | int ambapp_leon4_n2x_int_register( |
---|
| 609 | struct drvmgr_dev *dev, |
---|
| 610 | int irq, |
---|
| 611 | const char *info, |
---|
| 612 | drvmgr_isr handler, |
---|
| 613 | void *arg) |
---|
| 614 | { |
---|
| 615 | struct gr_cpci_leon4_n2x_priv *priv = dev->parent->dev->priv; |
---|
[ce76b9d2] | 616 | SPIN_IRQFLAGS(irqflags); |
---|
[ffd8002d] | 617 | int status; |
---|
[ce76b9d2] | 618 | void *h; |
---|
[ffd8002d] | 619 | |
---|
[ce76b9d2] | 620 | h = genirq_alloc_handler(handler, arg); |
---|
| 621 | if ( h == NULL ) |
---|
| 622 | return DRVMGR_FAIL; |
---|
[ffd8002d] | 623 | |
---|
[ce76b9d2] | 624 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
| 625 | |
---|
| 626 | status = genirq_register(priv->genirq, irq, h); |
---|
[ffd8002d] | 627 | if (status == 0) { |
---|
| 628 | /* Clear IRQ for first registered handler */ |
---|
| 629 | priv->irq->iclear = (1<<irq); |
---|
| 630 | } else if (status == 1) |
---|
| 631 | status = 0; |
---|
| 632 | |
---|
| 633 | if (status != 0) { |
---|
[ce76b9d2] | 634 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
| 635 | genirq_free_handler(h); |
---|
[ffd8002d] | 636 | return DRVMGR_FAIL; |
---|
| 637 | } |
---|
| 638 | |
---|
| 639 | status = genirq_enable(priv->genirq, irq, handler, arg); |
---|
| 640 | if ( status == 0 ) { |
---|
| 641 | /* Enable IRQ for first enabled handler only */ |
---|
| 642 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
| 643 | } else if ( status == 1 ) |
---|
| 644 | status = 0; |
---|
| 645 | |
---|
[ce76b9d2] | 646 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
[ffd8002d] | 647 | |
---|
| 648 | return status; |
---|
| 649 | } |
---|
| 650 | |
---|
| 651 | int ambapp_leon4_n2x_int_unregister( |
---|
| 652 | struct drvmgr_dev *dev, |
---|
| 653 | int irq, |
---|
| 654 | drvmgr_isr isr, |
---|
| 655 | void *arg) |
---|
| 656 | { |
---|
| 657 | struct gr_cpci_leon4_n2x_priv *priv = dev->parent->dev->priv; |
---|
[ce76b9d2] | 658 | SPIN_IRQFLAGS(irqflags); |
---|
[ffd8002d] | 659 | int status; |
---|
[ce76b9d2] | 660 | void *handler; |
---|
[ffd8002d] | 661 | |
---|
[ce76b9d2] | 662 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
[ffd8002d] | 663 | |
---|
| 664 | status = genirq_disable(priv->genirq, irq, isr, arg); |
---|
| 665 | if ( status == 0 ) { |
---|
| 666 | /* Disable IRQ only when no enabled handler exists */ |
---|
| 667 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
| 668 | } |
---|
| 669 | |
---|
[ce76b9d2] | 670 | handler = genirq_unregister(priv->genirq, irq, isr, arg); |
---|
| 671 | if ( handler == NULL ) |
---|
[ffd8002d] | 672 | status = DRVMGR_FAIL; |
---|
[ce76b9d2] | 673 | else |
---|
| 674 | status = DRVMGR_OK; |
---|
| 675 | |
---|
| 676 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
[ffd8002d] | 677 | |
---|
[ce76b9d2] | 678 | if (handler) |
---|
| 679 | genirq_free_handler(handler); |
---|
[ffd8002d] | 680 | |
---|
| 681 | return status; |
---|
| 682 | } |
---|
| 683 | |
---|
| 684 | int ambapp_leon4_n2x_int_unmask( |
---|
| 685 | struct drvmgr_dev *dev, |
---|
| 686 | int irq) |
---|
| 687 | { |
---|
| 688 | struct gr_cpci_leon4_n2x_priv *priv = dev->parent->dev->priv; |
---|
[ce76b9d2] | 689 | SPIN_IRQFLAGS(irqflags); |
---|
[ffd8002d] | 690 | |
---|
| 691 | DBG("LEON4-N2X IRQ %d: unmask\n", irq); |
---|
| 692 | |
---|
| 693 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 694 | return DRVMGR_EINVAL; |
---|
| 695 | |
---|
[ce76b9d2] | 696 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
[ffd8002d] | 697 | |
---|
| 698 | /* Enable IRQ for first enabled handler only */ |
---|
| 699 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
| 700 | |
---|
[ce76b9d2] | 701 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
[ffd8002d] | 702 | |
---|
| 703 | return DRVMGR_OK; |
---|
| 704 | } |
---|
| 705 | |
---|
| 706 | int ambapp_leon4_n2x_int_mask( |
---|
| 707 | struct drvmgr_dev *dev, |
---|
| 708 | int irq) |
---|
| 709 | { |
---|
| 710 | struct gr_cpci_leon4_n2x_priv *priv = dev->parent->dev->priv; |
---|
[ce76b9d2] | 711 | SPIN_IRQFLAGS(irqflags); |
---|
[ffd8002d] | 712 | |
---|
| 713 | DBG("LEON4-N2X IRQ %d: mask\n", irq); |
---|
| 714 | |
---|
| 715 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 716 | return DRVMGR_EINVAL; |
---|
| 717 | |
---|
[ce76b9d2] | 718 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
[ffd8002d] | 719 | |
---|
| 720 | /* Disable/mask IRQ */ |
---|
| 721 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
| 722 | |
---|
[ce76b9d2] | 723 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
[ffd8002d] | 724 | |
---|
| 725 | return DRVMGR_OK; |
---|
| 726 | } |
---|
| 727 | |
---|
| 728 | int ambapp_leon4_n2x_int_clear( |
---|
| 729 | struct drvmgr_dev *dev, |
---|
| 730 | int irq) |
---|
| 731 | { |
---|
| 732 | struct gr_cpci_leon4_n2x_priv *priv = dev->parent->dev->priv; |
---|
| 733 | |
---|
| 734 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 735 | return DRVMGR_EINVAL; |
---|
| 736 | |
---|
| 737 | priv->irq->iclear = (1<<irq); |
---|
| 738 | |
---|
| 739 | return DRVMGR_OK; |
---|
| 740 | } |
---|
| 741 | |
---|
| 742 | int ambapp_leon4_n2x_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
---|
| 743 | { |
---|
| 744 | struct gr_cpci_leon4_n2x_priv *priv = dev->parent->dev->priv; |
---|
| 745 | |
---|
| 746 | /* Device name prefix pointer, skip /dev */ |
---|
| 747 | params->dev_prefix = &priv->prefix[5]; |
---|
| 748 | |
---|
| 749 | return 0; |
---|
| 750 | } |
---|
| 751 | |
---|
| 752 | void gr_cpci_leon4_n2x_print_dev(struct drvmgr_dev *dev, int options) |
---|
| 753 | { |
---|
| 754 | struct gr_cpci_leon4_n2x_priv *priv = dev->priv; |
---|
| 755 | struct pci_dev_info *devinfo = priv->devinfo; |
---|
| 756 | uint32_t bar0, bar0_size; |
---|
| 757 | |
---|
| 758 | /* Print */ |
---|
| 759 | printf("--- GR-CPCI-LEON4-N2X [bus 0x%x, dev 0x%x, fun 0x%x] ---\n", |
---|
| 760 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
| 761 | |
---|
| 762 | bar0 = devinfo->resources[0].address; |
---|
| 763 | bar0_size = devinfo->resources[0].size; |
---|
[c05d7a9d] | 764 | printf(" PCI BAR[0]: 0x%" PRIx32 " - 0x%" PRIx32 "\n", |
---|
| 765 | bar0, bar0 + bar0_size - 1); |
---|
| 766 | printf(" IRQ REGS: 0x%" PRIxPTR "\n", (uintptr_t)priv->irq); |
---|
[ffd8002d] | 767 | printf(" IRQ: %d\n", devinfo->irq); |
---|
| 768 | printf(" PCI REVISION: %d\n", devinfo->rev); |
---|
| 769 | printf(" FREQ: %d Hz\n", priv->amba_freq_hz); |
---|
| 770 | printf(" IMASK: 0x%08x\n", priv->irq->mask[0]); |
---|
| 771 | printf(" IPEND: 0x%08x\n", priv->irq->ipend); |
---|
| 772 | |
---|
| 773 | /* Print amba config */ |
---|
| 774 | if (options & GR_LEON4_N2X_OPTIONS_AMBA) |
---|
| 775 | ambapp_print(&priv->abus, 10); |
---|
| 776 | } |
---|
| 777 | |
---|
| 778 | void gr_leon4_n2x_print(int options) |
---|
| 779 | { |
---|
| 780 | struct pci_drv_info *drv = &gr_cpci_leon4_n2x_info; |
---|
| 781 | struct drvmgr_dev *dev; |
---|
| 782 | |
---|
| 783 | dev = drv->general.dev; |
---|
| 784 | while(dev) { |
---|
| 785 | gr_cpci_leon4_n2x_print_dev(dev, options); |
---|
| 786 | dev = dev->next_in_drv; |
---|
| 787 | } |
---|
| 788 | } |
---|