1 | /* GR-CPCI-GR740 PCI Target driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2017. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | * Configures the GR-CPCI-GR740 interface PCI board in peripheral |
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11 | * mode. This driver provides a AMBA PnP bus by using the general part |
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12 | * of the AMBA PnP bus driver (ambapp_bus.c). Based on the |
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13 | * GR-RASTA-IO driver. |
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14 | * |
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15 | * |
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16 | * Driver resource options: |
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17 | * NAME DEFAULT VALUE |
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18 | * ahbmst2pci _RAM_START AMBA->PCI translation PCI base address |
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19 | * ambaFreq 250000000 (250MHz) AMBA system frequency of GR740 |
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20 | * cgEnMask 0x1f (all) Clock gating enable mask |
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21 | * bar0 0x00000000 L2-Cache SDRAM memory |
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22 | * bar1 0xf0000000 L2-Cache registers |
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23 | * |
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24 | * TODO/UNTESTED |
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25 | * Interrupt testing |
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26 | */ |
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27 | |
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28 | #include <stdio.h> |
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29 | #include <stdlib.h> |
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30 | #include <string.h> |
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31 | #include <sys/types.h> |
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32 | #include <sys/stat.h> |
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33 | |
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34 | #include <bsp.h> |
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35 | #include <rtems/bspIo.h> |
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36 | #include <rtems/score/isrlock.h> /* spin-lock */ |
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37 | #include <pci.h> |
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38 | |
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39 | #include <ambapp.h> |
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40 | #include <grlib.h> |
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41 | #include <drvmgr/drvmgr.h> |
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42 | #include <drvmgr/ambapp_bus.h> |
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43 | #include <drvmgr/pci_bus.h> |
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44 | #include <drvmgr/bspcommon.h> |
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45 | #include <bsp/genirq.h> |
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46 | |
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47 | #include <bsp/gr_cpci_gr740.h> |
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48 | |
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49 | /* map via rtems_interrupt_lock_* API: */ |
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50 | #define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock) |
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51 | #define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name) |
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52 | #define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level) |
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53 | #define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level) |
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54 | #define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level) |
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55 | #define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level) |
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56 | #define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k |
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57 | #define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k) |
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58 | |
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59 | /* Determines which PCI address the AHB masters on the GR740 board will |
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60 | * access when accessing the AHB to PCI window, it should be set so that the |
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61 | * masters can access the HOST RAM. |
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62 | * Default is base of HOST RAM, HOST RAM is mapped 1:1 to PCI memory space. |
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63 | */ |
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64 | extern unsigned int _RAM_START; |
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65 | #define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xc0000000) |
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66 | |
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67 | #define GRPCI2_BAR0_TO_AHB_MAP 0x04 |
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68 | #define GRPCI2_BAR1_TO_AHB_MAP 0x08 |
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69 | #define GRPCI2_BAR2_TO_AHB_MAP 0x0c |
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70 | #define GRPCI2_PCI_CONFIG 0x20 |
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71 | #define CAP9_AHBPREF_OFS 0x3c |
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72 | |
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73 | /* #define DEBUG 1 */ |
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74 | |
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75 | #ifdef DEBUG |
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76 | #define DBG(x...) printk(x) |
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77 | #else |
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78 | #define DBG(x...) |
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79 | #endif |
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80 | |
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81 | int gr_cpci_gr740_init1(struct drvmgr_dev *dev); |
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82 | int gr_cpci_gr740_init2(struct drvmgr_dev *dev); |
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83 | void gr_cpci_gr740_isr(void *arg); |
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84 | |
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85 | struct grpci2_regs { |
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86 | volatile unsigned int ctrl; /* 0x00 */ |
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87 | volatile unsigned int sts_cap; /* 0x04 */ |
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88 | volatile unsigned int ppref; /* 0x08 */ |
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89 | volatile unsigned int io_map; /* 0x0C */ |
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90 | volatile unsigned int dma_ctrl; /* 0x10 */ |
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91 | volatile unsigned int dma_bdbase; /* 0x14 */ |
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92 | volatile unsigned int dma_chact; /* 0x18 */ |
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93 | int res1; /* 0x1C */ |
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94 | volatile unsigned int bars[6]; /* 0x20 */ |
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95 | int res2[2]; /* 0x38 */ |
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96 | volatile unsigned int ahbmst_map[16]; /* 0x40 */ |
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97 | }; |
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98 | |
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99 | /* Clock gating unit register layout */ |
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100 | struct gr740_grcg_regs { |
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101 | volatile unsigned int unlock; |
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102 | volatile unsigned int enable; |
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103 | volatile unsigned int reset; |
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104 | volatile unsigned int cpu_fpu; |
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105 | }; |
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106 | #define CG_MASK 0x3ff |
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107 | |
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108 | /* Private data structure for driver */ |
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109 | struct gr_cpci_gr740_priv { |
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110 | /* Driver management */ |
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111 | struct drvmgr_dev *dev; |
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112 | char prefix[16]; |
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113 | SPIN_DECLARE(devlock); |
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114 | |
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115 | /* PCI */ |
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116 | pci_dev_t pcidev; |
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117 | struct pci_dev_info *devinfo; |
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118 | uint32_t ahbmst2pci_map; |
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119 | |
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120 | /* IRQ */ |
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121 | int eirq; |
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122 | genirq_t genirq; |
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123 | |
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124 | /* GR-CPCI-GR740 */ |
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125 | unsigned int amba_freq_hz; |
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126 | unsigned int cg_en_mask; /* Enabled cores */ |
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127 | struct irqmp_regs *irq; |
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128 | struct gr740_grcg_regs *cg; /* Clock-gating unit */ |
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129 | struct grpci2_regs *grpci2; |
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130 | struct drvmgr_map_entry bus_maps_up[2]; |
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131 | struct drvmgr_map_entry bus_maps_down[4]; |
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132 | |
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133 | /* AMBA Plug&Play information on GR-CPCI-GR740 */ |
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134 | struct ambapp_bus abus; |
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135 | struct ambapp_mmap amba_maps[5]; |
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136 | struct ambapp_config config; |
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137 | }; |
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138 | |
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139 | int ambapp_gr740_int_register( |
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140 | struct drvmgr_dev *dev, |
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141 | int irq, |
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142 | const char *info, |
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143 | drvmgr_isr handler, |
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144 | void *arg); |
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145 | int ambapp_gr740_int_unregister( |
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146 | struct drvmgr_dev *dev, |
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147 | int irq, |
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148 | drvmgr_isr handler, |
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149 | void *arg); |
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150 | int ambapp_gr740_int_unmask( |
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151 | struct drvmgr_dev *dev, |
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152 | int irq); |
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153 | int ambapp_gr740_int_mask( |
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154 | struct drvmgr_dev *dev, |
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155 | int irq); |
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156 | int ambapp_gr740_int_clear( |
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157 | struct drvmgr_dev *dev, |
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158 | int irq); |
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159 | int ambapp_gr740_get_params( |
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160 | struct drvmgr_dev *dev, |
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161 | struct drvmgr_bus_params *params); |
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162 | |
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163 | static struct ambapp_ops ambapp_gr740_ops = { |
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164 | .int_register = ambapp_gr740_int_register, |
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165 | .int_unregister = ambapp_gr740_int_unregister, |
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166 | .int_unmask = ambapp_gr740_int_unmask, |
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167 | .int_mask = ambapp_gr740_int_mask, |
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168 | .int_clear = ambapp_gr740_int_clear, |
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169 | .get_params = ambapp_gr740_get_params |
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170 | }; |
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171 | |
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172 | struct drvmgr_drv_ops gr_cpci_gr740_ops = |
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173 | { |
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174 | .init = {gr_cpci_gr740_init1, gr_cpci_gr740_init2, NULL, NULL}, |
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175 | .remove = NULL, |
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176 | .info = NULL |
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177 | }; |
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178 | |
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179 | struct pci_dev_id_match gr_cpci_gr740_ids[] = |
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180 | { |
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181 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_CPCI_GR740), |
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182 | PCIID_END_TABLE /* Mark end of table */ |
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183 | }; |
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184 | |
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185 | struct pci_drv_info gr_cpci_gr740_info = |
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186 | { |
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187 | { |
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188 | DRVMGR_OBJ_DRV, /* Driver */ |
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189 | NULL, /* Next driver */ |
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190 | NULL, /* Device list */ |
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191 | DRIVER_PCI_GAISLER_CPCI_GR740_ID, /* Driver ID */ |
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192 | "GR-CPCI-GR740", /* Driver Name */ |
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193 | DRVMGR_BUS_TYPE_PCI, /* Bus Type */ |
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194 | &gr_cpci_gr740_ops, |
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195 | NULL, /* Funcs */ |
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196 | 0, /* No devices yet */ |
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197 | sizeof(struct gr_cpci_gr740_priv), |
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198 | }, |
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199 | &gr_cpci_gr740_ids[0] |
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200 | }; |
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201 | |
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202 | /* Driver resources configuration for the AMBA bus on the GR-CPCI-GR740 board. |
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203 | * It is declared weak so that the user may override it from the project file, |
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204 | * if the default settings are not enough. |
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205 | * |
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206 | * The configuration consists of an array of configuration pointers, each |
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207 | * pointer determine the configuration of one GR-CPCI-GR740 board. Pointer |
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208 | * zero is for board0, pointer 1 for board1 and so on. |
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209 | * |
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210 | * The array must end with a NULL pointer. |
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211 | */ |
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212 | struct drvmgr_bus_res *gr_cpci_gr740_resources[] __attribute__((weak)) = |
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213 | { |
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214 | NULL |
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215 | }; |
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216 | |
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217 | void gr_cpci_gr740_register_drv(void) |
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218 | { |
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219 | DBG("Registering GR-CPCI-GR740 PCI driver\n"); |
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220 | drvmgr_drv_register(&gr_cpci_gr740_info.general); |
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221 | } |
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222 | |
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223 | void gr_cpci_gr740_isr(void *arg) |
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224 | { |
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225 | struct gr_cpci_gr740_priv *priv = arg; |
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226 | unsigned int status, tmp; |
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227 | int irq, eirq; |
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228 | SPIN_ISR_IRQFLAGS(irqflags); |
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229 | |
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230 | tmp = status = priv->irq->ipend; |
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231 | |
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232 | /* DBG("GR-CPCI-GR740: IRQ 0x%x\n",status); */ |
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233 | |
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234 | SPIN_LOCK(&priv->devlock, irqflags); |
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235 | for(irq = 0; irq < 32; irq++) { |
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236 | if (status & (1 << irq)) { |
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237 | if (irq == priv->eirq) { |
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238 | while ((eirq = priv->irq->intid[0] & 0x1f)) { |
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239 | if ((eirq & 0x10) == 0) |
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240 | continue; |
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241 | genirq_doirq(priv->genirq, eirq); |
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242 | priv->irq->iclear = (1 << eirq); |
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243 | } |
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244 | } else { |
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245 | genirq_doirq(priv->genirq, irq); |
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246 | } |
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247 | priv->irq->iclear = (1 << irq); |
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248 | status &= ~(1 << irq); |
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249 | if ( status == 0 ) |
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250 | break; |
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251 | } |
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252 | } |
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253 | SPIN_UNLOCK(&priv->devlock, irqflags); |
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254 | |
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255 | /* ACK interrupt, this is because PCI is Level, so the IRQ Controller |
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256 | * still drives the IRQ |
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257 | */ |
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258 | if ( tmp ) |
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259 | drvmgr_interrupt_clear(priv->dev, 0); |
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260 | |
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261 | DBG("GR-CPCI-GR740-IRQ: 0x%x\n", tmp); |
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262 | } |
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263 | |
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264 | static int gr_cpci_gr740_hw_init1(struct gr_cpci_gr740_priv *priv) |
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265 | { |
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266 | int i; |
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267 | uint32_t data; |
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268 | unsigned int ctrl; |
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269 | uint8_t tmp2; |
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270 | struct ambapp_dev *tmp; |
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271 | struct ambapp_ahb_info *ahb; |
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272 | uint8_t cap_ptr; |
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273 | pci_dev_t pcidev = priv->pcidev; |
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274 | struct pci_dev_info *devinfo = priv->devinfo; |
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275 | unsigned int cgmask, enabled; |
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276 | |
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277 | /* Check capabilities list bit and read its pointer */ |
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278 | pci_cfg_r8(pcidev, PCIR_STATUS, &tmp2); |
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279 | if (!((tmp2 >> 4) & 1)) { |
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280 | /* Capabilities list not available which it should be in the GRPCI2 */ |
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281 | return -2; |
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282 | } |
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283 | pci_cfg_r8(pcidev, PCIR_CAP_PTR, &cap_ptr); |
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284 | |
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285 | /* Set AHB address mappings for target PCI bars |
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286 | * BAR0 maps to 0x00000000-0x07ffffff 128MB (SDRAM/DDR2 memory) |
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287 | * BAR1 maps to 0xf0000000-0xf7ffffff 128MB (L2-Cache regs/diagnostics) |
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288 | * BAR2 maps to 0xff800000-0xffffffff 8MB (PnP, I/O regs) |
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289 | */ |
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290 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR0_TO_AHB_MAP, 0x00000000); |
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291 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR1_TO_AHB_MAP, 0xf0000000); |
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292 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR2_TO_AHB_MAP, 0xff800000); |
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293 | |
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294 | /* Set PCI bus to be big endian */ |
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295 | pci_cfg_r32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, &data); |
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296 | data = data & 0xFFFFFFFE; |
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297 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, data); |
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298 | |
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299 | #if 0 |
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300 | /* set parity error response */ |
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301 | pci_cfg_r32(pcidev, PCIR_COMMAND, &data); |
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302 | pci_cfg_w32(pcidev, PCIR_COMMAND, (data|PCIM_CMD_PERRESPEN)); |
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303 | #endif |
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304 | |
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305 | /* Scan AMBA Plug&Play */ |
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306 | |
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307 | /* AMBA MAP bar0 (in gr740) ==> 0x00000000 (remote amba address) */ |
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308 | priv->amba_maps[0].size = devinfo->resources[0].size; |
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309 | priv->amba_maps[0].local_adr = devinfo->resources[0].address; |
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310 | priv->amba_maps[0].remote_adr = 0x00000000; |
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311 | |
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312 | priv->amba_maps[1].size = devinfo->resources[1].size; |
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313 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
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314 | priv->amba_maps[1].remote_adr = 0xf0000000; |
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315 | |
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316 | priv->amba_maps[2].size = devinfo->resources[2].size; |
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317 | priv->amba_maps[2].local_adr = devinfo->resources[2].address; |
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318 | priv->amba_maps[2].remote_adr = 0xff800000; |
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319 | |
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320 | /* Addresses not matching with map be untouched */ |
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321 | priv->amba_maps[3].size = 0xfffffff0; |
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322 | priv->amba_maps[3].local_adr = 0; |
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323 | priv->amba_maps[3].remote_adr = 0; |
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324 | |
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325 | /* Mark end of table */ |
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326 | priv->amba_maps[4].size=0; |
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327 | |
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328 | /* Start AMBA PnP scan at first AHB bus */ |
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329 | ambapp_scan( |
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330 | &priv->abus, |
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331 | devinfo->resources[2].address + 0x00700000, |
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332 | NULL, |
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333 | &priv->amba_maps[0]); |
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334 | |
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335 | /* Initialize Frequency of AMBA bus */ |
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336 | ambapp_freq_init(&priv->abus, NULL, priv->amba_freq_hz); |
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337 | |
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338 | /* Find IRQ controller, Clear all current IRQs */ |
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339 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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340 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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341 | VENDOR_GAISLER, GAISLER_IRQMP, |
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342 | ambapp_find_by_idx, NULL); |
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343 | if ( !tmp ) { |
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344 | return -4; |
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345 | } |
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346 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
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347 | /* Set up GR-CPCI-GR740 irq controller |
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348 | * Interrupts are routed from IRQCtrl0, we leave the configuration |
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349 | * for the other CPUs, as the board's CPUs may be running something. |
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350 | * We assume IRQCtrl has been set up properly, or at least the reset |
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351 | * values shuold work with this code.. |
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352 | */ |
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353 | priv->irq->mask[0] = 0; |
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354 | priv->irq->iforce = 0; |
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355 | priv->irq->force[0] = 0; |
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356 | priv->irq->ilevel = 0; |
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357 | priv->irq->ipend = 0; |
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358 | priv->irq->iclear = 0xffffffff; |
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359 | priv->irq->ilevel = 0; |
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360 | /* Get extended Interrupt controller IRQ number */ |
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361 | priv->eirq = (priv->irq->mpstat >> 16) & 0xf; |
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362 | |
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363 | /* Find first Clock-Gating unit, enable/disable the requested cores */ |
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364 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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365 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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366 | VENDOR_GAISLER, GAISLER_CLKGATE, |
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367 | ambapp_find_by_idx, NULL); |
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368 | if ( !tmp ) { |
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369 | return -5; |
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370 | } |
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371 | priv->cg = (struct gr740_grcg_regs *)DEV_TO_APB(tmp)->start; |
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372 | /* Do reset and enable sequence only if not already enabled */ |
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373 | if (priv->cg && ((enabled = priv->cg->enable) != priv->cg_en_mask)) { |
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374 | /* First disable already enabled cores */ |
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375 | cgmask = ~priv->cg_en_mask & enabled; |
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376 | if (cgmask) { |
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377 | priv->cg->unlock = cgmask; |
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378 | priv->cg->enable = enabled = ~cgmask & enabled; |
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379 | priv->cg->unlock = 0; |
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380 | } |
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381 | /* Enable disabled cores */ |
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382 | cgmask = priv->cg_en_mask & ~enabled; |
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383 | if (cgmask) { |
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384 | priv->cg->unlock = cgmask; |
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385 | priv->cg->reset |= cgmask; |
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386 | priv->cg->enable = cgmask | enabled; |
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387 | priv->cg->reset &= ~cgmask; |
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388 | priv->cg->unlock = 0; |
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389 | } |
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390 | } |
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391 | |
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392 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
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393 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
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394 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
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395 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
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396 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
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397 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
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398 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
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399 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
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400 | priv->bus_maps_down[2].name = "PCI BAR2 -> AMBA"; |
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401 | priv->bus_maps_down[2].size = priv->amba_maps[2].size; |
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402 | priv->bus_maps_down[2].from_adr = (void *)priv->amba_maps[2].local_adr; |
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403 | priv->bus_maps_down[2].to_adr = (void *)priv->amba_maps[2].remote_adr; |
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404 | priv->bus_maps_down[3].size = 0; |
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405 | |
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406 | /* Find GRPCI2 controller AHB Slave interface */ |
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407 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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408 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
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409 | VENDOR_GAISLER, GAISLER_GRPCI2, |
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410 | ambapp_find_by_idx, NULL); |
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411 | if ( !tmp ) { |
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412 | return -6; |
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413 | } |
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414 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
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415 | priv->bus_maps_up[0].name = "AMBA GRPCI2 Window"; |
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416 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-CPCI-GR740 board */ |
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417 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
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418 | priv->bus_maps_up[0].to_adr = (void *) |
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419 | (priv->ahbmst2pci_map & ~(ahb->mask[0]-1)); |
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420 | priv->bus_maps_up[1].size = 0; |
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421 | |
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422 | /* Find GRPCI2 controller APB Slave interface */ |
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423 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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424 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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425 | VENDOR_GAISLER, GAISLER_GRPCI2, |
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426 | ambapp_find_by_idx, NULL); |
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427 | if ( !tmp ) { |
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428 | return -7; |
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429 | } |
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430 | priv->grpci2 = (struct grpci2_regs *) |
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431 | ((struct ambapp_apb_info *)tmp->devinfo)->start; |
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432 | |
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433 | /* Set AHB to PCI mapping for all AMBA AHB masters */ |
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434 | for(i = 0; i < 16; i++) { |
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435 | priv->grpci2->ahbmst_map[i] = priv->ahbmst2pci_map & |
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436 | ~(ahb->mask[0]-1); |
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437 | } |
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438 | |
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439 | /* Make sure dirq(0) sampling is enabled */ |
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440 | ctrl = priv->grpci2->ctrl; |
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441 | ctrl = (ctrl & 0xFFFFFF0F) | (1 << 4); |
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442 | priv->grpci2->ctrl = ctrl; |
---|
443 | |
---|
444 | /* Successfully registered the GR740 board */ |
---|
445 | return 0; |
---|
446 | } |
---|
447 | |
---|
448 | static int gr_cpci_gr740_hw_init2(struct gr_cpci_gr740_priv *priv) |
---|
449 | { |
---|
450 | /* Enable DMA by enabling PCI target as master */ |
---|
451 | pci_master_enable(priv->pcidev); |
---|
452 | |
---|
453 | return DRVMGR_OK; |
---|
454 | } |
---|
455 | |
---|
456 | /* Called when a PCI target is found with the PCI device and vendor ID |
---|
457 | * given in gr_cpci_gr740_ids[]. |
---|
458 | */ |
---|
459 | int gr_cpci_gr740_init1(struct drvmgr_dev *dev) |
---|
460 | { |
---|
461 | struct gr_cpci_gr740_priv *priv; |
---|
462 | struct pci_dev_info *devinfo; |
---|
463 | int status, i; |
---|
464 | union drvmgr_key_value *value; |
---|
465 | int resources_cnt; |
---|
466 | |
---|
467 | priv = dev->priv; |
---|
468 | if (!priv) |
---|
469 | return DRVMGR_NOMEM; |
---|
470 | |
---|
471 | memset(priv, 0, sizeof(*priv)); |
---|
472 | dev->priv = priv; |
---|
473 | priv->dev = dev; |
---|
474 | |
---|
475 | /* Determine number of configurations */ |
---|
476 | resources_cnt = get_resarray_count(gr_cpci_gr740_resources); |
---|
477 | |
---|
478 | /* Generate Device prefix */ |
---|
479 | |
---|
480 | strcpy(priv->prefix, "/dev/gr740_0"); |
---|
481 | priv->prefix[11] += dev->minor_drv; |
---|
482 | mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO); |
---|
483 | priv->prefix[12] = '/'; |
---|
484 | priv->prefix[13] = '\0'; |
---|
485 | |
---|
486 | priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo; |
---|
487 | priv->pcidev = devinfo->pcidev; |
---|
488 | printf("\n\n--- GR-CPCI-GR740[%d] ---\n", dev->minor_drv); |
---|
489 | printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n", |
---|
490 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
491 | printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n", |
---|
492 | devinfo->id.vendor, devinfo->id.device); |
---|
493 | for (i = 0; i < 3; i++) { |
---|
494 | printf(" PCI BAR[%d]: 0x%08lx - 0x%08lx\n", |
---|
495 | i, devinfo->resources[i].address, |
---|
496 | devinfo->resources[i].address + |
---|
497 | (devinfo->resources[i].size - 1)); |
---|
498 | /* all neccessary space assigned to GR-CPCI-GR740 target? */ |
---|
499 | if (devinfo->resources[i].size == 0) |
---|
500 | return DRVMGR_ENORES; |
---|
501 | } |
---|
502 | printf(" IRQ: %d\n\n\n", devinfo->irq); |
---|
503 | |
---|
504 | /* Initialize spin-lock for this PCI perihperal device. This is to |
---|
505 | * protect the Interrupt Controller Registers. The genirq layer is |
---|
506 | * protecting its own internals and ISR dispatching. |
---|
507 | */ |
---|
508 | SPIN_INIT(&priv->devlock, priv->prefix); |
---|
509 | |
---|
510 | /* Let user override which PCI address the AHB masters of the |
---|
511 | * GR740 board access when doing DMA to HOST RAM. The AHB masters |
---|
512 | * access the PCI Window of the AMBA bus, the MSB 2-bits of that address |
---|
513 | * is translated according this config option before the address goes |
---|
514 | * out on the PCI bus. |
---|
515 | * |
---|
516 | * Only the 2 MSB bits have an effect. |
---|
517 | */ |
---|
518 | value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", DRVMGR_KT_INT); |
---|
519 | if (value) |
---|
520 | priv->ahbmst2pci_map = value->i; |
---|
521 | else |
---|
522 | priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */ |
---|
523 | |
---|
524 | /* Let user override the default AMBA system frequency of the |
---|
525 | * CPU-bus of the remote GR-CPCI-GR740. Default is 250MHz. |
---|
526 | */ |
---|
527 | value = drvmgr_dev_key_get(priv->dev, "ambaFreq", DRVMGR_KT_INT); |
---|
528 | if (value) |
---|
529 | priv->amba_freq_hz = value->i; |
---|
530 | else |
---|
531 | priv->amba_freq_hz = 250000000; /* default */ |
---|
532 | |
---|
533 | /* Let user determine clock-gating unit configuration. The default |
---|
534 | * is to turn all cores on (disable gating). PCI is always turned ON. |
---|
535 | */ |
---|
536 | value = drvmgr_dev_key_get(priv->dev, "cgEnMask", DRVMGR_KT_INT); |
---|
537 | if (value) |
---|
538 | priv->cg_en_mask = (value->i & CG_MASK) | 0x08; |
---|
539 | else |
---|
540 | priv->cg_en_mask = CG_MASK; /* default all ON */ |
---|
541 | |
---|
542 | priv->genirq = genirq_init(32); |
---|
543 | if (priv->genirq == NULL) |
---|
544 | return DRVMGR_FAIL; |
---|
545 | |
---|
546 | if ((status = gr_cpci_gr740_hw_init1(priv)) != 0) { |
---|
547 | genirq_destroy(priv->genirq); |
---|
548 | printf(" Failed to initialize GR-CPCI-GR740 HW: %d\n", status); |
---|
549 | return DRVMGR_FAIL; |
---|
550 | } |
---|
551 | |
---|
552 | /* Init amba bus */ |
---|
553 | priv->config.abus = &priv->abus; |
---|
554 | priv->config.ops = &ambapp_gr740_ops; |
---|
555 | priv->config.maps_up = &priv->bus_maps_up[0]; |
---|
556 | priv->config.maps_down = &priv->bus_maps_down[0]; |
---|
557 | if ( priv->dev->minor_drv < resources_cnt ) { |
---|
558 | priv->config.resources = gr_cpci_gr740_resources[priv->dev->minor_drv]; |
---|
559 | } else { |
---|
560 | priv->config.resources = NULL; |
---|
561 | } |
---|
562 | |
---|
563 | /* Create and register AMBA PnP bus. */ |
---|
564 | return ambapp_bus_register(dev, &priv->config); |
---|
565 | } |
---|
566 | |
---|
567 | int gr_cpci_gr740_init2(struct drvmgr_dev *dev) |
---|
568 | { |
---|
569 | struct gr_cpci_gr740_priv *priv = dev->priv; |
---|
570 | |
---|
571 | /* Clear any old interrupt requests */ |
---|
572 | drvmgr_interrupt_clear(dev, 0); |
---|
573 | |
---|
574 | /* Enable System IRQ so that GR-CPCI-GR740 PCI target interrupt |
---|
575 | * goes through. |
---|
576 | * |
---|
577 | * It is important to enable it in stage init2. If interrupts were |
---|
578 | * enabled in init1 this might hang the system when more than one |
---|
579 | * PCI board is connected, this is because PCI interrupts might |
---|
580 | * be shared and PCI board 2 have not initialized and |
---|
581 | * might therefore drive interrupt already when entering init1(). |
---|
582 | */ |
---|
583 | drvmgr_interrupt_register( |
---|
584 | dev, |
---|
585 | 0, |
---|
586 | "gr_cpci_gr740", |
---|
587 | gr_cpci_gr740_isr, |
---|
588 | (void *)priv); |
---|
589 | |
---|
590 | return gr_cpci_gr740_hw_init2(priv); |
---|
591 | } |
---|
592 | |
---|
593 | int ambapp_gr740_int_register( |
---|
594 | struct drvmgr_dev *dev, |
---|
595 | int irq, |
---|
596 | const char *info, |
---|
597 | drvmgr_isr handler, |
---|
598 | void *arg) |
---|
599 | { |
---|
600 | struct gr_cpci_gr740_priv *priv = dev->parent->dev->priv; |
---|
601 | SPIN_IRQFLAGS(irqflags); |
---|
602 | int status; |
---|
603 | void *h; |
---|
604 | |
---|
605 | h = genirq_alloc_handler(handler, arg); |
---|
606 | if ( h == NULL ) |
---|
607 | return DRVMGR_FAIL; |
---|
608 | |
---|
609 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
610 | |
---|
611 | status = genirq_register(priv->genirq, irq, h); |
---|
612 | if (status == 0) { |
---|
613 | /* Clear IRQ for first registered handler */ |
---|
614 | priv->irq->iclear = (1<<irq); |
---|
615 | } else if (status == 1) |
---|
616 | status = 0; |
---|
617 | |
---|
618 | if (status != 0) { |
---|
619 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
620 | genirq_free_handler(h); |
---|
621 | return DRVMGR_FAIL; |
---|
622 | } |
---|
623 | |
---|
624 | status = genirq_enable(priv->genirq, irq, handler, arg); |
---|
625 | if ( status == 0 ) { |
---|
626 | /* Enable IRQ for first enabled handler only */ |
---|
627 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
628 | } else if ( status == 1 ) |
---|
629 | status = 0; |
---|
630 | |
---|
631 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
632 | |
---|
633 | return status; |
---|
634 | } |
---|
635 | |
---|
636 | int ambapp_gr740_int_unregister( |
---|
637 | struct drvmgr_dev *dev, |
---|
638 | int irq, |
---|
639 | drvmgr_isr isr, |
---|
640 | void *arg) |
---|
641 | { |
---|
642 | struct gr_cpci_gr740_priv *priv = dev->parent->dev->priv; |
---|
643 | SPIN_IRQFLAGS(irqflags); |
---|
644 | int status; |
---|
645 | void *handler; |
---|
646 | |
---|
647 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
648 | |
---|
649 | status = genirq_disable(priv->genirq, irq, isr, arg); |
---|
650 | if ( status == 0 ) { |
---|
651 | /* Disable IRQ only when no enabled handler exists */ |
---|
652 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
653 | } |
---|
654 | |
---|
655 | handler = genirq_unregister(priv->genirq, irq, isr, arg); |
---|
656 | if ( handler == NULL ) |
---|
657 | status = DRVMGR_FAIL; |
---|
658 | else |
---|
659 | status = DRVMGR_OK; |
---|
660 | |
---|
661 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
662 | |
---|
663 | if (handler) |
---|
664 | genirq_free_handler(handler); |
---|
665 | |
---|
666 | return status; |
---|
667 | } |
---|
668 | |
---|
669 | int ambapp_gr740_int_unmask( |
---|
670 | struct drvmgr_dev *dev, |
---|
671 | int irq) |
---|
672 | { |
---|
673 | struct gr_cpci_gr740_priv *priv = dev->parent->dev->priv; |
---|
674 | SPIN_IRQFLAGS(irqflags); |
---|
675 | |
---|
676 | DBG("GR740 IRQ %d: unmask\n", irq); |
---|
677 | |
---|
678 | if ( genirq_check(priv->genirq, irq) ) |
---|
679 | return DRVMGR_EINVAL; |
---|
680 | |
---|
681 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
682 | |
---|
683 | /* Enable IRQ for first enabled handler only */ |
---|
684 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
685 | |
---|
686 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
687 | |
---|
688 | return DRVMGR_OK; |
---|
689 | } |
---|
690 | |
---|
691 | int ambapp_gr740_int_mask( |
---|
692 | struct drvmgr_dev *dev, |
---|
693 | int irq) |
---|
694 | { |
---|
695 | struct gr_cpci_gr740_priv *priv = dev->parent->dev->priv; |
---|
696 | SPIN_IRQFLAGS(irqflags); |
---|
697 | |
---|
698 | DBG("GR740 IRQ %d: mask\n", irq); |
---|
699 | |
---|
700 | if ( genirq_check(priv->genirq, irq) ) |
---|
701 | return DRVMGR_EINVAL; |
---|
702 | |
---|
703 | SPIN_LOCK_IRQ(&priv->devlock, irqflags); |
---|
704 | |
---|
705 | /* Disable/mask IRQ */ |
---|
706 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
707 | |
---|
708 | SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); |
---|
709 | |
---|
710 | return DRVMGR_OK; |
---|
711 | } |
---|
712 | |
---|
713 | int ambapp_gr740_int_clear( |
---|
714 | struct drvmgr_dev *dev, |
---|
715 | int irq) |
---|
716 | { |
---|
717 | struct gr_cpci_gr740_priv *priv = dev->parent->dev->priv; |
---|
718 | |
---|
719 | if ( genirq_check(priv->genirq, irq) ) |
---|
720 | return DRVMGR_EINVAL; |
---|
721 | |
---|
722 | priv->irq->iclear = (1<<irq); |
---|
723 | |
---|
724 | return DRVMGR_OK; |
---|
725 | } |
---|
726 | |
---|
727 | int ambapp_gr740_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
---|
728 | { |
---|
729 | struct gr_cpci_gr740_priv *priv = dev->parent->dev->priv; |
---|
730 | |
---|
731 | /* Device name prefix pointer, skip /dev */ |
---|
732 | params->dev_prefix = &priv->prefix[5]; |
---|
733 | |
---|
734 | return 0; |
---|
735 | } |
---|
736 | |
---|
737 | void gr_cpci_gr740_print_dev(struct drvmgr_dev *dev, int options) |
---|
738 | { |
---|
739 | struct gr_cpci_gr740_priv *priv = dev->priv; |
---|
740 | struct pci_dev_info *devinfo = priv->devinfo; |
---|
741 | uint32_t bar0, bar0_size; |
---|
742 | |
---|
743 | /* Print */ |
---|
744 | printf("--- GR-CPCI-GR740 [bus 0x%x, dev 0x%x, fun 0x%x] ---\n", |
---|
745 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
746 | |
---|
747 | bar0 = devinfo->resources[0].address; |
---|
748 | bar0_size = devinfo->resources[0].size; |
---|
749 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
---|
750 | printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq); |
---|
751 | printf(" IRQ: %d\n", devinfo->irq); |
---|
752 | printf(" PCI REVISION: %d\n", devinfo->rev); |
---|
753 | printf(" FREQ: %d Hz\n", priv->amba_freq_hz); |
---|
754 | printf(" IMASK: 0x%08x\n", priv->irq->mask[0]); |
---|
755 | printf(" IPEND: 0x%08x\n", priv->irq->ipend); |
---|
756 | |
---|
757 | /* Print amba config */ |
---|
758 | if (options & GR_CPCI_GR740_OPTIONS_AMBA) |
---|
759 | ambapp_print(&priv->abus, 10); |
---|
760 | } |
---|
761 | |
---|
762 | void gr_cpci_gr740_print(int options) |
---|
763 | { |
---|
764 | struct pci_drv_info *drv = &gr_cpci_gr740_info; |
---|
765 | struct drvmgr_dev *dev; |
---|
766 | |
---|
767 | dev = drv->general.dev; |
---|
768 | while(dev) { |
---|
769 | gr_cpci_gr740_print_dev(dev, options); |
---|
770 | dev = dev->next_in_drv; |
---|
771 | } |
---|
772 | } |
---|