[3bb4122] | 1 | /* |
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| 2 | * Gaisler Research ethernet MAC driver |
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| 3 | * adapted from Opencores driver by Marko Isomaki |
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| 4 | * |
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| 5 | * The license and distribution terms for this file may be |
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| 6 | * found in found in the file LICENSE in this distribution or at |
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[4a7d1026] | 7 | * http://www.rtems.org/license/LICENSE. |
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[3bb4122] | 8 | * |
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| 9 | * |
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| 10 | * 2008-12-10, Converted to driver manager and added support for |
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| 11 | * multiple GRETH cores. <daniel@gaisler.com> |
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| 12 | * 2007-09-07, Ported GBIT support from 4.6.5 |
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| 13 | */ |
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[d8d6a08] | 14 | |
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[cb68253] | 15 | #include <machine/rtems-bsd-kernel-space.h> |
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[d8d6a08] | 16 | |
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[3bb4122] | 17 | #include <rtems.h> |
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| 18 | #define CPU_U32_FIX |
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| 19 | #include <bsp.h> |
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| 20 | |
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| 21 | #ifdef GRETH_SUPPORTED |
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| 22 | |
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| 23 | #include <inttypes.h> |
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| 24 | #include <errno.h> |
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| 25 | #include <rtems/bspIo.h> |
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| 26 | #include <stdlib.h> |
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| 27 | #include <stdio.h> |
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| 28 | #include <stdarg.h> |
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| 29 | #include <rtems/error.h> |
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| 30 | #include <rtems/rtems_bsdnet.h> |
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| 31 | |
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[5823bae8] | 32 | #include <bsp/greth.h> |
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[3bb4122] | 33 | #include <drvmgr/drvmgr.h> |
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| 34 | #include <drvmgr/ambapp_bus.h> |
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| 35 | #include <ambapp.h> |
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| 36 | |
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| 37 | #include <sys/param.h> |
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| 38 | #include <sys/mbuf.h> |
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| 39 | |
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| 40 | #include <sys/socket.h> |
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| 41 | #include <sys/sockio.h> |
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| 42 | #include <net/if.h> |
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| 43 | #include <netinet/in.h> |
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| 44 | #include <netinet/if_ether.h> |
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| 45 | |
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| 46 | #ifdef malloc |
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| 47 | #undef malloc |
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| 48 | #endif |
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| 49 | #ifdef free |
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| 50 | #undef free |
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| 51 | #endif |
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| 52 | |
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[11f3b9a] | 53 | #include <grlib_impl.h> |
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| 54 | |
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[3bb4122] | 55 | #if defined(__m68k__) |
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| 56 | extern m68k_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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| 57 | #else |
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| 58 | extern rtems_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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| 59 | #endif |
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| 60 | |
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| 61 | |
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| 62 | /* #define GRETH_DEBUG */ |
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| 63 | |
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| 64 | #ifdef GRETH_DEBUG |
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| 65 | #define DBG(args...) printk(args) |
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| 66 | #else |
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| 67 | #define DBG(args...) |
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| 68 | #endif |
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| 69 | |
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[107c5aea] | 70 | /* #define GRETH_DEBUG_MII */ |
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| 71 | |
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| 72 | #ifdef GRETH_DEBUG_MII |
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| 73 | #define MIIDBG(args...) printk(args) |
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| 74 | #else |
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| 75 | #define MIIDBG(args...) |
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| 76 | #endif |
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| 77 | |
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[3bb4122] | 78 | #ifdef CPU_U32_FIX |
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| 79 | extern void ipalign(struct mbuf *m); |
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| 80 | #endif |
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| 81 | |
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| 82 | /* Used when reading from memory written by GRETH DMA unit */ |
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| 83 | #ifndef GRETH_MEM_LOAD |
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| 84 | #define GRETH_MEM_LOAD(addr) (*(volatile unsigned int *)(addr)) |
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| 85 | #endif |
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| 86 | |
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| 87 | /* |
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| 88 | * Number of OCs supported by this driver |
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| 89 | */ |
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| 90 | #define NOCDRIVER 1 |
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| 91 | |
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| 92 | /* |
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| 93 | * Receive buffer size -- Allow for a full ethernet packet including CRC |
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| 94 | */ |
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| 95 | #define RBUF_SIZE 1518 |
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| 96 | |
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| 97 | #define ET_MINLEN 64 /* minimum message length */ |
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| 98 | |
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| 99 | /* |
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| 100 | * RTEMS event used by interrupt handler to signal driver tasks. |
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| 101 | * This must not be any of the events used by the network task synchronization. |
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| 102 | */ |
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| 103 | #define INTERRUPT_EVENT RTEMS_EVENT_1 |
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| 104 | |
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| 105 | /* |
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| 106 | * RTEMS event used to start transmit daemon. |
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| 107 | * This must not be the same as INTERRUPT_EVENT. |
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| 108 | */ |
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| 109 | #define START_TRANSMIT_EVENT RTEMS_EVENT_2 |
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| 110 | |
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| 111 | /* event to send when tx buffers become available */ |
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| 112 | #define GRETH_TX_WAIT_EVENT RTEMS_EVENT_3 |
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| 113 | |
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| 114 | #if (MCLBYTES < RBUF_SIZE) |
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| 115 | # error "Driver must have MCLBYTES > RBUF_SIZE" |
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| 116 | #endif |
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| 117 | |
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| 118 | /* 4s Autonegotiation Timeout */ |
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| 119 | #ifndef GRETH_AUTONEGO_TIMEOUT_MS |
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| 120 | #define GRETH_AUTONEGO_TIMEOUT_MS 4000 |
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| 121 | #endif |
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| 122 | const struct timespec greth_tan = { |
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| 123 | GRETH_AUTONEGO_TIMEOUT_MS/1000, |
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[aedc9849] | 124 | (GRETH_AUTONEGO_TIMEOUT_MS % 1000) * 1000000 |
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[3bb4122] | 125 | }; |
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| 126 | |
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| 127 | /* For optimizing the autonegotiation time */ |
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| 128 | #define GRETH_AUTONEGO_PRINT_TIME |
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| 129 | |
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| 130 | /* Ethernet buffer descriptor */ |
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| 131 | |
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| 132 | typedef struct _greth_rxtxdesc { |
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| 133 | volatile uint32_t ctrl; /* Length and status */ |
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| 134 | uint32_t *addr; /* Buffer pointer */ |
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| 135 | } greth_rxtxdesc; |
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| 136 | |
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| 137 | |
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| 138 | /* |
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| 139 | * Per-device data |
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| 140 | */ |
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| 141 | struct greth_softc |
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| 142 | { |
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| 143 | |
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| 144 | struct arpcom arpcom; |
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| 145 | struct drvmgr_dev *dev; /* Driver manager device */ |
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| 146 | char devName[32]; |
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| 147 | |
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| 148 | greth_regs *regs; |
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| 149 | int minor; |
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| 150 | int phyaddr; /* PHY Address configured by user (or -1 to autodetect) */ |
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[12718134] | 151 | unsigned int edcl_dis; |
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[fa27fe5c] | 152 | int greth_rst; |
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[3bb4122] | 153 | |
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| 154 | int acceptBroadcast; |
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| 155 | rtems_id daemonTid; |
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| 156 | |
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| 157 | unsigned int tx_ptr; |
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| 158 | unsigned int tx_dptr; |
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| 159 | unsigned int tx_cnt; |
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| 160 | unsigned int rx_ptr; |
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| 161 | unsigned int txbufs; |
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| 162 | unsigned int rxbufs; |
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| 163 | greth_rxtxdesc *txdesc; |
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| 164 | greth_rxtxdesc *rxdesc; |
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| 165 | unsigned int txdesc_remote; |
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| 166 | unsigned int rxdesc_remote; |
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| 167 | struct mbuf **rxmbuf; |
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| 168 | struct mbuf **txmbuf; |
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| 169 | rtems_vector_number vector; |
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| 170 | |
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| 171 | /* TX descriptor interrupt generation */ |
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| 172 | int tx_int_gen; |
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| 173 | int tx_int_gen_cur; |
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| 174 | struct mbuf *next_tx_mbuf; |
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| 175 | int max_fragsize; |
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| 176 | |
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| 177 | /*Status*/ |
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| 178 | struct phy_device_info phydev; |
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[107c5aea] | 179 | int phy_read_access; |
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| 180 | int phy_write_access; |
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[3bb4122] | 181 | int fd; |
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| 182 | int sp; |
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| 183 | int gb; |
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| 184 | int gbit_mac; |
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| 185 | int auto_neg; |
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[e6fbd26] | 186 | unsigned int advmodes; /* advertise ethernet speed modes. 0 = all modes. */ |
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[3bb4122] | 187 | struct timespec auto_neg_time; |
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[243ddb52] | 188 | int mc_available; |
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[3bb4122] | 189 | |
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| 190 | /* |
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| 191 | * Statistics |
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| 192 | */ |
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| 193 | unsigned long rxInterrupts; |
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| 194 | |
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| 195 | unsigned long rxPackets; |
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| 196 | unsigned long rxLengthError; |
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| 197 | unsigned long rxNonOctet; |
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| 198 | unsigned long rxBadCRC; |
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| 199 | unsigned long rxOverrun; |
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| 200 | |
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| 201 | unsigned long txInterrupts; |
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| 202 | |
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| 203 | unsigned long txDeferred; |
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| 204 | unsigned long txHeartbeat; |
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| 205 | unsigned long txLateCollision; |
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| 206 | unsigned long txRetryLimit; |
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| 207 | unsigned long txUnderrun; |
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| 208 | |
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[998e34ad] | 209 | /* Spin-lock ISR protection */ |
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| 210 | SPIN_DECLARE(devlock); |
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[3bb4122] | 211 | }; |
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| 212 | |
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| 213 | int greth_process_tx_gbit(struct greth_softc *sc); |
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| 214 | int greth_process_tx(struct greth_softc *sc); |
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| 215 | |
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| 216 | static char *almalloc(int sz, int alignment) |
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| 217 | { |
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| 218 | char *tmp; |
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[11f3b9a] | 219 | tmp = grlib_calloc(1, sz + (alignment-1)); |
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[3bb4122] | 220 | tmp = (char *) (((int)tmp+alignment) & ~(alignment -1)); |
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| 221 | return(tmp); |
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| 222 | } |
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| 223 | |
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| 224 | /* GRETH interrupt handler */ |
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| 225 | |
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[aedc9849] | 226 | static void greth_interrupt (void *arg) |
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[3bb4122] | 227 | { |
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| 228 | uint32_t status; |
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| 229 | uint32_t ctrl; |
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| 230 | rtems_event_set events = 0; |
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| 231 | struct greth_softc *greth = arg; |
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[998e34ad] | 232 | SPIN_ISR_IRQFLAGS(flags); |
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| 233 | |
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[3bb4122] | 234 | /* read and clear interrupt cause */ |
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| 235 | status = greth->regs->status; |
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| 236 | greth->regs->status = status; |
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[998e34ad] | 237 | |
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| 238 | SPIN_LOCK(&greth->devlock, flags); |
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[3bb4122] | 239 | ctrl = greth->regs->ctrl; |
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[998e34ad] | 240 | |
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[3bb4122] | 241 | /* Frame received? */ |
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| 242 | if ((ctrl & GRETH_CTRL_RXIRQ) && (status & (GRETH_STATUS_RXERR | GRETH_STATUS_RXIRQ))) |
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| 243 | { |
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| 244 | greth->rxInterrupts++; |
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| 245 | /* Stop RX-Error and RX-Packet interrupts */ |
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| 246 | ctrl &= ~GRETH_CTRL_RXIRQ; |
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| 247 | events |= INTERRUPT_EVENT; |
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| 248 | } |
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[998e34ad] | 249 | |
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[3bb4122] | 250 | if ( (ctrl & GRETH_CTRL_TXIRQ) && (status & (GRETH_STATUS_TXERR | GRETH_STATUS_TXIRQ)) ) |
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| 251 | { |
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| 252 | greth->txInterrupts++; |
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| 253 | ctrl &= ~GRETH_CTRL_TXIRQ; |
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| 254 | events |= GRETH_TX_WAIT_EVENT; |
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| 255 | } |
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[998e34ad] | 256 | |
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[3bb4122] | 257 | /* Clear interrupt sources */ |
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| 258 | greth->regs->ctrl = ctrl; |
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[998e34ad] | 259 | SPIN_UNLOCK(&greth->devlock, flags); |
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| 260 | |
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[3bb4122] | 261 | /* Send the event(s) */ |
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| 262 | if ( events ) |
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[a1e4e3bf] | 263 | rtems_bsdnet_event_send(greth->daemonTid, events); |
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[3bb4122] | 264 | } |
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| 265 | |
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| 266 | static uint32_t read_mii(struct greth_softc *sc, uint32_t phy_addr, uint32_t reg_addr) |
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| 267 | { |
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[107c5aea] | 268 | sc->phy_read_access++; |
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[3bb4122] | 269 | while (sc->regs->mdio_ctrl & GRETH_MDIO_BUSY) {} |
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| 270 | sc->regs->mdio_ctrl = (phy_addr << 11) | (reg_addr << 6) | GRETH_MDIO_READ; |
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| 271 | while (sc->regs->mdio_ctrl & GRETH_MDIO_BUSY) {} |
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[107c5aea] | 272 | if (!(sc->regs->mdio_ctrl & GRETH_MDIO_LINKFAIL)) { |
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[aedc9849] | 273 | MIIDBG("greth%d: mii read[%d] OK to %" PRIx32 ".%" PRIx32 |
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| 274 | " (0x%08" PRIx32 ",0x%08" PRIx32 ")\n", |
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| 275 | sc->minor, sc->phy_read_access, phy_addr, reg_addr, |
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| 276 | sc->regs->ctrl, sc->regs->mdio_ctrl); |
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[3bb4122] | 277 | return((sc->regs->mdio_ctrl >> 16) & 0xFFFF); |
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[107c5aea] | 278 | } else { |
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[aedc9849] | 279 | printf("greth%d: mii read[%d] failed to %" PRIx32 ".%" PRIx32 |
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| 280 | " (0x%08" PRIx32 ",0x%08" PRIx32 ")\n", |
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| 281 | sc->minor, sc->phy_read_access, phy_addr, reg_addr, |
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| 282 | sc->regs->ctrl, sc->regs->mdio_ctrl); |
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| 283 | return (0xffff); |
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[3bb4122] | 284 | } |
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| 285 | } |
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| 286 | |
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| 287 | static void write_mii(struct greth_softc *sc, uint32_t phy_addr, uint32_t reg_addr, uint32_t data) |
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| 288 | { |
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[107c5aea] | 289 | sc->phy_write_access++; |
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[3bb4122] | 290 | while (sc->regs->mdio_ctrl & GRETH_MDIO_BUSY) {} |
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| 291 | sc->regs->mdio_ctrl = |
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| 292 | ((data & 0xFFFF) << 16) | (phy_addr << 11) | (reg_addr << 6) | GRETH_MDIO_WRITE; |
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| 293 | while (sc->regs->mdio_ctrl & GRETH_MDIO_BUSY) {} |
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[107c5aea] | 294 | if (!(sc->regs->mdio_ctrl & GRETH_MDIO_LINKFAIL)) { |
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[aedc9849] | 295 | MIIDBG("greth%d: mii write[%d] OK to to %" PRIx32 ".%" PRIx32 |
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| 296 | "(0x%08" PRIx32 ",0x%08" PRIx32 ")\n", |
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| 297 | sc->minor, sc->phy_write_access, phy_addr, reg_addr, |
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| 298 | sc->regs->ctrl, sc->regs->mdio_ctrl); |
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[107c5aea] | 299 | } else { |
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[aedc9849] | 300 | printf("greth%d: mii write[%d] failed to to %" PRIx32 ".%" PRIx32 |
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| 301 | " (0x%08" PRIx32 ",0x%08" PRIx32 ")\n", |
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| 302 | sc->minor, sc->phy_write_access, phy_addr, reg_addr, |
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| 303 | sc->regs->ctrl, sc->regs->mdio_ctrl); |
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[107c5aea] | 304 | } |
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[3bb4122] | 305 | } |
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| 306 | |
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| 307 | static void print_init_info(struct greth_softc *sc) |
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| 308 | { |
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| 309 | printf("greth: driver attached\n"); |
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| 310 | if ( sc->auto_neg == -1 ){ |
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| 311 | printf("Auto negotiation timed out. Selecting default config\n"); |
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| 312 | } |
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| 313 | printf("**** PHY ****\n"); |
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| 314 | printf("Vendor: %x Device: %x Revision: %d\n",sc->phydev.vendor, sc->phydev.device, sc->phydev.rev); |
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| 315 | printf("Current Operating Mode: "); |
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| 316 | if (sc->gb) { |
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| 317 | printf("1000 Mbit "); |
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| 318 | } else if (sc->sp) { |
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| 319 | printf("100 Mbit "); |
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| 320 | } else { |
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| 321 | printf("10 Mbit "); |
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| 322 | } |
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| 323 | if (sc->fd) { |
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| 324 | printf("Full Duplex\n"); |
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| 325 | } else { |
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| 326 | printf("Half Duplex\n"); |
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| 327 | } |
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| 328 | #ifdef GRETH_AUTONEGO_PRINT_TIME |
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| 329 | if ( sc->auto_neg ) { |
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[aedc9849] | 330 | printf("Autonegotiation Time: %ldms\n", sc->auto_neg_time.tv_sec * 1000 + |
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[3bb4122] | 331 | sc->auto_neg_time.tv_nsec / 1000000); |
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| 332 | } |
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| 333 | #endif |
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| 334 | } |
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| 335 | |
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[243ddb52] | 336 | /* |
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| 337 | * Generates the hash words based on CRCs of the enabled MAC addresses that are |
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| 338 | * allowed to be received. The allowed MAC addresses are maintained in a linked |
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| 339 | * "multi-cast" list available in the arpcom structure. |
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| 340 | * |
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| 341 | * Returns the number of MAC addresses that were processed (in the list) |
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| 342 | */ |
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| 343 | static int |
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| 344 | greth_mac_filter_calc(struct arpcom *ac, uint32_t *msb, uint32_t *lsb) |
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| 345 | { |
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| 346 | struct ether_multistep step; |
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| 347 | struct ether_multi *enm; |
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| 348 | int cnt = 0; |
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| 349 | uint32_t crc, htindex, ht[2] = {0, 0}; |
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| 350 | |
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| 351 | /* Go through the Ethernet Multicast addresses one by one and add their |
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| 352 | * CRC contribution to the MAC filter. |
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| 353 | */ |
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| 354 | ETHER_FIRST_MULTI(step, ac, enm); |
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| 355 | while (enm) { |
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| 356 | crc = ether_crc32_be((uint8_t *)enm->enm_addrlo, 6); |
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| 357 | htindex = crc & 0x3f; |
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| 358 | ht[htindex >> 5] |= (1 << (htindex & 0x1F)); |
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| 359 | cnt++; |
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| 360 | ETHER_NEXT_MULTI(step, enm); |
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| 361 | } |
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| 362 | |
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| 363 | if (cnt > 0) { |
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| 364 | *msb = ht[1]; |
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| 365 | *lsb = ht[0]; |
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| 366 | } |
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| 367 | |
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| 368 | return cnt; |
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| 369 | } |
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| 370 | |
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| 371 | /* |
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| 372 | * Initialize the ethernet hardware |
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| 373 | */ |
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| 374 | static int greth_mac_filter_set(struct greth_softc *sc) |
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| 375 | { |
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| 376 | struct ifnet *ifp = &sc->arpcom.ac_if; |
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| 377 | uint32_t hash_msb, hash_lsb, ctrl; |
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| 378 | SPIN_IRQFLAGS(flags); |
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| 379 | |
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| 380 | hash_msb = 0; |
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| 381 | hash_lsb = 0; |
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| 382 | ctrl = 0; |
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| 383 | if (ifp->if_flags & IFF_PROMISC) { |
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| 384 | /* No need to enable multi-cast when promiscous mode accepts all */ |
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| 385 | ctrl |= GRETH_CTRL_PRO; |
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| 386 | } else if(!sc->mc_available) { |
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| 387 | return EINVAL; /* no hardware support for multicast filtering. */ |
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| 388 | } else if (ifp->if_flags & IFF_ALLMULTI) { |
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| 389 | /* We should accept all multicast addresses */ |
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| 390 | ctrl |= GRETH_CTRL_MCE; |
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| 391 | hash_msb = 0xFFFFFFFF; |
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| 392 | hash_lsb = 0xFFFFFFFF; |
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| 393 | } else if (greth_mac_filter_calc(&sc->arpcom, &hash_msb, &hash_lsb) > 0) { |
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| 394 | /* Generate hash for MAC filtering out multicast addresses */ |
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| 395 | ctrl |= GRETH_CTRL_MCE; |
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| 396 | } else { |
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| 397 | /* Multicast list is empty .. disable multicast */ |
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| 398 | } |
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| 399 | SPIN_LOCK_IRQ(&sc->devlock, flags); |
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| 400 | sc->regs->ht_msb = hash_msb; |
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| 401 | sc->regs->ht_lsb = hash_lsb; |
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| 402 | sc->regs->ctrl = (sc->regs->ctrl & ~(GRETH_CTRL_PRO | GRETH_CTRL_MCE)) | |
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| 403 | ctrl; |
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| 404 | SPIN_UNLOCK_IRQ(&sc->devlock, flags); |
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| 405 | |
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| 406 | return 0; |
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| 407 | } |
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[3bb4122] | 408 | |
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| 409 | /* |
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| 410 | * Initialize the ethernet hardware |
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| 411 | */ |
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| 412 | static void |
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| 413 | greth_initialize_hardware (struct greth_softc *sc) |
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| 414 | { |
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| 415 | struct mbuf *m; |
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| 416 | int i; |
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| 417 | int phyaddr; |
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| 418 | int phyctrl; |
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| 419 | int phystatus; |
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| 420 | int tmp1; |
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| 421 | int tmp2; |
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| 422 | struct timespec tstart, tnow; |
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| 423 | greth_regs *regs; |
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[fa27fe5c] | 424 | unsigned int advmodes, speed; |
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[3bb4122] | 425 | |
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| 426 | regs = sc->regs; |
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[12718134] | 427 | |
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[3bb4122] | 428 | /* Reset the controller. */ |
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| 429 | sc->rxInterrupts = 0; |
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| 430 | sc->rxPackets = 0; |
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| 431 | |
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[fa27fe5c] | 432 | if (sc->greth_rst) { |
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| 433 | /* Reset ON */ |
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| 434 | regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; |
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| 435 | for (i = 0; i<100 && (regs->ctrl & GRETH_CTRL_RST); i++) |
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| 436 | ; |
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| 437 | speed = 0; /* probe mode below */ |
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| 438 | } else { |
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| 439 | /* inherit EDCL mode for now */ |
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| 440 | speed = sc->regs->ctrl & (GRETH_CTRL_GB|GRETH_CTRL_SP|GRETH_CTRL_FULLD); |
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| 441 | } |
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| 442 | /* Reset OFF and RX/TX DMA OFF. SW do PHY Init */ |
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| 443 | regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED | speed; |
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[107c5aea] | 444 | |
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[3bb4122] | 445 | /* Check if mac is gbit capable*/ |
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| 446 | sc->gbit_mac = (regs->ctrl >> 27) & 1; |
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[107c5aea] | 447 | |
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[3bb4122] | 448 | /* Get the phy address which assumed to have been set |
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| 449 | correctly with the reset value in hardware*/ |
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| 450 | if ( sc->phyaddr == -1 ) { |
---|
| 451 | phyaddr = (regs->mdio_ctrl >> 11) & 0x1F; |
---|
| 452 | } else { |
---|
| 453 | phyaddr = sc->phyaddr; |
---|
| 454 | } |
---|
[107c5aea] | 455 | sc->phy_read_access = 0; |
---|
| 456 | sc->phy_write_access = 0; |
---|
| 457 | |
---|
| 458 | /* As I understand the PHY comes back to a good default state after |
---|
| 459 | * Power-down or Reset, so we do both just in case. Power-down bit should |
---|
| 460 | * be cleared. |
---|
| 461 | * Wait for old reset (if asserted by boot loader) to complete, otherwise |
---|
| 462 | * power-down instruction might not have any effect. |
---|
| 463 | */ |
---|
| 464 | while (read_mii(sc, phyaddr, 0) & 0x8000) {} |
---|
| 465 | write_mii(sc, phyaddr, 0, 0x0800); /* Power-down */ |
---|
| 466 | write_mii(sc, phyaddr, 0, 0x0000); /* Power-Up */ |
---|
| 467 | write_mii(sc, phyaddr, 0, 0x8000); /* Reset */ |
---|
[3bb4122] | 468 | |
---|
[107c5aea] | 469 | /* We wait about 30ms */ |
---|
| 470 | rtems_task_wake_after(rtems_clock_get_ticks_per_second()/32); |
---|
[a79c36ad] | 471 | |
---|
| 472 | /* Wait for reset to complete and get default values */ |
---|
[3bb4122] | 473 | while ((phyctrl = read_mii(sc, phyaddr, 0)) & 0x8000) {} |
---|
| 474 | |
---|
[e6fbd26] | 475 | /* Set up PHY advertising modes for auto-negotiation */ |
---|
| 476 | advmodes = sc->advmodes; |
---|
| 477 | if (advmodes == 0) |
---|
| 478 | advmodes = GRETH_ADV_ALL; |
---|
| 479 | if (!sc->gbit_mac) |
---|
| 480 | advmodes &= ~(GRETH_ADV_1000_FD | GRETH_ADV_1000_HD); |
---|
| 481 | |
---|
[107c5aea] | 482 | /* Enable/Disable GBit auto-neg advetisement so that the link partner |
---|
| 483 | * know that we have/haven't GBit capability. The MAC may not support |
---|
| 484 | * Gbit even though PHY does... |
---|
| 485 | */ |
---|
[a79c36ad] | 486 | phystatus = read_mii(sc, phyaddr, 1); |
---|
[107c5aea] | 487 | if (phystatus & 0x0100) { |
---|
| 488 | tmp1 = read_mii(sc, phyaddr, 9); |
---|
[e6fbd26] | 489 | tmp1 &= ~0x300; |
---|
| 490 | if (advmodes & GRETH_ADV_1000_FD) |
---|
| 491 | tmp1 |= 0x200; |
---|
| 492 | if (advmodes & GRETH_ADV_1000_HD) |
---|
| 493 | tmp1 |= 0x100; |
---|
| 494 | write_mii(sc, phyaddr, 9, tmp1); |
---|
[107c5aea] | 495 | } |
---|
| 496 | |
---|
[e6fbd26] | 497 | /* Optionally limit the 10/100 modes as configured by user */ |
---|
| 498 | tmp1 = read_mii(sc, phyaddr, 4); |
---|
| 499 | tmp1 &= ~0x1e0; |
---|
| 500 | if (advmodes & GRETH_ADV_100_FD) |
---|
| 501 | tmp1 |= 0x100; |
---|
| 502 | if (advmodes & GRETH_ADV_100_HD) |
---|
| 503 | tmp1 |= 0x080; |
---|
| 504 | if (advmodes & GRETH_ADV_10_FD) |
---|
| 505 | tmp1 |= 0x040; |
---|
| 506 | if (advmodes & GRETH_ADV_10_HD) |
---|
| 507 | tmp1 |= 0x020; |
---|
| 508 | write_mii(sc, phyaddr, 4, tmp1); |
---|
| 509 | |
---|
[107c5aea] | 510 | /* If autonegotiation implemented we start it */ |
---|
[a79c36ad] | 511 | if (phystatus & 0x0008) { |
---|
| 512 | write_mii(sc, phyaddr, 0, phyctrl | 0x1200); |
---|
| 513 | phyctrl = read_mii(sc, phyaddr, 0); |
---|
| 514 | } |
---|
| 515 | |
---|
[3bb4122] | 516 | /* Check if PHY is autoneg capable and then determine operating mode, |
---|
| 517 | otherwise force it to 10 Mbit halfduplex */ |
---|
| 518 | sc->gb = 0; |
---|
| 519 | sc->fd = 0; |
---|
| 520 | sc->sp = 0; |
---|
| 521 | sc->auto_neg = 0; |
---|
| 522 | _Timespec_Set_to_zero(&sc->auto_neg_time); |
---|
| 523 | if ((phyctrl >> 12) & 1) { |
---|
| 524 | /*wait for auto negotiation to complete*/ |
---|
| 525 | sc->auto_neg = 1; |
---|
| 526 | if (rtems_clock_get_uptime(&tstart) != RTEMS_SUCCESSFUL) |
---|
| 527 | printk("rtems_clock_get_uptime failed\n"); |
---|
| 528 | while (!(((phystatus = read_mii(sc, phyaddr, 1)) >> 5) & 1)) { |
---|
| 529 | if (rtems_clock_get_uptime(&tnow) != RTEMS_SUCCESSFUL) |
---|
| 530 | printk("rtems_clock_get_uptime failed\n"); |
---|
| 531 | _Timespec_Subtract(&tstart, &tnow, &sc->auto_neg_time); |
---|
| 532 | if (_Timespec_Greater_than(&sc->auto_neg_time, &greth_tan)) { |
---|
| 533 | sc->auto_neg = -1; /* Failed */ |
---|
| 534 | tmp1 = read_mii(sc, phyaddr, 0); |
---|
| 535 | sc->gb = ((phyctrl >> 6) & 1) && !((phyctrl >> 13) & 1); |
---|
| 536 | sc->sp = !((phyctrl >> 6) & 1) && ((phyctrl >> 13) & 1); |
---|
| 537 | sc->fd = (phyctrl >> 8) & 1; |
---|
| 538 | goto auto_neg_done; |
---|
| 539 | } |
---|
| 540 | /* Wait about 30ms, time is PHY dependent */ |
---|
| 541 | rtems_task_wake_after(rtems_clock_get_ticks_per_second()/32); |
---|
| 542 | } |
---|
| 543 | sc->phydev.adv = read_mii(sc, phyaddr, 4); |
---|
| 544 | sc->phydev.part = read_mii(sc, phyaddr, 5); |
---|
| 545 | if ((phystatus >> 8) & 1) { |
---|
| 546 | sc->phydev.extadv = read_mii(sc, phyaddr, 9); |
---|
| 547 | sc->phydev.extpart = read_mii(sc, phyaddr, 10); |
---|
| 548 | if ( (sc->phydev.extadv & GRETH_MII_EXTADV_1000HD) && |
---|
| 549 | (sc->phydev.extpart & GRETH_MII_EXTPRT_1000HD)) { |
---|
| 550 | sc->gb = 1; |
---|
| 551 | sc->fd = 0; |
---|
| 552 | } |
---|
[430949aa] | 553 | if ( (sc->phydev.extadv & GRETH_MII_EXTADV_1000FD) && |
---|
| 554 | (sc->phydev.extpart & GRETH_MII_EXTPRT_1000FD)) { |
---|
| 555 | sc->gb = 1; |
---|
| 556 | sc->fd = 1; |
---|
| 557 | } |
---|
[3bb4122] | 558 | } |
---|
| 559 | if ((sc->gb == 0) || ((sc->gb == 1) && (sc->gbit_mac == 0))) { |
---|
| 560 | if ( (sc->phydev.adv & GRETH_MII_100TXFD) && |
---|
| 561 | (sc->phydev.part & GRETH_MII_100TXFD)) { |
---|
| 562 | sc->sp = 1; |
---|
| 563 | sc->fd = 1; |
---|
[8ac070a] | 564 | } else if ( (sc->phydev.adv & GRETH_MII_100TXHD) && |
---|
| 565 | (sc->phydev.part & GRETH_MII_100TXHD)) { |
---|
[3bb4122] | 566 | sc->sp = 1; |
---|
| 567 | sc->fd = 0; |
---|
[8ac070a] | 568 | } else if ( (sc->phydev.adv & GRETH_MII_10FD) && |
---|
| 569 | (sc->phydev.part & GRETH_MII_10FD)) { |
---|
[3bb4122] | 570 | sc->fd = 1; |
---|
| 571 | } |
---|
| 572 | } |
---|
| 573 | } |
---|
| 574 | auto_neg_done: |
---|
| 575 | sc->phydev.vendor = 0; |
---|
| 576 | sc->phydev.device = 0; |
---|
| 577 | sc->phydev.rev = 0; |
---|
| 578 | phystatus = read_mii(sc, phyaddr, 1); |
---|
[37ac3b86] | 579 | |
---|
| 580 | /* Read out PHY info if extended registers are available */ |
---|
[3bb4122] | 581 | if (phystatus & 1) { |
---|
| 582 | tmp1 = read_mii(sc, phyaddr, 2); |
---|
| 583 | tmp2 = read_mii(sc, phyaddr, 3); |
---|
| 584 | |
---|
| 585 | sc->phydev.vendor = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F); |
---|
| 586 | sc->phydev.rev = tmp2 & 0xF; |
---|
| 587 | sc->phydev.device = (tmp2 >> 4) & 0x3F; |
---|
| 588 | } |
---|
| 589 | |
---|
[37ac3b86] | 590 | /* Force to 10 mbit half duplex if the 10/100 MAC is used with a 1000 PHY */ |
---|
| 591 | if (((sc->gb) && !(sc->gbit_mac)) || !((phyctrl >> 12) & 1)) { |
---|
| 592 | write_mii(sc, phyaddr, 0, sc->sp << 13); |
---|
| 593 | |
---|
| 594 | /* check if marvell 88EE1111 PHY. Needs special reset handling */ |
---|
| 595 | if ((phystatus & 1) && (sc->phydev.vendor == 0x005043) && |
---|
| 596 | (sc->phydev.device == 0x0C)) |
---|
| 597 | write_mii(sc, phyaddr, 0, 0x8000); |
---|
| 598 | |
---|
| 599 | sc->gb = 0; |
---|
| 600 | sc->sp = 0; |
---|
| 601 | sc->fd = 0; |
---|
[3bb4122] | 602 | } |
---|
| 603 | while ((read_mii(sc, phyaddr, 0)) & 0x8000) {} |
---|
| 604 | |
---|
[fa27fe5c] | 605 | if (sc->greth_rst) { |
---|
| 606 | /* Reset ON */ |
---|
| 607 | regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; |
---|
| 608 | for (i = 0; i < 100 && (regs->ctrl & GRETH_CTRL_RST); i++) |
---|
| 609 | ; |
---|
| 610 | } |
---|
| 611 | /* Reset OFF. Set mode matching PHY settings. */ |
---|
| 612 | speed = (sc->gb << 8) | (sc->sp << 7) | (sc->fd << 4); |
---|
| 613 | regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed; |
---|
[3bb4122] | 614 | |
---|
| 615 | /* Initialize rx/tx descriptor table pointers. Due to alignment we |
---|
| 616 | * always allocate maximum table size. |
---|
| 617 | */ |
---|
| 618 | sc->txdesc = (greth_rxtxdesc *) almalloc(0x800, 0x400); |
---|
| 619 | sc->rxdesc = (greth_rxtxdesc *) &sc->txdesc[128]; |
---|
| 620 | sc->tx_ptr = 0; |
---|
| 621 | sc->tx_dptr = 0; |
---|
| 622 | sc->tx_cnt = 0; |
---|
| 623 | sc->rx_ptr = 0; |
---|
| 624 | |
---|
| 625 | /* Translate the Descriptor DMA table base address into an address that |
---|
| 626 | * the GRETH core can understand |
---|
| 627 | */ |
---|
| 628 | drvmgr_translate_check( |
---|
| 629 | sc->dev, |
---|
| 630 | CPUMEM_TO_DMA, |
---|
| 631 | (void *)sc->txdesc, |
---|
| 632 | (void **)&sc->txdesc_remote, |
---|
| 633 | 0x800); |
---|
| 634 | sc->rxdesc_remote = sc->txdesc_remote + 0x400; |
---|
| 635 | regs->txdesc = (int) sc->txdesc_remote; |
---|
| 636 | regs->rxdesc = (int) sc->rxdesc_remote; |
---|
| 637 | |
---|
[11f3b9a] | 638 | sc->rxmbuf = grlib_calloc(sc->rxbufs, sizeof(*sc->rxmbuf)); |
---|
| 639 | sc->txmbuf = grlib_calloc(sc->txbufs, sizeof(*sc->txmbuf)); |
---|
[3bb4122] | 640 | |
---|
| 641 | for (i = 0; i < sc->txbufs; i++) |
---|
| 642 | { |
---|
| 643 | sc->txdesc[i].ctrl = 0; |
---|
| 644 | if (!(sc->gbit_mac)) { |
---|
| 645 | drvmgr_translate_check( |
---|
| 646 | sc->dev, |
---|
| 647 | CPUMEM_TO_DMA, |
---|
[11f3b9a] | 648 | (void *)grlib_malloc(GRETH_MAXBUF_LEN), |
---|
[3bb4122] | 649 | (void **)&sc->txdesc[i].addr, |
---|
| 650 | GRETH_MAXBUF_LEN); |
---|
| 651 | } |
---|
| 652 | #ifdef GRETH_DEBUG |
---|
| 653 | /* printf("TXBUF: %08x\n", (int) sc->txdesc[i].addr); */ |
---|
| 654 | #endif |
---|
| 655 | } |
---|
| 656 | for (i = 0; i < sc->rxbufs; i++) |
---|
| 657 | { |
---|
| 658 | MGETHDR (m, M_WAIT, MT_DATA); |
---|
| 659 | MCLGET (m, M_WAIT); |
---|
| 660 | if (sc->gbit_mac) |
---|
| 661 | m->m_data += 2; |
---|
| 662 | m->m_pkthdr.rcvif = &sc->arpcom.ac_if; |
---|
| 663 | sc->rxmbuf[i] = m; |
---|
| 664 | drvmgr_translate_check( |
---|
| 665 | sc->dev, |
---|
| 666 | CPUMEM_TO_DMA, |
---|
| 667 | (void *)mtod(m, uint32_t *), |
---|
| 668 | (void **)&sc->rxdesc[i].addr, |
---|
| 669 | GRETH_MAXBUF_LEN); |
---|
| 670 | sc->rxdesc[i].ctrl = GRETH_RXD_ENABLE | GRETH_RXD_IRQ; |
---|
| 671 | #ifdef GRETH_DEBUG |
---|
| 672 | /* printf("RXBUF: %08x\n", (int) sc->rxdesc[i].addr); */ |
---|
| 673 | #endif |
---|
| 674 | } |
---|
| 675 | sc->rxdesc[sc->rxbufs - 1].ctrl |= GRETH_RXD_WRAP; |
---|
| 676 | |
---|
| 677 | /* set ethernet address. */ |
---|
| 678 | regs->mac_addr_msb = |
---|
| 679 | sc->arpcom.ac_enaddr[0] << 8 | sc->arpcom.ac_enaddr[1]; |
---|
| 680 | regs->mac_addr_lsb = |
---|
| 681 | sc->arpcom.ac_enaddr[2] << 24 | sc->arpcom.ac_enaddr[3] << 16 | |
---|
| 682 | sc->arpcom.ac_enaddr[4] << 8 | sc->arpcom.ac_enaddr[5]; |
---|
| 683 | |
---|
| 684 | if ( sc->rxbufs < 10 ) { |
---|
| 685 | sc->tx_int_gen = sc->tx_int_gen_cur = 1; |
---|
| 686 | }else{ |
---|
| 687 | sc->tx_int_gen = sc->tx_int_gen_cur = sc->txbufs/2; |
---|
| 688 | } |
---|
| 689 | sc->next_tx_mbuf = NULL; |
---|
[12718134] | 690 | |
---|
[3bb4122] | 691 | if ( !sc->gbit_mac ) |
---|
| 692 | sc->max_fragsize = 1; |
---|
| 693 | |
---|
| 694 | /* clear all pending interrupts */ |
---|
| 695 | regs->status = 0xffffffff; |
---|
| 696 | |
---|
| 697 | /* install interrupt handler */ |
---|
| 698 | drvmgr_interrupt_register(sc->dev, 0, "greth", greth_interrupt, sc); |
---|
| 699 | |
---|
[fa27fe5c] | 700 | regs->ctrl |= GRETH_CTRL_RXEN | GRETH_CTRL_RXIRQ; |
---|
[3bb4122] | 701 | |
---|
| 702 | print_init_info(sc); |
---|
| 703 | } |
---|
| 704 | |
---|
| 705 | #ifdef CPU_U32_FIX |
---|
| 706 | |
---|
| 707 | /* |
---|
| 708 | * Routine to align the received packet so that the ip header |
---|
| 709 | * is on a 32-bit boundary. Necessary for cpu's that do not |
---|
| 710 | * allow unaligned loads and stores and when the 32-bit DMA |
---|
| 711 | * mode is used. |
---|
| 712 | * |
---|
| 713 | * Transfers are done on word basis to avoid possibly slow byte |
---|
| 714 | * and half-word writes. |
---|
| 715 | */ |
---|
| 716 | |
---|
| 717 | void ipalign(struct mbuf *m) |
---|
| 718 | { |
---|
| 719 | unsigned int *first, *last, data; |
---|
| 720 | unsigned int tmp = 0; |
---|
| 721 | |
---|
| 722 | if ((((int) m->m_data) & 2) && (m->m_len)) { |
---|
| 723 | last = (unsigned int *) ((((int) m->m_data) + m->m_len + 8) & ~3); |
---|
| 724 | first = (unsigned int *) (((int) m->m_data) & ~3); |
---|
| 725 | /* tmp = *first << 16; */ |
---|
| 726 | asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(first) ); |
---|
| 727 | tmp = tmp << 16; |
---|
| 728 | first++; |
---|
| 729 | do { |
---|
| 730 | /* When snooping is not available the LDA instruction must be used |
---|
| 731 | * to avoid the cache to return an illegal value. |
---|
| 732 | ** Load with forced cache miss |
---|
| 733 | * data = *first; |
---|
| 734 | */ |
---|
| 735 | asm volatile (" lda [%1] 1, %0\n" : "=r"(data) : "r"(first) ); |
---|
| 736 | *first = tmp | (data >> 16); |
---|
| 737 | tmp = data << 16; |
---|
| 738 | first++; |
---|
| 739 | } while (first <= last); |
---|
| 740 | |
---|
| 741 | m->m_data = (caddr_t)(((int) m->m_data) + 2); |
---|
| 742 | } |
---|
| 743 | } |
---|
| 744 | #endif |
---|
| 745 | |
---|
[aedc9849] | 746 | static void |
---|
[3bb4122] | 747 | greth_Daemon (void *arg) |
---|
| 748 | { |
---|
| 749 | struct ether_header *eh; |
---|
| 750 | struct greth_softc *dp = (struct greth_softc *) arg; |
---|
| 751 | struct ifnet *ifp = &dp->arpcom.ac_if; |
---|
| 752 | struct mbuf *m; |
---|
| 753 | unsigned int len, len_status, bad; |
---|
| 754 | rtems_event_set events; |
---|
[998e34ad] | 755 | SPIN_IRQFLAGS(flags); |
---|
[3bb4122] | 756 | int first; |
---|
[998e34ad] | 757 | int tmp; |
---|
| 758 | unsigned int addr; |
---|
| 759 | |
---|
[3bb4122] | 760 | for (;;) |
---|
| 761 | { |
---|
| 762 | rtems_bsdnet_event_receive (INTERRUPT_EVENT | GRETH_TX_WAIT_EVENT, |
---|
| 763 | RTEMS_WAIT | RTEMS_EVENT_ANY, |
---|
| 764 | RTEMS_NO_TIMEOUT, &events); |
---|
| 765 | |
---|
| 766 | if ( events & GRETH_TX_WAIT_EVENT ){ |
---|
| 767 | /* TX interrupt. |
---|
| 768 | * We only end up here when all TX descriptors has been used, |
---|
| 769 | * and |
---|
| 770 | */ |
---|
| 771 | if ( dp->gbit_mac ) |
---|
| 772 | greth_process_tx_gbit(dp); |
---|
| 773 | else |
---|
| 774 | greth_process_tx(dp); |
---|
| 775 | |
---|
| 776 | /* If we didn't get a RX interrupt we don't process it */ |
---|
| 777 | if ( (events & INTERRUPT_EVENT) == 0 ) |
---|
| 778 | continue; |
---|
| 779 | } |
---|
| 780 | |
---|
| 781 | |
---|
| 782 | #ifdef GRETH_ETH_DEBUG |
---|
| 783 | printf ("r\n"); |
---|
| 784 | #endif |
---|
| 785 | first=1; |
---|
| 786 | /* Scan for Received packets */ |
---|
| 787 | again: |
---|
| 788 | while (!((len_status = |
---|
| 789 | GRETH_MEM_LOAD(&dp->rxdesc[dp->rx_ptr].ctrl)) & GRETH_RXD_ENABLE)) |
---|
| 790 | { |
---|
| 791 | bad = 0; |
---|
| 792 | if (len_status & GRETH_RXD_TOOLONG) |
---|
| 793 | { |
---|
| 794 | dp->rxLengthError++; |
---|
| 795 | bad = 1; |
---|
| 796 | } |
---|
| 797 | if (len_status & GRETH_RXD_DRIBBLE) |
---|
| 798 | { |
---|
| 799 | dp->rxNonOctet++; |
---|
| 800 | bad = 1; |
---|
| 801 | } |
---|
| 802 | if (len_status & GRETH_RXD_CRCERR) |
---|
| 803 | { |
---|
| 804 | dp->rxBadCRC++; |
---|
| 805 | bad = 1; |
---|
| 806 | } |
---|
| 807 | if (len_status & GRETH_RXD_OVERRUN) |
---|
| 808 | { |
---|
| 809 | dp->rxOverrun++; |
---|
| 810 | bad = 1; |
---|
| 811 | } |
---|
| 812 | if (len_status & GRETH_RXD_LENERR) |
---|
| 813 | { |
---|
| 814 | dp->rxLengthError++; |
---|
| 815 | bad = 1; |
---|
| 816 | } |
---|
| 817 | if (!bad) |
---|
| 818 | { |
---|
| 819 | /* pass on the packet in the receive buffer */ |
---|
| 820 | len = len_status & 0x7FF; |
---|
| 821 | m = dp->rxmbuf[dp->rx_ptr]; |
---|
| 822 | #ifdef GRETH_DEBUG |
---|
| 823 | int i; |
---|
| 824 | printf("RX: 0x%08x, Len: %d : ", (int) m->m_data, len); |
---|
| 825 | for (i=0; i<len; i++) |
---|
| 826 | printf("%x%x", (m->m_data[i] >> 4) & 0x0ff, m->m_data[i] & 0x0ff); |
---|
| 827 | printf("\n"); |
---|
| 828 | #endif |
---|
| 829 | m->m_len = m->m_pkthdr.len = |
---|
| 830 | len - sizeof (struct ether_header); |
---|
| 831 | |
---|
| 832 | eh = mtod (m, struct ether_header *); |
---|
| 833 | |
---|
| 834 | m->m_data += sizeof (struct ether_header); |
---|
| 835 | #ifdef CPU_U32_FIX |
---|
| 836 | if(!dp->gbit_mac) { |
---|
| 837 | /* OVERRIDE CACHED ETHERNET HEADER FOR NON-SNOOPING SYSTEMS */ |
---|
| 838 | addr = (unsigned int)eh; |
---|
| 839 | asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr) ); |
---|
| 840 | addr+=4; |
---|
| 841 | asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr) ); |
---|
| 842 | addr+=4; |
---|
| 843 | asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr) ); |
---|
| 844 | addr+=4; |
---|
| 845 | asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr) ); |
---|
| 846 | |
---|
| 847 | ipalign(m); /* Align packet on 32-bit boundary */ |
---|
| 848 | } |
---|
| 849 | #endif |
---|
| 850 | /* |
---|
| 851 | if(!(dp->gbit_mac) && !CPU_SPARC_HAS_SNOOPING) { |
---|
| 852 | rtems_cache_invalidate_entire_data(); |
---|
| 853 | } |
---|
| 854 | */ |
---|
| 855 | ether_input (ifp, eh, m); |
---|
| 856 | MGETHDR (m, M_WAIT, MT_DATA); |
---|
| 857 | MCLGET (m, M_WAIT); |
---|
| 858 | if (dp->gbit_mac) |
---|
| 859 | m->m_data += 2; |
---|
| 860 | dp->rxmbuf[dp->rx_ptr] = m; |
---|
| 861 | m->m_pkthdr.rcvif = ifp; |
---|
| 862 | drvmgr_translate_check( |
---|
| 863 | dp->dev, |
---|
| 864 | CPUMEM_TO_DMA, |
---|
| 865 | (void *)mtod (m, uint32_t *), |
---|
| 866 | (void **)&dp->rxdesc[dp->rx_ptr].addr, |
---|
| 867 | GRETH_MAXBUF_LEN); |
---|
| 868 | dp->rxPackets++; |
---|
| 869 | } |
---|
| 870 | if (dp->rx_ptr == dp->rxbufs - 1) { |
---|
| 871 | dp->rxdesc[dp->rx_ptr].ctrl = GRETH_RXD_ENABLE | GRETH_RXD_IRQ | GRETH_RXD_WRAP; |
---|
| 872 | } else { |
---|
| 873 | dp->rxdesc[dp->rx_ptr].ctrl = GRETH_RXD_ENABLE | GRETH_RXD_IRQ; |
---|
| 874 | } |
---|
[998e34ad] | 875 | SPIN_LOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 876 | dp->regs->ctrl |= GRETH_CTRL_RXEN; |
---|
[998e34ad] | 877 | SPIN_UNLOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 878 | dp->rx_ptr = (dp->rx_ptr + 1) % dp->rxbufs; |
---|
| 879 | } |
---|
[998e34ad] | 880 | |
---|
[3bb4122] | 881 | /* Always scan twice to avoid deadlock */ |
---|
| 882 | if ( first ){ |
---|
| 883 | first=0; |
---|
[998e34ad] | 884 | SPIN_LOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 885 | dp->regs->ctrl |= GRETH_CTRL_RXIRQ; |
---|
[998e34ad] | 886 | SPIN_UNLOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 887 | goto again; |
---|
| 888 | } |
---|
| 889 | |
---|
| 890 | } |
---|
| 891 | } |
---|
| 892 | |
---|
| 893 | static int |
---|
| 894 | sendpacket (struct ifnet *ifp, struct mbuf *m) |
---|
| 895 | { |
---|
| 896 | struct greth_softc *dp = ifp->if_softc; |
---|
| 897 | unsigned char *temp; |
---|
| 898 | struct mbuf *n; |
---|
| 899 | unsigned int len; |
---|
[998e34ad] | 900 | SPIN_IRQFLAGS(flags); |
---|
| 901 | |
---|
[3bb4122] | 902 | /* |
---|
| 903 | * Is there a free descriptor available? |
---|
| 904 | */ |
---|
| 905 | if (GRETH_MEM_LOAD(&dp->txdesc[dp->tx_ptr].ctrl) & GRETH_TXD_ENABLE){ |
---|
| 906 | /* No. */ |
---|
| 907 | return 1; |
---|
| 908 | } |
---|
| 909 | |
---|
| 910 | /* Remember head of chain */ |
---|
| 911 | n = m; |
---|
| 912 | |
---|
| 913 | len = 0; |
---|
| 914 | temp = (unsigned char *) GRETH_MEM_LOAD(&dp->txdesc[dp->tx_ptr].addr); |
---|
| 915 | drvmgr_translate(dp->dev, CPUMEM_FROM_DMA, (void *)temp, (void **)&temp); |
---|
| 916 | #ifdef GRETH_DEBUG |
---|
| 917 | printf("TXD: 0x%08x : BUF: 0x%08x\n", (int) m->m_data, (int) temp); |
---|
| 918 | #endif |
---|
| 919 | for (;;) |
---|
| 920 | { |
---|
| 921 | #ifdef GRETH_DEBUG |
---|
| 922 | int i; |
---|
| 923 | printf("MBUF: 0x%08x : ", (int) m->m_data); |
---|
| 924 | for (i=0;i<m->m_len;i++) |
---|
| 925 | printf("%x%x", (m->m_data[i] >> 4) & 0x0ff, m->m_data[i] & 0x0ff); |
---|
| 926 | printf("\n"); |
---|
| 927 | #endif |
---|
| 928 | len += m->m_len; |
---|
| 929 | if (len <= RBUF_SIZE) |
---|
| 930 | memcpy ((void *) temp, (char *) m->m_data, m->m_len); |
---|
| 931 | temp += m->m_len; |
---|
| 932 | if ((m = m->m_next) == NULL) |
---|
| 933 | break; |
---|
| 934 | } |
---|
[2fbe2ef3] | 935 | |
---|
[3bb4122] | 936 | m_freem (n); |
---|
[2fbe2ef3] | 937 | |
---|
[3bb4122] | 938 | /* don't send long packets */ |
---|
| 939 | |
---|
| 940 | if (len <= GRETH_MAXBUF_LEN) { |
---|
| 941 | if (dp->tx_ptr < dp->txbufs-1) { |
---|
[2fbe2ef3] | 942 | dp->txdesc[dp->tx_ptr].ctrl = GRETH_TXD_IRQ | |
---|
| 943 | GRETH_TXD_ENABLE | len; |
---|
[3bb4122] | 944 | } else { |
---|
[2fbe2ef3] | 945 | dp->txdesc[dp->tx_ptr].ctrl = GRETH_TXD_IRQ | |
---|
[3bb4122] | 946 | GRETH_TXD_WRAP | GRETH_TXD_ENABLE | len; |
---|
| 947 | } |
---|
| 948 | dp->tx_ptr = (dp->tx_ptr + 1) % dp->txbufs; |
---|
[998e34ad] | 949 | SPIN_LOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 950 | dp->regs->ctrl = dp->regs->ctrl | GRETH_CTRL_TXEN; |
---|
[998e34ad] | 951 | SPIN_UNLOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 952 | } |
---|
[998e34ad] | 953 | |
---|
[3bb4122] | 954 | return 0; |
---|
| 955 | } |
---|
| 956 | |
---|
| 957 | |
---|
[aedc9849] | 958 | static int |
---|
[3bb4122] | 959 | sendpacket_gbit (struct ifnet *ifp, struct mbuf *m) |
---|
| 960 | { |
---|
| 961 | struct greth_softc *dp = ifp->if_softc; |
---|
| 962 | unsigned int len; |
---|
| 963 | |
---|
| 964 | unsigned int ctrl; |
---|
| 965 | int frags; |
---|
| 966 | struct mbuf *mtmp; |
---|
| 967 | int int_en; |
---|
[998e34ad] | 968 | SPIN_IRQFLAGS(flags); |
---|
[3bb4122] | 969 | |
---|
| 970 | len = 0; |
---|
| 971 | #ifdef GRETH_DEBUG |
---|
| 972 | printf("TXD: 0x%08x\n", (int) m->m_data); |
---|
| 973 | #endif |
---|
| 974 | /* Get number of fragments too see if we have enough |
---|
| 975 | * resources. |
---|
| 976 | */ |
---|
| 977 | frags=1; |
---|
| 978 | mtmp=m; |
---|
| 979 | while(mtmp->m_next){ |
---|
| 980 | frags++; |
---|
| 981 | mtmp = mtmp->m_next; |
---|
| 982 | } |
---|
| 983 | |
---|
| 984 | if ( frags > dp->max_fragsize ) |
---|
| 985 | dp->max_fragsize = frags; |
---|
| 986 | |
---|
| 987 | if ( frags > dp->txbufs ){ |
---|
| 988 | printf("GRETH: MBUF-chain cannot be sent. Increase descriptor count.\n"); |
---|
| 989 | return -1; |
---|
| 990 | } |
---|
| 991 | |
---|
| 992 | if ( frags > (dp->txbufs-dp->tx_cnt) ){ |
---|
| 993 | /* Return number of fragments */ |
---|
| 994 | return frags; |
---|
| 995 | } |
---|
| 996 | |
---|
| 997 | |
---|
| 998 | /* Enable interrupt from descriptor every tx_int_gen |
---|
| 999 | * descriptor. Typically every 16 descriptor. This |
---|
| 1000 | * is only to reduce the number of interrupts during |
---|
| 1001 | * heavy load. |
---|
| 1002 | */ |
---|
| 1003 | dp->tx_int_gen_cur-=frags; |
---|
| 1004 | if ( dp->tx_int_gen_cur <= 0 ){ |
---|
| 1005 | dp->tx_int_gen_cur = dp->tx_int_gen; |
---|
| 1006 | int_en = GRETH_TXD_IRQ; |
---|
| 1007 | }else{ |
---|
| 1008 | int_en = 0; |
---|
| 1009 | } |
---|
| 1010 | |
---|
| 1011 | /* At this stage we know that enough descriptors are available */ |
---|
| 1012 | for (;;) |
---|
| 1013 | { |
---|
| 1014 | |
---|
| 1015 | #ifdef GRETH_DEBUG |
---|
| 1016 | int i; |
---|
| 1017 | printf("MBUF: 0x%08x, Len: %d : ", (int) m->m_data, m->m_len); |
---|
| 1018 | for (i=0; i<m->m_len; i++) |
---|
| 1019 | printf("%x%x", (m->m_data[i] >> 4) & 0x0ff, m->m_data[i] & 0x0ff); |
---|
| 1020 | printf("\n"); |
---|
| 1021 | #endif |
---|
| 1022 | len += m->m_len; |
---|
| 1023 | drvmgr_translate_check( |
---|
| 1024 | dp->dev, |
---|
| 1025 | CPUMEM_TO_DMA, |
---|
| 1026 | (void *)(uint32_t *)m->m_data, |
---|
| 1027 | (void **)&dp->txdesc[dp->tx_ptr].addr, |
---|
| 1028 | m->m_len); |
---|
| 1029 | |
---|
| 1030 | /* Wrap around? */ |
---|
| 1031 | if (dp->tx_ptr < dp->txbufs-1) { |
---|
[9b8e04e2] | 1032 | ctrl = GRETH_TXD_ENABLE; |
---|
[3bb4122] | 1033 | }else{ |
---|
[9b8e04e2] | 1034 | ctrl = GRETH_TXD_ENABLE | GRETH_TXD_WRAP; |
---|
[3bb4122] | 1035 | } |
---|
| 1036 | |
---|
| 1037 | /* Enable Descriptor */ |
---|
| 1038 | if ((m->m_next) == NULL) { |
---|
| 1039 | dp->txdesc[dp->tx_ptr].ctrl = ctrl | int_en | m->m_len; |
---|
| 1040 | break; |
---|
| 1041 | }else{ |
---|
| 1042 | dp->txdesc[dp->tx_ptr].ctrl = GRETH_TXD_MORE | ctrl | int_en | m->m_len; |
---|
| 1043 | } |
---|
| 1044 | |
---|
| 1045 | /* Next */ |
---|
| 1046 | dp->txmbuf[dp->tx_ptr] = m; |
---|
| 1047 | dp->tx_ptr = (dp->tx_ptr + 1) % dp->txbufs; |
---|
| 1048 | dp->tx_cnt++; |
---|
| 1049 | m = m->m_next; |
---|
| 1050 | } |
---|
| 1051 | dp->txmbuf[dp->tx_ptr] = m; |
---|
| 1052 | dp->tx_ptr = (dp->tx_ptr + 1) % dp->txbufs; |
---|
| 1053 | dp->tx_cnt++; |
---|
| 1054 | |
---|
| 1055 | /* Tell Hardware about newly enabled descriptor */ |
---|
[998e34ad] | 1056 | SPIN_LOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 1057 | dp->regs->ctrl = dp->regs->ctrl | GRETH_CTRL_TXEN; |
---|
[998e34ad] | 1058 | SPIN_UNLOCK_IRQ(&dp->devlock, flags); |
---|
[3bb4122] | 1059 | |
---|
| 1060 | return 0; |
---|
| 1061 | } |
---|
| 1062 | |
---|
| 1063 | int greth_process_tx_gbit(struct greth_softc *sc) |
---|
| 1064 | { |
---|
| 1065 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
| 1066 | struct mbuf *m; |
---|
[998e34ad] | 1067 | SPIN_IRQFLAGS(flags); |
---|
[3bb4122] | 1068 | int first=1; |
---|
[998e34ad] | 1069 | |
---|
[3bb4122] | 1070 | /* |
---|
| 1071 | * Send packets till queue is empty |
---|
| 1072 | */ |
---|
| 1073 | for (;;){ |
---|
| 1074 | /* Reap Sent packets */ |
---|
| 1075 | while((sc->tx_cnt > 0) && !(GRETH_MEM_LOAD(&sc->txdesc[sc->tx_dptr].ctrl) & GRETH_TXD_ENABLE)) { |
---|
| 1076 | m_free(sc->txmbuf[sc->tx_dptr]); |
---|
| 1077 | sc->tx_dptr = (sc->tx_dptr + 1) % sc->txbufs; |
---|
| 1078 | sc->tx_cnt--; |
---|
| 1079 | } |
---|
| 1080 | |
---|
| 1081 | if ( sc->next_tx_mbuf ){ |
---|
| 1082 | /* Get packet we tried but faild to transmit last time */ |
---|
| 1083 | m = sc->next_tx_mbuf; |
---|
| 1084 | sc->next_tx_mbuf = NULL; /* Mark packet taken */ |
---|
| 1085 | }else{ |
---|
| 1086 | /* |
---|
| 1087 | * Get the next mbuf chain to transmit from Stack. |
---|
| 1088 | */ |
---|
| 1089 | IF_DEQUEUE (&ifp->if_snd, m); |
---|
| 1090 | if (!m){ |
---|
| 1091 | /* Hardware has sent all schedule packets, this |
---|
| 1092 | * makes the stack enter at greth_start next time |
---|
| 1093 | * a packet is to be sent. |
---|
| 1094 | */ |
---|
| 1095 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
| 1096 | break; |
---|
| 1097 | } |
---|
| 1098 | } |
---|
| 1099 | |
---|
| 1100 | /* Are there free descriptors available? */ |
---|
| 1101 | /* Try to send packet, if it a negative number is returned. */ |
---|
| 1102 | if ( (sc->tx_cnt >= sc->txbufs) || sendpacket_gbit(ifp, m) ){ |
---|
| 1103 | /* Not enough resources */ |
---|
| 1104 | |
---|
| 1105 | /* Since we have taken the mbuf out of the "send chain" |
---|
| 1106 | * we must remember to use that next time we come back. |
---|
| 1107 | * or else we have dropped a packet. |
---|
| 1108 | */ |
---|
| 1109 | sc->next_tx_mbuf = m; |
---|
| 1110 | |
---|
| 1111 | /* Not enough resources, enable interrupt for transmissions |
---|
| 1112 | * this way we will be informed when more TX-descriptors are |
---|
| 1113 | * available. |
---|
| 1114 | */ |
---|
| 1115 | if ( first ){ |
---|
| 1116 | first = 0; |
---|
[998e34ad] | 1117 | SPIN_LOCK_IRQ(&sc->devlock, flags); |
---|
[3bb4122] | 1118 | ifp->if_flags |= IFF_OACTIVE; |
---|
| 1119 | sc->regs->ctrl |= GRETH_CTRL_TXIRQ; |
---|
[998e34ad] | 1120 | SPIN_UNLOCK_IRQ(&sc->devlock, flags); |
---|
[3bb4122] | 1121 | |
---|
| 1122 | /* We must check again to be sure that we didn't |
---|
| 1123 | * miss an interrupt (if a packet was sent just before |
---|
| 1124 | * enabling interrupts) |
---|
| 1125 | */ |
---|
| 1126 | continue; |
---|
| 1127 | } |
---|
[998e34ad] | 1128 | |
---|
[3bb4122] | 1129 | return -1; |
---|
| 1130 | }else{ |
---|
| 1131 | /* Sent Ok, proceed to process more packets if available */ |
---|
| 1132 | } |
---|
| 1133 | } |
---|
| 1134 | return 0; |
---|
| 1135 | } |
---|
| 1136 | |
---|
| 1137 | int greth_process_tx(struct greth_softc *sc) |
---|
| 1138 | { |
---|
| 1139 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
| 1140 | struct mbuf *m; |
---|
[998e34ad] | 1141 | SPIN_IRQFLAGS(flags); |
---|
[3bb4122] | 1142 | int first=1; |
---|
[998e34ad] | 1143 | |
---|
[3bb4122] | 1144 | /* |
---|
| 1145 | * Send packets till queue is empty |
---|
| 1146 | */ |
---|
| 1147 | for (;;){ |
---|
| 1148 | if ( sc->next_tx_mbuf ){ |
---|
| 1149 | /* Get packet we tried but failed to transmit last time */ |
---|
| 1150 | m = sc->next_tx_mbuf; |
---|
| 1151 | sc->next_tx_mbuf = NULL; /* Mark packet taken */ |
---|
| 1152 | }else{ |
---|
| 1153 | /* |
---|
| 1154 | * Get the next mbuf chain to transmit from Stack. |
---|
| 1155 | */ |
---|
| 1156 | IF_DEQUEUE (&ifp->if_snd, m); |
---|
| 1157 | if (!m){ |
---|
| 1158 | /* Hardware has sent all schedule packets, this |
---|
| 1159 | * makes the stack enter at greth_start next time |
---|
| 1160 | * a packet is to be sent. |
---|
| 1161 | */ |
---|
| 1162 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
| 1163 | break; |
---|
| 1164 | } |
---|
| 1165 | } |
---|
| 1166 | |
---|
| 1167 | /* Try to send packet, failed if it a non-zero number is returned. */ |
---|
| 1168 | if ( sendpacket(ifp, m) ){ |
---|
| 1169 | /* Not enough resources */ |
---|
| 1170 | |
---|
| 1171 | /* Since we have taken the mbuf out of the "send chain" |
---|
| 1172 | * we must remember to use that next time we come back. |
---|
| 1173 | * or else we have dropped a packet. |
---|
| 1174 | */ |
---|
| 1175 | sc->next_tx_mbuf = m; |
---|
| 1176 | |
---|
| 1177 | /* Not enough resources, enable interrupt for transmissions |
---|
| 1178 | * this way we will be informed when more TX-descriptors are |
---|
| 1179 | * available. |
---|
| 1180 | */ |
---|
| 1181 | if ( first ){ |
---|
| 1182 | first = 0; |
---|
[998e34ad] | 1183 | SPIN_LOCK_IRQ(&sc->devlock, flags); |
---|
[3bb4122] | 1184 | ifp->if_flags |= IFF_OACTIVE; |
---|
| 1185 | sc->regs->ctrl |= GRETH_CTRL_TXIRQ; |
---|
[998e34ad] | 1186 | SPIN_UNLOCK_IRQ(&sc->devlock, flags); |
---|
| 1187 | |
---|
[3bb4122] | 1188 | /* We must check again to be sure that we didn't |
---|
| 1189 | * miss an interrupt (if a packet was sent just before |
---|
| 1190 | * enabling interrupts) |
---|
| 1191 | */ |
---|
| 1192 | continue; |
---|
| 1193 | } |
---|
[998e34ad] | 1194 | |
---|
[3bb4122] | 1195 | return -1; |
---|
| 1196 | }else{ |
---|
| 1197 | /* Sent Ok, proceed to process more packets if available */ |
---|
| 1198 | } |
---|
| 1199 | } |
---|
| 1200 | return 0; |
---|
| 1201 | } |
---|
| 1202 | |
---|
| 1203 | static void |
---|
| 1204 | greth_start (struct ifnet *ifp) |
---|
| 1205 | { |
---|
| 1206 | struct greth_softc *sc = ifp->if_softc; |
---|
| 1207 | |
---|
| 1208 | if ( ifp->if_flags & IFF_OACTIVE ) |
---|
| 1209 | return; |
---|
| 1210 | |
---|
| 1211 | if ( sc->gbit_mac ){ |
---|
| 1212 | /* No use trying to handle this if we are waiting on GRETH |
---|
| 1213 | * to send the previously scheduled packets. |
---|
| 1214 | */ |
---|
| 1215 | |
---|
| 1216 | greth_process_tx_gbit(sc); |
---|
| 1217 | }else{ |
---|
| 1218 | greth_process_tx(sc); |
---|
| 1219 | } |
---|
| 1220 | |
---|
| 1221 | } |
---|
| 1222 | |
---|
| 1223 | /* |
---|
| 1224 | * Initialize and start the device |
---|
| 1225 | */ |
---|
| 1226 | static void |
---|
| 1227 | greth_init (void *arg) |
---|
| 1228 | { |
---|
| 1229 | struct greth_softc *sc = arg; |
---|
| 1230 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
[bee7c46f] | 1231 | char name[4] = {'E', 'T', 'H', '0'}; |
---|
[3bb4122] | 1232 | |
---|
| 1233 | if (sc->daemonTid == 0) |
---|
| 1234 | { |
---|
[998e34ad] | 1235 | /* |
---|
| 1236 | * Start driver tasks |
---|
| 1237 | */ |
---|
| 1238 | name[3] += sc->minor; |
---|
| 1239 | sc->daemonTid = rtems_bsdnet_newproc (name, 4096, |
---|
| 1240 | greth_Daemon, sc); |
---|
| 1241 | |
---|
| 1242 | /* |
---|
| 1243 | * Set up GRETH hardware |
---|
| 1244 | */ |
---|
| 1245 | greth_initialize_hardware (sc); |
---|
[3bb4122] | 1246 | } |
---|
| 1247 | |
---|
[243ddb52] | 1248 | /* |
---|
| 1249 | * Setup promiscous/multi-cast MAC address filters if user enabled it |
---|
| 1250 | */ |
---|
| 1251 | greth_mac_filter_set(sc); |
---|
| 1252 | |
---|
[3bb4122] | 1253 | /* |
---|
| 1254 | * Tell the world that we're running. |
---|
| 1255 | */ |
---|
| 1256 | ifp->if_flags |= IFF_RUNNING; |
---|
| 1257 | } |
---|
| 1258 | |
---|
| 1259 | /* |
---|
| 1260 | * Stop the device |
---|
| 1261 | */ |
---|
| 1262 | static void |
---|
| 1263 | greth_stop (struct greth_softc *sc) |
---|
| 1264 | { |
---|
| 1265 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
[998e34ad] | 1266 | SPIN_IRQFLAGS(flags); |
---|
[fa27fe5c] | 1267 | unsigned int speed; |
---|
[3bb4122] | 1268 | |
---|
[998e34ad] | 1269 | SPIN_LOCK_IRQ(&sc->devlock, flags); |
---|
[3bb4122] | 1270 | ifp->if_flags &= ~IFF_RUNNING; |
---|
| 1271 | |
---|
[fa27fe5c] | 1272 | speed = sc->regs->ctrl & (GRETH_CTRL_GB | GRETH_CTRL_SP | GRETH_CTRL_FULLD); |
---|
| 1273 | |
---|
[12718134] | 1274 | /* RX/TX OFF */ |
---|
[fa27fe5c] | 1275 | sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED | speed; |
---|
[12718134] | 1276 | /* Reset ON */ |
---|
[fa27fe5c] | 1277 | if (sc->greth_rst) |
---|
| 1278 | sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED | speed; |
---|
[12718134] | 1279 | /* Reset OFF and restore link settings previously detected if any */ |
---|
[fa27fe5c] | 1280 | sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed; |
---|
[998e34ad] | 1281 | SPIN_UNLOCK_IRQ(&sc->devlock, flags); |
---|
| 1282 | |
---|
[3bb4122] | 1283 | sc->next_tx_mbuf = NULL; |
---|
| 1284 | } |
---|
| 1285 | |
---|
| 1286 | |
---|
| 1287 | /* |
---|
| 1288 | * Show interface statistics |
---|
| 1289 | */ |
---|
| 1290 | static void |
---|
| 1291 | greth_stats (struct greth_softc *sc) |
---|
| 1292 | { |
---|
| 1293 | printf (" Rx Interrupts:%-8lu", sc->rxInterrupts); |
---|
| 1294 | printf (" Rx Packets:%-8lu", sc->rxPackets); |
---|
| 1295 | printf (" Length:%-8lu", sc->rxLengthError); |
---|
| 1296 | printf (" Non-octet:%-8lu\n", sc->rxNonOctet); |
---|
| 1297 | printf (" Bad CRC:%-8lu", sc->rxBadCRC); |
---|
| 1298 | printf (" Overrun:%-8lu", sc->rxOverrun); |
---|
| 1299 | printf (" Tx Interrupts:%-8lu", sc->txInterrupts); |
---|
| 1300 | printf (" Maximal Frags:%-8d", sc->max_fragsize); |
---|
| 1301 | printf (" GBIT MAC:%-8d", sc->gbit_mac); |
---|
| 1302 | } |
---|
| 1303 | |
---|
| 1304 | /* |
---|
| 1305 | * Driver ioctl handler |
---|
| 1306 | */ |
---|
| 1307 | static int |
---|
| 1308 | greth_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_t data) |
---|
| 1309 | { |
---|
| 1310 | struct greth_softc *sc = ifp->if_softc; |
---|
| 1311 | int error = 0; |
---|
[243ddb52] | 1312 | struct ifreq *ifr; |
---|
[3bb4122] | 1313 | |
---|
| 1314 | switch (command) |
---|
| 1315 | { |
---|
| 1316 | case SIOCGIFADDR: |
---|
| 1317 | case SIOCSIFADDR: |
---|
| 1318 | ether_ioctl (ifp, command, data); |
---|
| 1319 | break; |
---|
| 1320 | |
---|
| 1321 | case SIOCSIFFLAGS: |
---|
| 1322 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) |
---|
| 1323 | { |
---|
| 1324 | case IFF_RUNNING: |
---|
| 1325 | greth_stop (sc); |
---|
| 1326 | break; |
---|
| 1327 | |
---|
| 1328 | case IFF_UP: |
---|
| 1329 | greth_init (sc); |
---|
| 1330 | break; |
---|
| 1331 | |
---|
| 1332 | case IFF_UP | IFF_RUNNING: |
---|
| 1333 | greth_stop (sc); |
---|
| 1334 | greth_init (sc); |
---|
| 1335 | break; |
---|
| 1336 | default: |
---|
| 1337 | break; |
---|
| 1338 | } |
---|
| 1339 | break; |
---|
| 1340 | |
---|
| 1341 | case SIO_RTEMS_SHOW_STATS: |
---|
| 1342 | greth_stats (sc); |
---|
| 1343 | break; |
---|
| 1344 | |
---|
| 1345 | /* |
---|
[243ddb52] | 1346 | * Multicast commands: Enabling/disabling filtering of MAC addresses |
---|
[3bb4122] | 1347 | */ |
---|
[243ddb52] | 1348 | case SIOCADDMULTI: |
---|
| 1349 | case SIOCDELMULTI: |
---|
| 1350 | ifr = (struct ifreq *)data; |
---|
| 1351 | if (command == SIOCADDMULTI) { |
---|
| 1352 | error = ether_addmulti(ifr, &sc->arpcom); |
---|
| 1353 | } else { |
---|
| 1354 | error = ether_delmulti(ifr, &sc->arpcom); |
---|
| 1355 | } |
---|
| 1356 | if (error == ENETRESET) { |
---|
| 1357 | error = greth_mac_filter_set(sc); |
---|
| 1358 | } |
---|
| 1359 | break; |
---|
| 1360 | |
---|
[3bb4122] | 1361 | default: |
---|
| 1362 | error = EINVAL; |
---|
| 1363 | break; |
---|
| 1364 | } |
---|
| 1365 | |
---|
| 1366 | return error; |
---|
| 1367 | } |
---|
| 1368 | |
---|
| 1369 | /* |
---|
| 1370 | * Attach an GRETH driver to the system |
---|
| 1371 | */ |
---|
[aedc9849] | 1372 | static int |
---|
[3bb4122] | 1373 | greth_interface_driver_attach ( |
---|
| 1374 | struct rtems_bsdnet_ifconfig *config, |
---|
| 1375 | int attach |
---|
| 1376 | ) |
---|
| 1377 | { |
---|
| 1378 | struct greth_softc *sc; |
---|
| 1379 | struct ifnet *ifp; |
---|
| 1380 | int mtu; |
---|
| 1381 | int unitNumber; |
---|
| 1382 | char *unitName; |
---|
| 1383 | |
---|
| 1384 | /* parse driver name */ |
---|
| 1385 | if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0) |
---|
| 1386 | return 0; |
---|
| 1387 | |
---|
| 1388 | sc = config->drv_ctrl; |
---|
| 1389 | ifp = &sc->arpcom.ac_if; |
---|
| 1390 | #ifdef GRETH_DEBUG |
---|
| 1391 | printf("GRETH[%d]: %s, sc %p, dev %p on %s\n", unitNumber, config->ip_address, sc, sc->dev, sc->dev->parent->dev->name); |
---|
| 1392 | #endif |
---|
| 1393 | if (config->hardware_address) |
---|
| 1394 | { |
---|
| 1395 | memcpy (sc->arpcom.ac_enaddr, config->hardware_address, |
---|
| 1396 | ETHER_ADDR_LEN); |
---|
| 1397 | } |
---|
| 1398 | else |
---|
| 1399 | { |
---|
| 1400 | memset (sc->arpcom.ac_enaddr, 0x08, ETHER_ADDR_LEN); |
---|
| 1401 | } |
---|
| 1402 | |
---|
| 1403 | if (config->mtu) |
---|
| 1404 | mtu = config->mtu; |
---|
| 1405 | else |
---|
| 1406 | mtu = ETHERMTU; |
---|
| 1407 | |
---|
| 1408 | sc->acceptBroadcast = !config->ignore_broadcast; |
---|
| 1409 | |
---|
| 1410 | /* |
---|
| 1411 | * Set up network interface values |
---|
| 1412 | */ |
---|
| 1413 | ifp->if_softc = sc; |
---|
| 1414 | ifp->if_unit = unitNumber; |
---|
| 1415 | ifp->if_name = unitName; |
---|
| 1416 | ifp->if_mtu = mtu; |
---|
| 1417 | ifp->if_init = greth_init; |
---|
| 1418 | ifp->if_ioctl = greth_ioctl; |
---|
| 1419 | ifp->if_start = greth_start; |
---|
| 1420 | ifp->if_output = ether_output; |
---|
| 1421 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; |
---|
[243ddb52] | 1422 | if (sc->mc_available) |
---|
| 1423 | ifp->if_flags |= IFF_MULTICAST; |
---|
[3bb4122] | 1424 | if (ifp->if_snd.ifq_maxlen == 0) |
---|
| 1425 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
---|
| 1426 | |
---|
| 1427 | /* |
---|
| 1428 | * Attach the interface |
---|
| 1429 | */ |
---|
| 1430 | if_attach (ifp); |
---|
| 1431 | ether_ifattach (ifp); |
---|
| 1432 | |
---|
| 1433 | #ifdef GRETH_DEBUG |
---|
| 1434 | printf ("GRETH : driver has been attached\n"); |
---|
| 1435 | #endif |
---|
| 1436 | return 1; |
---|
| 1437 | } |
---|
| 1438 | |
---|
| 1439 | /******************* Driver manager interface ***********************/ |
---|
| 1440 | |
---|
| 1441 | /* Driver prototypes */ |
---|
| 1442 | int greth_register_io(rtems_device_major_number *m); |
---|
| 1443 | int greth_device_init(struct greth_softc *sc); |
---|
| 1444 | int network_interface_add(struct rtems_bsdnet_ifconfig *interface); |
---|
| 1445 | |
---|
| 1446 | #ifdef GRETH_INFO_AVAIL |
---|
| 1447 | static int greth_info( |
---|
| 1448 | struct drvmgr_dev *dev, |
---|
| 1449 | void (*print_line)(void *p, char *str), |
---|
| 1450 | void *p, int argc, char *argv[]); |
---|
| 1451 | #define GRETH_INFO_FUNC greth_info |
---|
| 1452 | #else |
---|
| 1453 | #define GRETH_INFO_FUNC NULL |
---|
| 1454 | #endif |
---|
| 1455 | |
---|
| 1456 | int greth_init2(struct drvmgr_dev *dev); |
---|
| 1457 | int greth_init3(struct drvmgr_dev *dev); |
---|
| 1458 | |
---|
| 1459 | struct drvmgr_drv_ops greth_ops = |
---|
| 1460 | { |
---|
| 1461 | .init = |
---|
| 1462 | { |
---|
| 1463 | NULL, |
---|
| 1464 | greth_init2, |
---|
| 1465 | greth_init3, |
---|
| 1466 | NULL |
---|
| 1467 | }, |
---|
| 1468 | .remove = NULL, |
---|
| 1469 | .info = GRETH_INFO_FUNC, |
---|
| 1470 | }; |
---|
| 1471 | |
---|
| 1472 | struct amba_dev_id greth_ids[] = |
---|
| 1473 | { |
---|
| 1474 | {VENDOR_GAISLER, GAISLER_ETHMAC}, |
---|
| 1475 | {0, 0} /* Mark end of table */ |
---|
| 1476 | }; |
---|
| 1477 | |
---|
| 1478 | struct amba_drv_info greth_drv_info = |
---|
| 1479 | { |
---|
| 1480 | { |
---|
| 1481 | DRVMGR_OBJ_DRV, /* Driver */ |
---|
| 1482 | NULL, /* Next driver */ |
---|
| 1483 | NULL, /* Device list */ |
---|
| 1484 | DRIVER_AMBAPP_GAISLER_GRETH_ID, /* Driver ID */ |
---|
| 1485 | "GRETH_DRV", /* Driver Name */ |
---|
| 1486 | DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */ |
---|
| 1487 | &greth_ops, |
---|
| 1488 | NULL, /* Funcs */ |
---|
| 1489 | 0, /* No devices yet */ |
---|
| 1490 | 0, |
---|
| 1491 | }, |
---|
| 1492 | &greth_ids[0] |
---|
| 1493 | }; |
---|
| 1494 | |
---|
| 1495 | void greth_register_drv (void) |
---|
| 1496 | { |
---|
| 1497 | DBG("Registering GRETH driver\n"); |
---|
| 1498 | drvmgr_drv_register(&greth_drv_info.general); |
---|
| 1499 | } |
---|
| 1500 | |
---|
| 1501 | int greth_init2(struct drvmgr_dev *dev) |
---|
| 1502 | { |
---|
| 1503 | struct greth_softc *priv; |
---|
| 1504 | |
---|
| 1505 | DBG("GRETH[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name); |
---|
[11f3b9a] | 1506 | priv = dev->priv = grlib_calloc(1, sizeof(*priv)); |
---|
[3bb4122] | 1507 | if ( !priv ) |
---|
| 1508 | return DRVMGR_NOMEM; |
---|
| 1509 | priv->dev = dev; |
---|
| 1510 | |
---|
| 1511 | /* This core will not find other cores, so we wait for init3() */ |
---|
| 1512 | |
---|
| 1513 | return DRVMGR_OK; |
---|
| 1514 | } |
---|
| 1515 | |
---|
| 1516 | int greth_init3(struct drvmgr_dev *dev) |
---|
| 1517 | { |
---|
| 1518 | struct greth_softc *sc; |
---|
| 1519 | struct rtems_bsdnet_ifconfig *ifp; |
---|
| 1520 | rtems_status_code status; |
---|
| 1521 | |
---|
| 1522 | sc = dev->priv; |
---|
| 1523 | sprintf(sc->devName, "gr_eth%d", (dev->minor_drv+1)); |
---|
| 1524 | |
---|
| 1525 | /* Init GRETH device */ |
---|
| 1526 | if ( greth_device_init(sc) ) { |
---|
| 1527 | printk("GRETH: Failed to init device\n"); |
---|
| 1528 | return DRVMGR_FAIL; |
---|
| 1529 | } |
---|
| 1530 | |
---|
[998e34ad] | 1531 | /* Initialize Spin-lock for GRSPW Device. This is to protect |
---|
| 1532 | * CTRL and DMACTRL registers from ISR. |
---|
| 1533 | */ |
---|
| 1534 | SPIN_INIT(&sc->devlock, sc->devName); |
---|
| 1535 | |
---|
[3bb4122] | 1536 | /* Register GRETH device as an Network interface */ |
---|
[75e1009f] | 1537 | ifp = grlib_calloc(1, sizeof(*ifp)); |
---|
[3bb4122] | 1538 | |
---|
| 1539 | ifp->name = sc->devName; |
---|
| 1540 | ifp->drv_ctrl = sc; |
---|
| 1541 | ifp->attach = greth_interface_driver_attach; |
---|
| 1542 | |
---|
| 1543 | status = network_interface_add(ifp); |
---|
| 1544 | if (status != 0) { |
---|
| 1545 | return DRVMGR_FAIL; |
---|
| 1546 | } |
---|
| 1547 | |
---|
| 1548 | return DRVMGR_OK; |
---|
| 1549 | } |
---|
| 1550 | |
---|
| 1551 | int greth_device_init(struct greth_softc *sc) |
---|
| 1552 | { |
---|
| 1553 | struct amba_dev_info *ambadev; |
---|
| 1554 | struct ambapp_core *pnpinfo; |
---|
| 1555 | union drvmgr_key_value *value; |
---|
[12718134] | 1556 | unsigned int speed; |
---|
[3bb4122] | 1557 | |
---|
| 1558 | /* Get device information from AMBA PnP information */ |
---|
| 1559 | ambadev = (struct amba_dev_info *)sc->dev->businfo; |
---|
| 1560 | if ( ambadev == NULL ) { |
---|
| 1561 | return -1; |
---|
| 1562 | } |
---|
| 1563 | pnpinfo = &ambadev->info; |
---|
| 1564 | sc->regs = (greth_regs *)pnpinfo->apb_slv->start; |
---|
| 1565 | sc->minor = sc->dev->minor_drv; |
---|
[fa27fe5c] | 1566 | sc->greth_rst = 1; |
---|
[3bb4122] | 1567 | |
---|
[12718134] | 1568 | /* Remember EDCL enabled/disable state before reset */ |
---|
| 1569 | sc->edcl_dis = sc->regs->ctrl & GRETH_CTRL_ED; |
---|
| 1570 | |
---|
| 1571 | /* Default is to inherit EDCL Disable bit from HW. User can force En/Dis */ |
---|
| 1572 | value = drvmgr_dev_key_get(sc->dev, "edclDis", DRVMGR_KT_INT); |
---|
| 1573 | if ( value ) { |
---|
| 1574 | /* Force EDCL mode. Has an effect later when GRETH+PHY is initialized */ |
---|
[fa27fe5c] | 1575 | if (value->i > 0) { |
---|
[12718134] | 1576 | sc->edcl_dis = GRETH_CTRL_ED; |
---|
[fa27fe5c] | 1577 | } else { |
---|
| 1578 | /* Default to avoid soft-reset the GRETH when EDCL is forced */ |
---|
[12718134] | 1579 | sc->edcl_dis = 0; |
---|
[fa27fe5c] | 1580 | sc->greth_rst = 0; |
---|
| 1581 | } |
---|
| 1582 | } |
---|
| 1583 | |
---|
| 1584 | /* let user control soft-reset of GRETH (for debug) */ |
---|
| 1585 | value = drvmgr_dev_key_get(sc->dev, "soft-reset", DRVMGR_KT_INT); |
---|
| 1586 | if ( value) { |
---|
| 1587 | sc->greth_rst = value->i ? 1 : 0; |
---|
[12718134] | 1588 | } |
---|
| 1589 | |
---|
| 1590 | /* clear control register and reset NIC and keep current speed modes. |
---|
[3bb4122] | 1591 | * This should be done as quick as possible during startup, this is to |
---|
| 1592 | * stop DMA transfers after a reboot. |
---|
[fa27fe5c] | 1593 | * |
---|
| 1594 | * When EDCL is forced enabled reset is skipped, disabling RX/TX DMA is |
---|
| 1595 | * is enough during debug. |
---|
[3bb4122] | 1596 | */ |
---|
[12718134] | 1597 | speed = sc->regs->ctrl & (GRETH_CTRL_GB | GRETH_CTRL_SP | GRETH_CTRL_FULLD); |
---|
[fa27fe5c] | 1598 | sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED | speed; |
---|
| 1599 | if (sc->greth_rst) |
---|
| 1600 | sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED | speed; |
---|
[12718134] | 1601 | sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed; |
---|
[3bb4122] | 1602 | |
---|
| 1603 | /* Configure driver by overriding default config with the bus resources |
---|
| 1604 | * configured by the user |
---|
| 1605 | */ |
---|
| 1606 | sc->txbufs = 32; |
---|
| 1607 | sc->rxbufs = 32; |
---|
| 1608 | sc->phyaddr = -1; |
---|
| 1609 | |
---|
[4d3e70f4] | 1610 | value = drvmgr_dev_key_get(sc->dev, "txDescs", DRVMGR_KT_INT); |
---|
[3bb4122] | 1611 | if ( value && (value->i <= 128) ) |
---|
| 1612 | sc->txbufs = value->i; |
---|
| 1613 | |
---|
[4d3e70f4] | 1614 | value = drvmgr_dev_key_get(sc->dev, "rxDescs", DRVMGR_KT_INT); |
---|
[3bb4122] | 1615 | if ( value && (value->i <= 128) ) |
---|
| 1616 | sc->rxbufs = value->i; |
---|
| 1617 | |
---|
[4d3e70f4] | 1618 | value = drvmgr_dev_key_get(sc->dev, "phyAdr", DRVMGR_KT_INT); |
---|
[3bb4122] | 1619 | if ( value && (value->i < 32) ) |
---|
| 1620 | sc->phyaddr = value->i; |
---|
| 1621 | |
---|
[e6fbd26] | 1622 | value = drvmgr_dev_key_get(sc->dev, "advModes", DRVMGR_KT_INT); |
---|
| 1623 | if ( value ) |
---|
| 1624 | sc->advmodes = value->i; |
---|
| 1625 | |
---|
[243ddb52] | 1626 | /* Check if multicast support is available */ |
---|
| 1627 | sc->mc_available = sc->regs->ctrl & GRETH_CTRL_MC; |
---|
| 1628 | |
---|
[3bb4122] | 1629 | return 0; |
---|
| 1630 | } |
---|
| 1631 | |
---|
| 1632 | #ifdef GRETH_INFO_AVAIL |
---|
| 1633 | static int greth_info( |
---|
| 1634 | struct drvmgr_dev *dev, |
---|
| 1635 | void (*print_line)(void *p, char *str), |
---|
| 1636 | void *p, int argc, char *argv[]) |
---|
| 1637 | { |
---|
| 1638 | struct greth_softc *sc; |
---|
| 1639 | char buf[64]; |
---|
| 1640 | |
---|
| 1641 | if (dev->priv == NULL) |
---|
| 1642 | return -DRVMGR_EINVAL; |
---|
| 1643 | sc = dev->priv; |
---|
| 1644 | |
---|
| 1645 | sprintf(buf, "IFACE NAME: %s", sc->devName); |
---|
| 1646 | print_line(p, buf); |
---|
| 1647 | sprintf(buf, "GBIT MAC: %s", sc->gbit_mac ? "YES" : "NO"); |
---|
| 1648 | print_line(p, buf); |
---|
| 1649 | |
---|
| 1650 | return DRVMGR_OK; |
---|
| 1651 | } |
---|
| 1652 | #endif |
---|
| 1653 | |
---|
| 1654 | #endif |
---|