1 | /* |
---|
2 | * Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
---|
3 | * |
---|
4 | * embedded brains GmbH |
---|
5 | * Dornierstr. 4 |
---|
6 | * 82178 Puchheim |
---|
7 | * Germany |
---|
8 | * <rtems@embedded-brains.de> |
---|
9 | * |
---|
10 | * The license and distribution terms for this file may be |
---|
11 | * found in the file LICENSE in this distribution or at |
---|
12 | * http://www.rtems.org/license/LICENSE. |
---|
13 | */ |
---|
14 | |
---|
15 | #include <amba.h> |
---|
16 | #include <leon.h> |
---|
17 | |
---|
18 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
---|
19 | |
---|
20 | #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |
---|
21 | |
---|
22 | #define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING |
---|
23 | |
---|
24 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT 64 |
---|
25 | |
---|
26 | #define CPU_DATA_CACHE_ALIGNMENT 64 |
---|
27 | |
---|
28 | static inline volatile struct l2c_regs *get_l2c_regs(void) |
---|
29 | { |
---|
30 | volatile struct l2c_regs *l2c = NULL; |
---|
31 | struct ambapp_dev *adev; |
---|
32 | |
---|
33 | adev = (void *) ambapp_for_each( |
---|
34 | ambapp_plb(), |
---|
35 | OPTIONS_ALL | OPTIONS_AHB_SLVS, |
---|
36 | VENDOR_GAISLER, |
---|
37 | GAISLER_L2CACHE, |
---|
38 | ambapp_find_by_idx, |
---|
39 | NULL |
---|
40 | ); |
---|
41 | if (adev != NULL) { |
---|
42 | l2c = (volatile struct l2c_regs *) DEV_TO_AHB(adev)->start[1]; |
---|
43 | } |
---|
44 | |
---|
45 | return l2c; |
---|
46 | } |
---|
47 | |
---|
48 | static inline size_t get_l2_size(void) |
---|
49 | { |
---|
50 | size_t size = 0; |
---|
51 | volatile struct l2c_regs *l2c = get_l2c_regs(); |
---|
52 | |
---|
53 | if (l2c != NULL) { |
---|
54 | unsigned status = l2c->status; |
---|
55 | unsigned ways = (status & 0x3) + 1; |
---|
56 | unsigned set_size = ((status & 0x7ff) >> 2) * 1024; |
---|
57 | |
---|
58 | size = ways * set_size; |
---|
59 | } |
---|
60 | |
---|
61 | return size; |
---|
62 | } |
---|
63 | |
---|
64 | static inline size_t get_l1_size(uint32_t l1_cfg) |
---|
65 | { |
---|
66 | uint32_t ways = ((l1_cfg >> 24) & 0x7) + 1; |
---|
67 | uint32_t wsize = UINT32_C(1) << (((l1_cfg >> 20) & 0xf) + 10); |
---|
68 | |
---|
69 | return ways * wsize; |
---|
70 | } |
---|
71 | |
---|
72 | static inline size_t get_max_size(size_t a, size_t b) |
---|
73 | { |
---|
74 | return a < b ? b : a; |
---|
75 | } |
---|
76 | |
---|
77 | static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg) |
---|
78 | { |
---|
79 | size_t size; |
---|
80 | |
---|
81 | switch (level) { |
---|
82 | case 0: |
---|
83 | size = get_max_size(get_l1_size(l1_cfg), get_l2_size()); |
---|
84 | break; |
---|
85 | case 1: |
---|
86 | size = get_l1_size(l1_cfg); |
---|
87 | break; |
---|
88 | case 2: |
---|
89 | size = get_l2_size(); |
---|
90 | break; |
---|
91 | default: |
---|
92 | size = 0; |
---|
93 | break; |
---|
94 | } |
---|
95 | |
---|
96 | return size; |
---|
97 | } |
---|
98 | |
---|
99 | static inline size_t _CPU_cache_get_data_cache_size(uint32_t level) |
---|
100 | { |
---|
101 | return get_cache_size(level, leon3_get_data_cache_config_register()); |
---|
102 | } |
---|
103 | |
---|
104 | static inline void _CPU_cache_flush_data_range( |
---|
105 | const void *d_addr, |
---|
106 | size_t n_bytes |
---|
107 | ) |
---|
108 | { |
---|
109 | /* TODO */ |
---|
110 | } |
---|
111 | |
---|
112 | static inline void _CPU_cache_invalidate_data_range( |
---|
113 | const void *d_addr, |
---|
114 | size_t n_bytes |
---|
115 | ) |
---|
116 | { |
---|
117 | /* TODO */ |
---|
118 | } |
---|
119 | |
---|
120 | static inline void _CPU_cache_freeze_data(void) |
---|
121 | { |
---|
122 | /* TODO */ |
---|
123 | } |
---|
124 | |
---|
125 | static inline void _CPU_cache_unfreeze_data(void) |
---|
126 | { |
---|
127 | /* TODO */ |
---|
128 | } |
---|
129 | |
---|
130 | static inline void _CPU_cache_invalidate_entire_instruction(void) |
---|
131 | { |
---|
132 | uint32_t cache_reg = leon3_get_cache_control_register(); |
---|
133 | |
---|
134 | cache_reg |= LEON3_REG_CACHE_CTRL_FI; |
---|
135 | leon3_set_cache_control_register(cache_reg); |
---|
136 | } |
---|
137 | |
---|
138 | static inline void _CPU_cache_invalidate_instruction_range( |
---|
139 | const void *i_addr, |
---|
140 | size_t n_bytes |
---|
141 | ) |
---|
142 | { |
---|
143 | _CPU_cache_invalidate_entire_instruction(); |
---|
144 | } |
---|
145 | |
---|
146 | static inline void _CPU_cache_freeze_instruction(void) |
---|
147 | { |
---|
148 | /* TODO */ |
---|
149 | } |
---|
150 | |
---|
151 | static inline void _CPU_cache_unfreeze_instruction(void) |
---|
152 | { |
---|
153 | /* TODO */ |
---|
154 | } |
---|
155 | |
---|
156 | static inline void _CPU_cache_flush_entire_data(void) |
---|
157 | { |
---|
158 | /* TODO */ |
---|
159 | } |
---|
160 | |
---|
161 | static inline void _CPU_cache_invalidate_entire_data(void) |
---|
162 | { |
---|
163 | /* TODO */ |
---|
164 | } |
---|
165 | |
---|
166 | static inline void _CPU_cache_enable_data(void) |
---|
167 | { |
---|
168 | /* TODO */ |
---|
169 | } |
---|
170 | |
---|
171 | static inline void _CPU_cache_disable_data(void) |
---|
172 | { |
---|
173 | /* TODO */ |
---|
174 | } |
---|
175 | |
---|
176 | static inline size_t _CPU_cache_get_instruction_cache_size( uint32_t level ) |
---|
177 | { |
---|
178 | return get_cache_size(level, leon3_get_inst_cache_config_register()); |
---|
179 | } |
---|
180 | |
---|
181 | static inline void _CPU_cache_enable_instruction(void) |
---|
182 | { |
---|
183 | /* TODO */ |
---|
184 | } |
---|
185 | |
---|
186 | static inline void _CPU_cache_disable_instruction(void) |
---|
187 | { |
---|
188 | /* TODO */ |
---|
189 | } |
---|
190 | |
---|
191 | #include "../../../shared/cache/cacheimpl.h" |
---|