1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * @ingroup sparc_leon3 |
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6 | * @brief Implementations for interrupt mechanisms for Time Test 27 |
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7 | */ |
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8 | |
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9 | /* |
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10 | * COPYRIGHT (c) 2006. |
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11 | * Aeroflex Gaisler AB. |
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12 | * |
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13 | * Redistribution and use in source and binary forms, with or without |
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14 | * modification, are permitted provided that the following conditions |
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15 | * are met: |
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16 | * 1. Redistributions of source code must retain the above copyright |
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17 | * notice, this list of conditions and the following disclaimer. |
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18 | * 2. Redistributions in binary form must reproduce the above copyright |
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19 | * notice, this list of conditions and the following disclaimer in the |
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20 | * documentation and/or other materials provided with the distribution. |
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21 | * |
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22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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26 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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32 | * POSSIBILITY OF SUCH DAMAGE. |
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33 | */ |
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34 | |
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35 | #ifndef _RTEMS_TMTEST27 |
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36 | #error "This is an RTEMS internal file you must not include directly." |
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37 | #endif |
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38 | |
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39 | #ifndef __tm27_h |
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40 | #define __tm27_h |
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41 | |
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42 | #include <bsp.h> |
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43 | #include <bsp/irq.h> |
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44 | |
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45 | #if defined(RTEMS_SMP) |
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46 | #include <rtems/score/smpimpl.h> |
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47 | #endif |
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48 | |
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49 | /* |
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50 | * Define the interrupt mechanism for Time Test 27 |
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51 | * |
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52 | * NOTE: Since the interrupt code for the SPARC supports both synchronous |
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53 | * and asynchronous trap handlers, support for testing with both |
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54 | * is included. |
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55 | */ |
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56 | |
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57 | #define SIS_USE_SYNCHRONOUS_TRAP 0 |
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58 | |
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59 | /* |
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60 | * The synchronous trap is an arbitrarily chosen software trap. |
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61 | */ |
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62 | |
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63 | #if (SIS_USE_SYNCHRONOUS_TRAP == 1) |
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64 | |
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65 | #define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) |
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66 | |
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67 | #define MUST_WAIT_FOR_INTERRUPT 1 |
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68 | |
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69 | #define Install_tm27_vector( handler ) \ |
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70 | set_vector( (handler), TEST_VECTOR, 1 ); |
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71 | |
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72 | #define Cause_tm27_intr() \ |
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73 | __asm__ volatile( "ta 0x10; nop " ); |
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74 | |
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75 | #define Clear_tm27_intr() /* empty */ |
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76 | |
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77 | #define Lower_tm27_intr() /* empty */ |
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78 | |
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79 | /* |
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80 | * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. |
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81 | */ |
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82 | |
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83 | #else /* use a regular asynchronous trap */ |
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84 | |
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85 | extern uint32_t Interrupt_nest; |
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86 | |
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87 | #define TEST_INTERRUPT_SOURCE 5 |
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88 | #define TEST_INTERRUPT_SOURCE2 6 |
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89 | #define MUST_WAIT_FOR_INTERRUPT 1 |
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90 | |
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91 | static inline void Install_tm27_vector( |
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92 | void ( *handler )( rtems_vector_number ) |
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93 | ) |
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94 | { |
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95 | static rtems_interrupt_entry entry_low; |
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96 | static rtems_interrupt_entry entry_high; |
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97 | |
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98 | #if defined(RTEMS_SMP) |
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99 | bsp_interrupt_set_affinity( |
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100 | TEST_INTERRUPT_SOURCE, |
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101 | _SMP_Get_online_processors() |
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102 | ); |
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103 | bsp_interrupt_set_affinity( |
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104 | TEST_INTERRUPT_SOURCE2, |
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105 | _SMP_Get_online_processors() |
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106 | ); |
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107 | #endif |
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108 | |
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109 | rtems_interrupt_entry_initialize( |
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110 | &entry_low, |
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111 | (rtems_interrupt_handler) handler, |
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112 | NULL, |
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113 | "tm27 low" |
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114 | ); |
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115 | (void) rtems_interrupt_entry_install( |
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116 | TEST_INTERRUPT_SOURCE, |
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117 | RTEMS_INTERRUPT_SHARED, |
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118 | &entry_low |
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119 | ); |
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120 | rtems_interrupt_entry_initialize( |
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121 | &entry_high, |
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122 | (rtems_interrupt_handler) handler, |
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123 | NULL, |
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124 | "tm27 high" |
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125 | ); |
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126 | (void) rtems_interrupt_entry_install( |
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127 | TEST_INTERRUPT_SOURCE2, |
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128 | RTEMS_INTERRUPT_SHARED, |
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129 | &entry_high |
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130 | ); |
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131 | } |
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132 | |
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133 | static inline void Cause_tm27_intr( void ) |
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134 | { |
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135 | rtems_vector_number vector; |
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136 | |
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137 | vector = TEST_INTERRUPT_SOURCE + ( Interrupt_nest >> 1 ); |
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138 | #if defined(RTEMS_SMP) |
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139 | (void) rtems_interrupt_raise_on( vector, rtems_scheduler_get_processor() ); |
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140 | #else |
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141 | (void) rtems_interrupt_raise( vector ); |
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142 | #endif |
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143 | nop(); |
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144 | nop(); |
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145 | nop(); |
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146 | } |
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147 | |
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148 | static inline void Clear_tm27_intr( void ) |
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149 | { |
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150 | (void) rtems_interrupt_clear( TEST_INTERRUPT_SOURCE ); |
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151 | } |
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152 | |
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153 | #define Lower_tm27_intr() /* empty */ |
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154 | |
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155 | #endif |
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156 | |
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157 | #endif |
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