source: rtems/bsps/sparc/include/grlib.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 6.8 KB
Line 
1/**
2 * @file
3 * @ingroup amba
4 * @brief Common GRLIB AMBA Core Register definitions
5 */
6
7/*
8 *  COPYRIGHT (c) 2012
9 *  Aeroflex Gaisler
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#ifndef __GRLIB_H__
17#define __GRLIB_H__
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/* ESA MEMORY CONTROLLER */
24struct mctrl_regs {
25  unsigned int mcfg1;
26  unsigned int mcfg2;
27  unsigned int mcfg3;
28};
29
30/* APB UART */
31struct apbuart_regs {
32  volatile unsigned int data;
33  volatile unsigned int status;
34  volatile unsigned int ctrl;
35  volatile unsigned int scaler;
36};
37
38/* IRQMP and IRQAMP interrupt controller timestamps */
39struct irqmp_timestamp_regs {
40  volatile unsigned int counter;     /* 0x00 */
41  volatile unsigned int control;     /* 0x04 */
42  volatile unsigned int assertion;   /* 0x08 */
43  volatile unsigned int ack;         /* 0x0c */
44};
45
46/* IRQMP and IRQAMP interrupt controllers */
47struct irqmp_regs {
48  volatile unsigned int ilevel;      /* 0x00 */
49  volatile unsigned int ipend;       /* 0x04 */
50  volatile unsigned int iforce;      /* 0x08 */
51  volatile unsigned int iclear;      /* 0x0c */
52  volatile unsigned int mpstat;      /* 0x10 */
53  volatile unsigned int bcast;       /* 0x14 */
54  volatile unsigned int notused02;   /* 0x18 */
55  volatile unsigned int wdgctrl;     /* 0x1c */
56  volatile unsigned int ampctrl;     /* 0x20 */
57  volatile unsigned int icsel[2];    /* 0x24,0x28 */
58  volatile unsigned int notused13;   /* 0x2c */
59  volatile unsigned int notused20;   /* 0x30 */
60  volatile unsigned int notused21;   /* 0x34 */
61  volatile unsigned int notused22;   /* 0x38 */
62  volatile unsigned int notused23;   /* 0x3c */
63  volatile unsigned int mask[16];    /* 0x40 */
64  volatile unsigned int force[16];   /* 0x80 */
65  /* Extended IRQ registers */
66  volatile unsigned int intid[16];   /* 0xc0 */
67  volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */
68  volatile unsigned int resetaddr[4]; /* 0x200 */
69  volatile unsigned int resv0[12];    /* 0x210 - 0x23C */
70  volatile unsigned int pboot;        /* 0x240 */
71  volatile unsigned int resv1[47];    /* 0x244 - 0x2FC */
72  volatile unsigned int irqmap[8];    /* 0x300 - 0x31C */
73  volatile unsigned int resv2[824];   /* 0x320 - 0x1000 */
74};
75
76/* GPTIMER Timer instance */
77struct gptimer_timer_regs {
78  volatile unsigned int value;
79  volatile unsigned int reload;
80  volatile unsigned int ctrl;
81  volatile unsigned int notused;
82};
83
84#define GPTIMER_TIMER_CTRL_EN 0x00000001U
85#define GPTIMER_TIMER_CTRL_RS 0x00000002U
86#define GPTIMER_TIMER_CTRL_LD 0x00000004U
87#define GPTIMER_TIMER_CTRL_IE 0x00000008U
88#define GPTIMER_TIMER_CTRL_IP 0x00000010U
89#define GPTIMER_TIMER_CTRL_CH 0x00000020U
90#define GPTIMER_TIMER_CTRL_DH 0x00000040U
91
92/* GPTIMER common registers */
93struct gptimer_regs {
94  volatile unsigned int scaler_value;   /* common timer registers */
95  volatile unsigned int scaler_reload;
96  volatile unsigned int cfg;
97  volatile unsigned int notused;
98  struct gptimer_timer_regs timer[7];
99};
100
101/* GRGPIO GPIO */
102struct grgpio_regs {
103  volatile unsigned int data;        /* 0x00 I/O port data register */
104  volatile unsigned int output;      /* 0x04 I/O port output register */
105  volatile unsigned int dir;         /* 0x08 I/O port direction register */
106  volatile unsigned int imask;       /* 0x0C Interrupt mask register */
107  volatile unsigned int ipol;        /* 0x10 Interrupt polarity register */
108  volatile unsigned int iedge;       /* 0x14 Interrupt edge register */
109  volatile unsigned int bypass;      /* 0x18 Bypass register */
110  volatile unsigned int cap;         /* 0x1C Capability register */
111  volatile unsigned int irqmap[4];   /* 0x20 - 0x2C Interrupt map registers */
112  volatile unsigned int res_30;      /* 0x30 Reserved */
113  volatile unsigned int res_34;      /* 0x34 Reserved */
114  volatile unsigned int res_38;      /* 0x38 Reserved */
115  volatile unsigned int res_3C;      /* 0x3C Reserved */
116  volatile unsigned int iavail;      /* 0x40 Interrupt available register */
117  volatile unsigned int iflag;       /* 0x44 Interrupt flag register */
118  volatile unsigned int res_48;      /* 0x48 Reserved */
119  volatile unsigned int pulse;       /* 0x4C Pulse register */
120  volatile unsigned int res_50;      /* 0x50 Reserved */
121  volatile unsigned int output_or;   /* 0x54 I/O port output register, logical-OR */
122  volatile unsigned int dir_or;      /* 0x58 I/O port direction register, logical-OR */
123  volatile unsigned int imask_or;    /* 0x5C Interrupt mask register, logical-OR */
124  volatile unsigned int res_60;      /* 0x60 Reserved */
125  volatile unsigned int output_and;  /* 0x64 I/O port output register, logical-AND */
126  volatile unsigned int dir_and;     /* 0x68 I/O port direction register, logical-AND */
127  volatile unsigned int imask_and;   /* 0x6C Interrupt mask register, logical-AND */
128  volatile unsigned int res_70;      /* 0x70 Reserved */
129  volatile unsigned int output_xor;  /* 0x74 I/O port output register, logical-XOR */
130  volatile unsigned int dir_xor;     /* 0x78 I/O port direction register, logical-XOR */
131  volatile unsigned int imask_xor;   /* 0x7C Interrupt mask register, logical-XOR */
132};
133
134/* L2C - Level 2 Cache Controller registers */
135struct l2c_regs {
136  volatile unsigned int control;                /* 0x00 Control register */
137  volatile unsigned int status;                 /* 0x04 Status register */
138  volatile unsigned int flush_mem_addr;         /* 0x08 Flush (Memory address) */
139  volatile unsigned int flush_set_index;        /* 0x0c Flush (set, index) */
140  volatile unsigned int access_counter;         /* 0x10 */
141  volatile unsigned int hit_counter;            /* 0x14 */
142  volatile unsigned int bus_cycle_counter;      /* 0x18 */
143  volatile unsigned int bus_usage_counter;      /* 0x1c */
144  volatile unsigned int error_status_control;   /* 0x20 Error status/control */
145  volatile unsigned int error_addr;             /* 0x24 Error address */
146  volatile unsigned int tag_check_bit;          /* 0x28 TAG-check-bit */
147  volatile unsigned int data_check_bit;         /* 0x2c Data-check-bit */
148  volatile unsigned int scrub_control_status;   /* 0x30 Scrub Control/Status */
149  volatile unsigned int scrub_delay;            /* 0x34 Scrub Delay */
150  volatile unsigned int error_injection;        /* 0x38 Error injection */
151  volatile unsigned int access_control;         /* 0x3c Access control */
152  volatile unsigned int reserved_40[16];        /* 0x40 Reserved */
153  volatile unsigned int mtrr[32];               /* 0x80 - 0xFC MTRR registers */
154  volatile unsigned int reserved_100[131008];   /* 0x100 Reserved */
155  volatile unsigned int diag_iface_tag[16384];  /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */
156  volatile unsigned int reserved_90000[376832]; /* 0x90000 Reserved */
157  volatile unsigned int diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */
158};
159
160#ifdef __cplusplus
161}
162#endif
163
164#endif
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