1 | /** |
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2 | * @file |
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3 | * @ingroup amba |
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4 | * @brief Common GRLIB AMBA Core Register definitions |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 2012 |
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9 | * Aeroflex Gaisler |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #ifndef __GRLIB_H__ |
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17 | #define __GRLIB_H__ |
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18 | |
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19 | #ifdef __cplusplus |
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20 | extern "C" { |
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21 | #endif |
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22 | |
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23 | /* ESA MEMORY CONTROLLER */ |
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24 | struct mctrl_regs { |
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25 | unsigned int mcfg1; |
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26 | unsigned int mcfg2; |
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27 | unsigned int mcfg3; |
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28 | }; |
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29 | |
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30 | /* APB UART */ |
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31 | struct apbuart_regs { |
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32 | volatile unsigned int data; |
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33 | volatile unsigned int status; |
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34 | volatile unsigned int ctrl; |
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35 | volatile unsigned int scaler; |
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36 | }; |
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37 | |
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38 | /* IRQMP and IRQAMP interrupt controller timestamps */ |
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39 | struct irqmp_timestamp_regs { |
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40 | volatile unsigned int counter; /* 0x00 */ |
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41 | volatile unsigned int control; /* 0x04 */ |
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42 | volatile unsigned int assertion; /* 0x08 */ |
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43 | volatile unsigned int ack; /* 0x0c */ |
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44 | }; |
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45 | |
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46 | /* IRQMP and IRQAMP interrupt controllers */ |
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47 | struct irqmp_regs { |
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48 | volatile unsigned int ilevel; /* 0x00 */ |
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49 | volatile unsigned int ipend; /* 0x04 */ |
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50 | volatile unsigned int iforce; /* 0x08 */ |
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51 | volatile unsigned int iclear; /* 0x0c */ |
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52 | volatile unsigned int mpstat; /* 0x10 */ |
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53 | volatile unsigned int bcast; /* 0x14 */ |
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54 | volatile unsigned int notused02; /* 0x18 */ |
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55 | volatile unsigned int wdgctrl; /* 0x1c */ |
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56 | volatile unsigned int ampctrl; /* 0x20 */ |
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57 | volatile unsigned int icsel[2]; /* 0x24,0x28 */ |
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58 | volatile unsigned int notused13; /* 0x2c */ |
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59 | volatile unsigned int notused20; /* 0x30 */ |
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60 | volatile unsigned int notused21; /* 0x34 */ |
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61 | volatile unsigned int notused22; /* 0x38 */ |
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62 | volatile unsigned int notused23; /* 0x3c */ |
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63 | volatile unsigned int mask[16]; /* 0x40 */ |
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64 | volatile unsigned int force[16]; /* 0x80 */ |
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65 | /* Extended IRQ registers */ |
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66 | volatile unsigned int intid[16]; /* 0xc0 */ |
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67 | volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */ |
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68 | volatile unsigned int resetaddr[4]; /* 0x200 */ |
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69 | volatile unsigned int resv0[12]; /* 0x210 - 0x23C */ |
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70 | volatile unsigned int pboot; /* 0x240 */ |
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71 | volatile unsigned int resv1[47]; /* 0x244 - 0x2FC */ |
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72 | volatile unsigned int irqmap[8]; /* 0x300 - 0x31C */ |
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73 | volatile unsigned int resv2[824]; /* 0x320 - 0x1000 */ |
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74 | }; |
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75 | |
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76 | /* GPTIMER Timer instance */ |
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77 | struct gptimer_timer_regs { |
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78 | volatile unsigned int value; |
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79 | volatile unsigned int reload; |
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80 | volatile unsigned int ctrl; |
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81 | volatile unsigned int notused; |
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82 | }; |
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83 | |
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84 | #define GPTIMER_TIMER_CTRL_EN 0x00000001U |
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85 | #define GPTIMER_TIMER_CTRL_RS 0x00000002U |
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86 | #define GPTIMER_TIMER_CTRL_LD 0x00000004U |
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87 | #define GPTIMER_TIMER_CTRL_IE 0x00000008U |
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88 | #define GPTIMER_TIMER_CTRL_IP 0x00000010U |
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89 | #define GPTIMER_TIMER_CTRL_CH 0x00000020U |
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90 | #define GPTIMER_TIMER_CTRL_DH 0x00000040U |
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91 | |
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92 | /* GPTIMER common registers */ |
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93 | struct gptimer_regs { |
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94 | volatile unsigned int scaler_value; /* common timer registers */ |
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95 | volatile unsigned int scaler_reload; |
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96 | volatile unsigned int cfg; |
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97 | volatile unsigned int notused; |
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98 | struct gptimer_timer_regs timer[7]; |
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99 | }; |
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100 | |
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101 | /* GRGPIO GPIO */ |
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102 | struct grgpio_regs { |
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103 | volatile unsigned int data; /* 0x00 I/O port data register */ |
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104 | volatile unsigned int output; /* 0x04 I/O port output register */ |
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105 | volatile unsigned int dir; /* 0x08 I/O port direction register */ |
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106 | volatile unsigned int imask; /* 0x0C Interrupt mask register */ |
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107 | volatile unsigned int ipol; /* 0x10 Interrupt polarity register */ |
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108 | volatile unsigned int iedge; /* 0x14 Interrupt edge register */ |
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109 | volatile unsigned int bypass; /* 0x18 Bypass register */ |
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110 | volatile unsigned int cap; /* 0x1C Capability register */ |
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111 | volatile unsigned int irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */ |
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112 | volatile unsigned int res_30; /* 0x30 Reserved */ |
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113 | volatile unsigned int res_34; /* 0x34 Reserved */ |
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114 | volatile unsigned int res_38; /* 0x38 Reserved */ |
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115 | volatile unsigned int res_3C; /* 0x3C Reserved */ |
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116 | volatile unsigned int iavail; /* 0x40 Interrupt available register */ |
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117 | volatile unsigned int iflag; /* 0x44 Interrupt flag register */ |
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118 | volatile unsigned int res_48; /* 0x48 Reserved */ |
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119 | volatile unsigned int pulse; /* 0x4C Pulse register */ |
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120 | volatile unsigned int res_50; /* 0x50 Reserved */ |
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121 | volatile unsigned int output_or; /* 0x54 I/O port output register, logical-OR */ |
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122 | volatile unsigned int dir_or; /* 0x58 I/O port direction register, logical-OR */ |
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123 | volatile unsigned int imask_or; /* 0x5C Interrupt mask register, logical-OR */ |
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124 | volatile unsigned int res_60; /* 0x60 Reserved */ |
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125 | volatile unsigned int output_and; /* 0x64 I/O port output register, logical-AND */ |
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126 | volatile unsigned int dir_and; /* 0x68 I/O port direction register, logical-AND */ |
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127 | volatile unsigned int imask_and; /* 0x6C Interrupt mask register, logical-AND */ |
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128 | volatile unsigned int res_70; /* 0x70 Reserved */ |
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129 | volatile unsigned int output_xor; /* 0x74 I/O port output register, logical-XOR */ |
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130 | volatile unsigned int dir_xor; /* 0x78 I/O port direction register, logical-XOR */ |
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131 | volatile unsigned int imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ |
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132 | }; |
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133 | |
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134 | /* L2C - Level 2 Cache Controller registers */ |
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135 | struct l2c_regs { |
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136 | volatile unsigned int control; /* 0x00 Control register */ |
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137 | volatile unsigned int status; /* 0x04 Status register */ |
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138 | volatile unsigned int flush_mem_addr; /* 0x08 Flush (Memory address) */ |
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139 | volatile unsigned int flush_set_index; /* 0x0c Flush (set, index) */ |
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140 | volatile unsigned int access_counter; /* 0x10 */ |
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141 | volatile unsigned int hit_counter; /* 0x14 */ |
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142 | volatile unsigned int bus_cycle_counter; /* 0x18 */ |
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143 | volatile unsigned int bus_usage_counter; /* 0x1c */ |
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144 | volatile unsigned int error_status_control; /* 0x20 Error status/control */ |
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145 | volatile unsigned int error_addr; /* 0x24 Error address */ |
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146 | volatile unsigned int tag_check_bit; /* 0x28 TAG-check-bit */ |
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147 | volatile unsigned int data_check_bit; /* 0x2c Data-check-bit */ |
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148 | volatile unsigned int scrub_control_status; /* 0x30 Scrub Control/Status */ |
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149 | volatile unsigned int scrub_delay; /* 0x34 Scrub Delay */ |
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150 | volatile unsigned int error_injection; /* 0x38 Error injection */ |
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151 | volatile unsigned int access_control; /* 0x3c Access control */ |
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152 | volatile unsigned int reserved_40[16]; /* 0x40 Reserved */ |
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153 | volatile unsigned int mtrr[32]; /* 0x80 - 0xFC MTRR registers */ |
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154 | volatile unsigned int reserved_100[131008]; /* 0x100 Reserved */ |
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155 | volatile unsigned int diag_iface_tag[16384]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */ |
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156 | volatile unsigned int reserved_90000[376832]; /* 0x90000 Reserved */ |
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157 | volatile unsigned int diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */ |
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158 | }; |
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159 | |
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160 | #ifdef __cplusplus |
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161 | } |
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162 | #endif |
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163 | |
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164 | #endif |
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