source: rtems/bsps/sparc/include/bsp/grpci2.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*  GRLIB GRPCI2 PCI HOST driver.
2 *
3 *  COPYRIGHT (c) 2011
4 *  Cobham Gaisler AB.
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef __GRPCI2_H__
12#define __GRPCI2_H__
13
14#ifdef __cplusplus
15extern "C" {
16#endif
17
18extern void grpci2_register_drv(void);
19
20/* Driver Resources:
21 *
22 * PCI Interrupts
23 * ==============
24 * The interrupt settings are normally autodetected from Plyg&Play, however
25 * if IRQs are routed using custom GPIO pins in order to reduce the PIN count
26 * reserved for PCI, the options below can be used to tell GRPCI2 driver which
27 * System IRQ a PCI interrupt is connected to.
28 * Name="INTA#", Type=INT, System Interrupt number that PCI INTA is connected to
29 * Name="INTB#", Type=INT, System Interrupt number that PCI INTB is connected to
30 * Name="INTC#", Type=INT, System Interrupt number that PCI INTC is connected to
31 * Name="INTD#", Type=INT, System Interrupt number that PCI INTD is connected to
32 *
33 * Name="IRQmask", Type=INT,
34 *
35 * PCI Bytetwisting (endianess)
36 * ============================
37 * Name="byteTwisting", Type=INT, Enable/Disable Bytetwisting by hardware
38 *
39 * PCI Latency timer
40 * ============================
41 * Name="latencyTimer", Type=INT, Set the latency timer
42 *
43 * PCI Host's Target BARs setup
44 * ============================
45 * The Host's BARs are not configured by the configuration routines, by default
46 * the BARs are configured disabled (BAR=0) except for BAR0 which is mapped to
47 * the Main Memory for the Host.
48 * Name="tgtBarCfg", Type=PTR (*grpci2_pcibar_cfg), Target PCI BARs of Host
49 */
50
51/* When the Host acts as a target on the PCI bus, the PCI BARs of the host's
52 * configuration space determine at which PCI address the Host will be accessed
53 * at and when accessing a BAR which AMBA address it will be translated to.
54 */
55struct grpci2_pcibar_cfg {
56        unsigned int pciadr;    /* PCI address of BAR (BAR content) */
57        unsigned int ahbadr;    /* 'pciadr' translated to this AHB Address */
58        unsigned int barsize;   /* PCI BAR Size, must be a power of 2 */
59};
60
61#ifdef __cplusplus
62}
63#endif
64
65#endif
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