source: rtems/bsps/sparc/include/bsp/greth.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 * Cobham Gaisler ethernet MAC driver
3 * adapted from Opencores driver by Marko Isomaki
4 *
5 * The license and distribution terms for this file may be
6 * found in found in the file LICENSE in this distribution or at
7 * http://www.rtems.org/license/LICENSE.
8 */
9
10#ifndef __GRETH_H__
11#define __GRETH_H__
12
13#ifdef __cplusplus
14extern "C" {
15#endif
16
17/* Ethernet configuration registers */
18
19typedef struct _greth_regs {
20   volatile uint32_t ctrl;         /* Ctrl Register */
21   volatile uint32_t status;       /* Status Register */
22   volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */
23   volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */
24   volatile uint32_t mdio_ctrl;    /* MDIO control and status */
25   volatile uint32_t txdesc;       /* Transmit descriptor pointer */
26   volatile uint32_t rxdesc;       /* Receive descriptor pointer */
27} greth_regs;
28
29#define GRETH_TOTAL_BD           128
30#define GRETH_MAXBUF_LEN         1520
31                               
32/* Tx BD */                     
33#define GRETH_TXD_ENABLE      0x0800 /* Tx BD Enable */
34#define GRETH_TXD_WRAP        0x1000 /* Tx BD Wrap (last BD) */
35#define GRETH_TXD_IRQ         0x2000 /* Tx BD IRQ Enable */
36#define GRETH_TXD_MORE        0x20000 /* Tx BD More (more descs for packet) */
37#define GRETH_TXD_IPCS        0x40000 /* Tx BD insert ip chksum */
38#define GRETH_TXD_TCPCS       0x80000 /* Tx BD insert tcp chksum */
39#define GRETH_TXD_UDPCS       0x100000 /* Tx BD insert udp chksum */
40
41#define GRETH_TXD_UNDERRUN    0x4000 /* Tx BD Underrun Status */
42#define GRETH_TXD_RETLIM      0x8000 /* Tx BD Retransmission Limit Status */
43#define GRETH_TXD_LATECOL     0x10000 /* Tx BD Late Collision */
44
45#define GRETH_TXD_STATS       (GRETH_TXD_UNDERRUN            | \
46                               GRETH_TXD_RETLIM              | \
47                               GRETH_TXD_LATECOL)
48
49#define GRETH_TXD_CS          (GRETH_TXD_IPCS            | \
50                               GRETH_TXD_TCPCS           | \
51                               GRETH_TXD_UDPCS)
52                               
53/* Rx BD */                     
54#define GRETH_RXD_ENABLE      0x0800 /* Rx BD Enable */
55#define GRETH_RXD_WRAP        0x1000 /* Rx BD Wrap (last BD) */
56#define GRETH_RXD_IRQ         0x2000 /* Rx BD IRQ Enable */
57
58#define GRETH_RXD_DRIBBLE     0x4000 /* Rx BD Dribble Nibble Status */                               
59#define GRETH_RXD_TOOLONG     0x8000 /* Rx BD Too Long Status */
60#define GRETH_RXD_CRCERR      0x10000 /* Rx BD CRC Error Status */
61#define GRETH_RXD_OVERRUN     0x20000 /* Rx BD Overrun Status */
62#define GRETH_RXD_LENERR      0x40000 /* Rx BD Length Error */
63#define GRETH_RXD_ID          0x40000 /* Rx BD IP Detected */
64#define GRETH_RXD_IR          0x40000 /* Rx BD IP Chksum Error */
65#define GRETH_RXD_UD          0x40000 /* Rx BD UDP Detected*/
66#define GRETH_RXD_UR          0x40000 /* Rx BD UDP Chksum Error */
67#define GRETH_RXD_TD          0x40000 /* Rx BD TCP Detected */
68#define GRETH_RXD_TR          0x40000 /* Rx BD TCP Chksum Error */
69
70
71#define GRETH_RXD_STATS       (GRETH_RXD_OVERRUN             | \
72                               GRETH_RXD_DRIBBLE             | \
73                               GRETH_RXD_TOOLONG             | \
74                               GRETH_RXD_CRCERR)
75
76/* CTRL Register */
77#define GRETH_CTRL_TXEN         0x00000001 /* Transmit Enable */
78#define GRETH_CTRL_RXEN         0x00000002 /* Receive Enable  */
79#define GRETH_CTRL_TXIRQ        0x00000004 /* Transmit Enable */
80#define GRETH_CTRL_RXIRQ        0x00000008 /* Receive Enable  */
81#define GRETH_CTRL_FULLD        0x00000010 /* Full Duplex */
82#define GRETH_CTRL_PRO          0x00000020 /* Promiscuous (receive all) */
83#define GRETH_CTRL_RST          0x00000040 /* Reset MAC */
84#define GRETH_CTRL_SP           0x00000080 /* 100MBit speed mode */
85#define GRETH_CTRL_GB           0x00000100 /* 1GBit speed mode */
86#define GRETH_CTRL_DD           0x00001000 /* Disable EDCL Duplex Detection */
87#define GRETH_CTRL_ED           0x00004000 /* EDCL Disable */
88
89/* Status Register */
90#define GRETH_STATUS_RXERR      0x00000001 /* Receive Error */
91#define GRETH_STATUS_TXERR      0x00000002 /* Transmit Error IRQ */
92#define GRETH_STATUS_RXIRQ      0x00000004 /* Receive Frame IRQ */
93#define GRETH_STATUS_TXIRQ      0x00000008 /* Transmit Error IRQ */
94#define GRETH_STATUS_RXAHBERR   0x00000010 /* Receiver AHB Error */
95#define GRETH_STATUS_TXAHBERR   0x00000020 /* Transmitter AHB Error */
96
97/* MDIO Control  */
98#define GRETH_MDIO_WRITE        0x00000001 /* MDIO Write */
99#define GRETH_MDIO_READ         0x00000002 /* MDIO Read */
100#define GRETH_MDIO_LINKFAIL     0x00000004 /* MDIO Link failed */
101#define GRETH_MDIO_BUSY         0x00000008 /* MDIO Link Busy */
102#define GRETH_MDIO_REGADR       0x000007C0 /* Register Address */
103#define GRETH_MDIO_PHYADR       0x0000F800 /* PHY address */
104#define GRETH_MDIO_DATA         0xFFFF0000 /* MDIO DATA */
105
106
107/* MII registers */
108#define GRETH_MII_EXTADV_1000FD 0x00000200
109#define GRETH_MII_EXTADV_1000HD 0x00000100
110#define GRETH_MII_EXTPRT_1000FD 0x00000800
111#define GRETH_MII_EXTPRT_1000HD 0x00000400
112
113#define GRETH_MII_100T4         0x00000200
114#define GRETH_MII_100TXFD       0x00000100
115#define GRETH_MII_100TXHD       0x00000080
116#define GRETH_MII_10FD          0x00000040
117#define GRETH_MII_10HD          0x00000020
118
119
120/* Attach routine */
121
122void greth_register_drv(void);
123
124/* PHY data */
125struct phy_device_info
126{
127   int vendor;
128   int device;
129   int rev;
130   
131   int adv;
132   int part;
133
134   int extadv;
135   int extpart;
136};
137
138/* Limit speed modes advertised during auto-negotiation */
139#define GRETH_ADV_10_HD    0x0001
140#define GRETH_ADV_10_FD    0x0002
141#define GRETH_ADV_100_HD   0x0004
142#define GRETH_ADV_100_FD   0x0008
143#define GRETH_ADV_1000_HD  0x0010
144#define GRETH_ADV_1000_FD  0x0020
145#define GRETH_ADV_ALL      0x003f
146/*
147#ifdef CPU_U32_FIX
148void ipalign(struct mbuf *m);
149#endif
150
151*/
152#ifdef __cplusplus
153}
154#endif
155
156#endif
157
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