[3bb4122] | 1 | /* |
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| 2 | * Cobham Gaisler ethernet MAC driver |
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| 3 | * adapted from Opencores driver by Marko Isomaki |
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| 4 | * |
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| 5 | * The license and distribution terms for this file may be |
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| 6 | * found in found in the file LICENSE in this distribution or at |
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[4a7d1026] | 7 | * http://www.rtems.org/license/LICENSE. |
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[3bb4122] | 8 | */ |
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| 9 | |
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| 10 | #ifndef __GRETH_H__ |
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| 11 | #define __GRETH_H__ |
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| 12 | |
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| 13 | #ifdef __cplusplus |
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| 14 | extern "C" { |
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| 15 | #endif |
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| 16 | |
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| 17 | /* Ethernet configuration registers */ |
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| 18 | |
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| 19 | typedef struct _greth_regs { |
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| 20 | volatile uint32_t ctrl; /* Ctrl Register */ |
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| 21 | volatile uint32_t status; /* Status Register */ |
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| 22 | volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */ |
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| 23 | volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */ |
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| 24 | volatile uint32_t mdio_ctrl; /* MDIO control and status */ |
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| 25 | volatile uint32_t txdesc; /* Transmit descriptor pointer */ |
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| 26 | volatile uint32_t rxdesc; /* Receive descriptor pointer */ |
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[243ddb52] | 27 | volatile uint32_t edcl; /* EDCL IP register */ |
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| 28 | volatile uint32_t ht_msb; /* Multicast MSB hash */ |
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| 29 | volatile uint32_t ht_lsb; /* Multicast LSB hash */ |
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[3bb4122] | 30 | } greth_regs; |
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| 31 | |
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| 32 | #define GRETH_TOTAL_BD 128 |
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| 33 | #define GRETH_MAXBUF_LEN 1520 |
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| 34 | |
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| 35 | /* Tx BD */ |
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| 36 | #define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */ |
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| 37 | #define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */ |
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| 38 | #define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */ |
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| 39 | #define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */ |
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| 40 | #define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */ |
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| 41 | #define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */ |
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| 42 | #define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */ |
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| 43 | |
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| 44 | #define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */ |
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| 45 | #define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */ |
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| 46 | #define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */ |
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| 47 | |
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| 48 | #define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \ |
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| 49 | GRETH_TXD_RETLIM | \ |
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| 50 | GRETH_TXD_LATECOL) |
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| 51 | |
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| 52 | #define GRETH_TXD_CS (GRETH_TXD_IPCS | \ |
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| 53 | GRETH_TXD_TCPCS | \ |
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| 54 | GRETH_TXD_UDPCS) |
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| 55 | |
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| 56 | /* Rx BD */ |
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| 57 | #define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */ |
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| 58 | #define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */ |
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| 59 | #define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */ |
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| 60 | |
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| 61 | #define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */ |
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| 62 | #define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */ |
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| 63 | #define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */ |
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| 64 | #define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */ |
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| 65 | #define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */ |
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| 66 | #define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */ |
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| 67 | #define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */ |
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| 68 | #define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/ |
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| 69 | #define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */ |
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| 70 | #define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */ |
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| 71 | #define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */ |
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| 72 | |
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| 73 | |
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| 74 | #define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \ |
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| 75 | GRETH_RXD_DRIBBLE | \ |
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| 76 | GRETH_RXD_TOOLONG | \ |
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| 77 | GRETH_RXD_CRCERR) |
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| 78 | |
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| 79 | /* CTRL Register */ |
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| 80 | #define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */ |
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| 81 | #define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */ |
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| 82 | #define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */ |
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| 83 | #define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */ |
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| 84 | #define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */ |
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| 85 | #define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */ |
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| 86 | #define GRETH_CTRL_RST 0x00000040 /* Reset MAC */ |
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[e6fbd26] | 87 | #define GRETH_CTRL_SP 0x00000080 /* 100MBit speed mode */ |
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| 88 | #define GRETH_CTRL_GB 0x00000100 /* 1GBit speed mode */ |
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[243ddb52] | 89 | #define GRETH_CTRL_MCE 0x00000800 /* Multicast Enable */ |
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[107c5aea] | 90 | #define GRETH_CTRL_DD 0x00001000 /* Disable EDCL Duplex Detection */ |
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[12718134] | 91 | #define GRETH_CTRL_ED 0x00004000 /* EDCL Disable */ |
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[243ddb52] | 92 | #define GRETH_CTRL_MC 0x02000000 /* Multicast available */ |
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| 93 | #define GRETH_CTRL_ME 0x04000000 /* MDIO interrupts enabled */ |
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| 94 | #define GRETH_CTRL_GA 0x08000000 /* Gigabit MAC available */ |
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[3bb4122] | 95 | |
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| 96 | /* Status Register */ |
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| 97 | #define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */ |
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| 98 | #define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */ |
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| 99 | #define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */ |
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| 100 | #define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */ |
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| 101 | #define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */ |
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| 102 | #define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */ |
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| 103 | |
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| 104 | /* MDIO Control */ |
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| 105 | #define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */ |
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| 106 | #define GRETH_MDIO_READ 0x00000002 /* MDIO Read */ |
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| 107 | #define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */ |
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| 108 | #define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */ |
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| 109 | #define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */ |
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| 110 | #define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */ |
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| 111 | #define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */ |
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| 112 | |
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| 113 | |
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| 114 | /* MII registers */ |
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| 115 | #define GRETH_MII_EXTADV_1000FD 0x00000200 |
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| 116 | #define GRETH_MII_EXTADV_1000HD 0x00000100 |
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| 117 | #define GRETH_MII_EXTPRT_1000FD 0x00000800 |
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| 118 | #define GRETH_MII_EXTPRT_1000HD 0x00000400 |
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| 119 | |
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| 120 | #define GRETH_MII_100T4 0x00000200 |
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| 121 | #define GRETH_MII_100TXFD 0x00000100 |
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| 122 | #define GRETH_MII_100TXHD 0x00000080 |
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| 123 | #define GRETH_MII_10FD 0x00000040 |
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| 124 | #define GRETH_MII_10HD 0x00000020 |
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| 125 | |
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| 126 | |
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| 127 | /* Attach routine */ |
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| 128 | |
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| 129 | void greth_register_drv(void); |
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| 130 | |
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| 131 | /* PHY data */ |
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| 132 | struct phy_device_info |
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| 133 | { |
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| 134 | int vendor; |
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| 135 | int device; |
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| 136 | int rev; |
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| 137 | |
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| 138 | int adv; |
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| 139 | int part; |
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| 140 | |
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| 141 | int extadv; |
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| 142 | int extpart; |
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| 143 | }; |
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| 144 | |
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[e6fbd26] | 145 | /* Limit speed modes advertised during auto-negotiation */ |
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| 146 | #define GRETH_ADV_10_HD 0x0001 |
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| 147 | #define GRETH_ADV_10_FD 0x0002 |
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| 148 | #define GRETH_ADV_100_HD 0x0004 |
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| 149 | #define GRETH_ADV_100_FD 0x0008 |
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| 150 | #define GRETH_ADV_1000_HD 0x0010 |
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| 151 | #define GRETH_ADV_1000_FD 0x0020 |
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| 152 | #define GRETH_ADV_ALL 0x003f |
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[3bb4122] | 153 | /* |
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| 154 | #ifdef CPU_U32_FIX |
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| 155 | void ipalign(struct mbuf *m); |
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| 156 | #endif |
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| 157 | |
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| 158 | */ |
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| 159 | #ifdef __cplusplus |
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| 160 | } |
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| 161 | #endif |
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| 162 | |
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| 163 | #endif |
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| 164 | |
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