1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup sparc_erc32 |
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5 | * |
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6 | * @brief THARSYS VME SPARC RT board SONIC Configuration Information |
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7 | * |
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8 | * References: |
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9 | * |
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10 | * 1) SVME/DMV-171 Single Board Computer Documentation Package, #805905, |
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11 | * DY 4 Systems Inc., Kanata, Ontario, September, 1996. |
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12 | */ |
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13 | |
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14 | /* |
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15 | * COPYRIGHT (c) 2000. |
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16 | * European Space Agency. |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <machine/rtems-bsd-kernel-space.h> |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <libchip/sonic.h> |
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27 | #if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) |
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28 | #include <stdio.h> |
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29 | #endif |
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30 | |
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31 | static void erc32_sonic_write_register( |
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32 | void *base, |
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33 | uint32_t regno, |
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34 | uint32_t value |
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35 | ) |
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36 | { |
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37 | volatile uint32_t *p = base; |
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38 | |
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39 | #if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) |
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40 | printf( "%p Write 0x%04x to %s (0x%02x)\n", |
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41 | &p[regno], value, SONIC_Reg_name[regno], regno ); |
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42 | fflush( stdout ); |
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43 | #endif |
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44 | p[regno] = 0x0ffff & value; |
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45 | } |
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46 | |
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47 | static uint32_t erc32_sonic_read_register( |
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48 | void *base, |
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49 | uint32_t regno |
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50 | ) |
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51 | { |
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52 | volatile uint32_t *p = base; |
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53 | uint32_t value; |
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54 | |
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55 | value = p[regno]; |
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56 | #if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) |
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57 | printf( "%p Read 0x%04x from %s (0x%02x)\n", |
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58 | &p[regno], value, SONIC_Reg_name[regno], regno ); |
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59 | fflush( stdout ); |
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60 | #endif |
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61 | return 0x0ffff & value; |
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62 | } |
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63 | |
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64 | /* |
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65 | * Default sizes of transmit and receive descriptor areas |
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66 | */ |
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67 | #define RDA_COUNT 20 /* 20 */ |
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68 | #define TDA_COUNT 20 /* 10 */ |
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69 | |
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70 | /* |
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71 | * Default device configuration register values |
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72 | * Conservative, generic values. |
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73 | * DCR: |
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74 | * No extended bus mode |
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75 | * Unlatched bus retry |
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76 | * Programmable outputs unused |
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77 | * Asynchronous bus mode |
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78 | * User definable pins unused |
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79 | * No wait states (access time controlled by DTACK*) |
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80 | * 32-bit DMA |
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81 | * Empty/Fill DMA mode |
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82 | * Maximum Transmit/Receive FIFO |
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83 | * DC2: |
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84 | * Extended programmable outputs unused |
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85 | * Normal HOLD request |
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86 | * Packet compress output unused |
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87 | * No reject on CAM match |
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88 | */ |
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89 | #define SONIC_DCR ( DCR_DW32 | DCR_RFT24 | DCR_TFT28) |
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90 | #define SONIC_DC2 (0) |
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91 | |
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92 | /* |
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93 | * Default location of device registers |
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94 | */ |
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95 | #define SONIC_BASE_ADDRESS 0x10000100 |
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96 | |
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97 | /* |
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98 | * Default interrupt vector |
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99 | */ |
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100 | #define SONIC_VECTOR 0x1E |
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101 | |
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102 | sonic_configuration_t erc32_sonic_configuration = { |
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103 | (void *)SONIC_BASE_ADDRESS, /* base address */ |
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104 | SONIC_VECTOR, /* vector number */ |
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105 | SONIC_DCR, /* DCR register value */ |
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106 | SONIC_DC2, /* DC2 register value */ |
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107 | TDA_COUNT, /* number of transmit descriptors */ |
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108 | RDA_COUNT, /* number of receive descriptors */ |
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109 | erc32_sonic_write_register, |
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110 | erc32_sonic_read_register |
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111 | }; |
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112 | |
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113 | int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config) |
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114 | { |
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115 | |
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116 | ERC32_MEC.IO_Configuration |= |
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117 | (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8)); |
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118 | ERC32_MEC.Control &= ~0x60001; /* Disable DMA time-out, parity & power-down */ |
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119 | ERC32_MEC.Control |= 0x10000; /* Enable DMA */ |
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120 | ERC32_MEC.Interrupt_Mask &= ~(1 << (SONIC_VECTOR - 0x10)); |
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121 | return(rtems_sonic_driver_attach( config, &erc32_sonic_configuration )); |
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122 | |
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123 | } |
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