source: rtems/bsps/sparc/erc32/README @ c05d7a9d

Last change on this file since c05d7a9d was eb36d11, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 25, 2018 at 1:06:08 PM

bsps: Move documentation, etc. files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.3 KB
Line 
1#
2#  Description of SIS as related to this BSP
3#
4
5BSP NAME:           sis
6BOARD:              any based on the European Space Agency's ERC32
7BUS:                N/A
8CPU FAMILY:         sparc
9CPU:                ERC32 (SPARC V7 + on-CPU peripherals)
10                    based on Cypress 601/602
11COPROCESSORS:       on-chip 602 compatible FPU
12MODE:               32 bit mode
13
14DEBUG MONITOR:      none
15
16PERIPHERALS
17===========
18TIMERS:
19  NAME:             General Purpose Timer 
20  RESOLUTION:         50 nanoseconds - 12.8 microseconds
21  NAME:             Real Time Clock Timer 
22  RESOLUTION:         50 nanoseconds - 3.2768 milliseconds
23  NAME:             Watchdog Timer 
24  RESOLUTION:         XXX
25SERIAL PORTS:       2 using on-chip UART
26REAL-TIME CLOCK:    none
27DMA:                on-chip
28VIDEO:              none
29SCSI:               none
30NETWORKING:         none
31
32DRIVER INFORMATION
33==================
34CLOCK DRIVER:       ERC32 internal Real Time Clock Timer
35IOSUPP DRIVER:      N/A
36SHMSUPP:            N/A
37TIMER DRIVER:       ERC32 internal General Purpose Timer
38CONSOLE DRIVER:     ERC32 internal UART
39
40STDIO
41=====
42PORT:               Channel A
43ELECTRICAL:         na since using simulator
44BAUD:               na
45BITS PER CHARACTER: na
46PARITY:             na
47STOP BITS:          na
48
49Notes
50=====
51
52ERC32 BSP only supports single processor operations.
53
54A nice feature of this BSP is that the RAM and PROM size are set in the
55linkcmds file and the startup code programs the Memory Configuration
56Register based on those sizes.
57
58The Watchdog Timer is disabled.
59
60This code was developed and tested entirely using the SPARC Instruction
61Simulator (SIS) for the ERC32.  All tests were known to run correctly
62against sis v1.7.
63
64
65Memory Map
66==========
67
680x00000000 - 0x00000000 + _PROM_SIZE      code and initialized data
690x01f80000                                on chip peripherals
700x00000000 - 0x02000000 + _RAM_SIZE       destination for initialized data
71                                          BSS (i.e. unitialized data)
72                                          C Heap (i.e. malloc area)
73                                          RTEMS Workspace
74
75The C heap is assigned all memory between the end of the BSS and the
76RTEMS Workspace.  The size of the RTEMS Workspace is based on that
77specified in the application's configuration table.
78 
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