[2b947a4] | 1 | /* |
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| 2 | * Copyright (c) 1995, David Greenman |
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| 3 | * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> |
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| 4 | * All rights reserved. |
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| 5 | * |
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| 6 | * Redistribution and use in source and binary forms, with or without |
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| 7 | * modification, are permitted provided that the following conditions |
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| 8 | * are met: |
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| 9 | * 1. Redistributions of source code must retain the above copyright |
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| 10 | * notice unmodified, this list of conditions, and the following |
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| 11 | * disclaimer. |
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| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer in the |
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| 14 | * documentation and/or other materials provided with the distribution. |
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| 15 | * |
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| 16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 26 | * SUCH DAMAGE. |
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| 27 | * |
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| 28 | * $FreeBSD: src/sys/dev/fxp/if_fxpreg.h,v 1.23.2.4 2001/08/31 02:17:02 jlemon Exp $ |
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| 29 | */ |
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| 30 | |
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| 31 | #define FXP_VENDORID_INTEL 0x8086 |
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| 32 | |
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| 33 | #define FXP_PCI_MMBA 0x10 |
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| 34 | #define FXP_PCI_IOBA 0x14 |
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| 35 | |
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| 36 | /* |
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| 37 | * Control/status registers. |
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| 38 | */ |
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| 39 | #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ |
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| 40 | #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ |
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| 41 | #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ |
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| 42 | #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ |
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| 43 | #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ |
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| 44 | #define FXP_CSR_PORT 8 /* port (4 bytes) */ |
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| 45 | #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ |
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| 46 | #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ |
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| 47 | #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ |
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| 48 | #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ |
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| 49 | #define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ |
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| 50 | |
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| 51 | /* |
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| 52 | * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: |
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| 53 | * |
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| 54 | * volatile u_int8_t :2, |
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| 55 | * scb_rus:4, |
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| 56 | * scb_cus:2; |
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| 57 | */ |
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| 58 | |
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| 59 | #define FXP_PORT_SOFTWARE_RESET 0 |
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| 60 | #define FXP_PORT_SELFTEST 1 |
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| 61 | #define FXP_PORT_SELECTIVE_RESET 2 |
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| 62 | #define FXP_PORT_DUMP 3 |
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| 63 | |
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| 64 | #define FXP_SCB_RUS_IDLE 0 |
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| 65 | #define FXP_SCB_RUS_SUSPENDED 1 |
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| 66 | #define FXP_SCB_RUS_NORESOURCES 2 |
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| 67 | #define FXP_SCB_RUS_READY 4 |
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| 68 | #define FXP_SCB_RUS_SUSP_NORBDS 9 |
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| 69 | #define FXP_SCB_RUS_NORES_NORBDS 10 |
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| 70 | #define FXP_SCB_RUS_READY_NORBDS 12 |
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| 71 | |
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| 72 | #define FXP_SCB_CUS_IDLE 0 |
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| 73 | #define FXP_SCB_CUS_SUSPENDED 1 |
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| 74 | #define FXP_SCB_CUS_ACTIVE 2 |
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| 75 | |
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| 76 | #define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ |
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| 77 | #define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ |
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| 78 | #define FXP_SCB_INTMASK_FCP 0x04 |
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| 79 | #define FXP_SCB_INTMASK_ER 0x08 |
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| 80 | #define FXP_SCB_INTMASK_RNR 0x10 |
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| 81 | #define FXP_SCB_INTMASK_CNA 0x20 |
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| 82 | #define FXP_SCB_INTMASK_FR 0x40 |
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| 83 | #define FXP_SCB_INTMASK_CXTNO 0x80 |
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| 84 | |
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| 85 | #define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ |
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| 86 | #define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ |
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| 87 | #define FXP_SCB_STATACK_SWI 0x04 |
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| 88 | #define FXP_SCB_STATACK_MDI 0x08 |
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| 89 | #define FXP_SCB_STATACK_RNR 0x10 |
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| 90 | #define FXP_SCB_STATACK_CNA 0x20 |
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| 91 | #define FXP_SCB_STATACK_FR 0x40 |
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| 92 | #define FXP_SCB_STATACK_CXTNO 0x80 |
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| 93 | |
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| 94 | #define FXP_SCB_COMMAND_CU_NOP 0x00 |
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| 95 | #define FXP_SCB_COMMAND_CU_START 0x10 |
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| 96 | #define FXP_SCB_COMMAND_CU_RESUME 0x20 |
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| 97 | #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 |
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| 98 | #define FXP_SCB_COMMAND_CU_DUMP 0x50 |
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| 99 | #define FXP_SCB_COMMAND_CU_BASE 0x60 |
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| 100 | #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 |
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| 101 | |
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| 102 | #define FXP_SCB_COMMAND_RU_NOP 0 |
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| 103 | #define FXP_SCB_COMMAND_RU_START 1 |
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| 104 | #define FXP_SCB_COMMAND_RU_RESUME 2 |
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| 105 | #define FXP_SCB_COMMAND_RU_ABORT 4 |
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| 106 | #define FXP_SCB_COMMAND_RU_LOADHDS 5 |
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| 107 | #define FXP_SCB_COMMAND_RU_BASE 6 |
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| 108 | #define FXP_SCB_COMMAND_RU_RBDRESUME 7 |
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| 109 | |
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| 110 | /* |
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| 111 | * Command block definitions |
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| 112 | */ |
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| 113 | struct fxp_cb_nop { |
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| 114 | void *fill[2]; |
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| 115 | volatile u_int16_t cb_status; |
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| 116 | volatile u_int16_t cb_command; |
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| 117 | volatile u_int32_t link_addr; |
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| 118 | }; |
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| 119 | struct fxp_cb_ias { |
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| 120 | void *fill[2]; |
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| 121 | volatile u_int16_t cb_status; |
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| 122 | volatile u_int16_t cb_command; |
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| 123 | volatile u_int32_t link_addr; |
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| 124 | volatile u_int8_t macaddr[6]; |
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| 125 | }; |
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| 126 | /* I hate bit-fields :-( */ |
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| 127 | struct fxp_cb_config { |
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| 128 | void *fill[2]; |
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| 129 | volatile u_int16_t cb_status; |
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| 130 | volatile u_int16_t cb_command; |
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| 131 | volatile u_int32_t link_addr; |
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| 132 | volatile u_int byte_count:6, |
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| 133 | :2; |
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| 134 | volatile u_int rx_fifo_limit:4, |
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| 135 | tx_fifo_limit:3, |
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| 136 | :1; |
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| 137 | volatile u_int8_t adaptive_ifs; |
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| 138 | volatile u_int mwi_enable:1, /* 8,9 */ |
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| 139 | type_enable:1, /* 8,9 */ |
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| 140 | read_align_en:1, /* 8,9 */ |
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| 141 | end_wr_on_cl:1, /* 8,9 */ |
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| 142 | :4; |
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| 143 | volatile u_int rx_dma_bytecount:7, |
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| 144 | :1; |
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| 145 | volatile u_int tx_dma_bytecount:7, |
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| 146 | dma_mbce:1; |
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| 147 | volatile u_int late_scb:1, /* 7 */ |
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| 148 | direct_dma_dis:1, /* 8,9 */ |
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| 149 | tno_int_or_tco_en:1, /* 7,9 */ |
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| 150 | ci_int:1, |
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| 151 | ext_txcb_dis:1, /* 8,9 */ |
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| 152 | ext_stats_dis:1, /* 8,9 */ |
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| 153 | keep_overrun_rx:1, |
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| 154 | save_bf:1; |
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| 155 | volatile u_int disc_short_rx:1, |
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| 156 | underrun_retry:2, |
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| 157 | :3, |
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| 158 | two_frames:1, /* 8,9 */ |
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| 159 | dyn_tbd:1; /* 8,9 */ |
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| 160 | volatile u_int mediatype:1, /* 7 */ |
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| 161 | :6, |
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| 162 | csma_dis:1; /* 8,9 */ |
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| 163 | volatile u_int tcp_udp_cksum:1, /* 9 */ |
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| 164 | :3, |
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| 165 | vlan_tco:1, /* 8,9 */ |
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| 166 | link_wake_en:1, /* 8,9 */ |
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| 167 | arp_wake_en:1, /* 8 */ |
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| 168 | mc_wake_en:1; /* 8 */ |
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| 169 | volatile u_int :3, |
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| 170 | nsai:1, |
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| 171 | preamble_length:2, |
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| 172 | loopback:2; |
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| 173 | volatile u_int linear_priority:3, /* 7 */ |
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| 174 | :5; |
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| 175 | volatile u_int linear_pri_mode:1, /* 7 */ |
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| 176 | :3, |
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| 177 | interfrm_spacing:4; |
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| 178 | volatile u_int :8; |
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| 179 | volatile u_int :8; |
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| 180 | volatile u_int promiscuous:1, |
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| 181 | bcast_disable:1, |
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| 182 | wait_after_win:1, /* 8,9 */ |
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| 183 | :1, |
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| 184 | ignore_ul:1, /* 8,9 */ |
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| 185 | crc16_en:1, /* 9 */ |
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| 186 | :1, |
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| 187 | crscdt:1; |
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| 188 | volatile u_int fc_delay_lsb:8; /* 8,9 */ |
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| 189 | volatile u_int fc_delay_msb:8; /* 8,9 */ |
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| 190 | volatile u_int stripping:1, |
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| 191 | padding:1, |
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| 192 | rcv_crc_xfer:1, |
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| 193 | long_rx_en:1, /* 8,9 */ |
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| 194 | pri_fc_thresh:3, /* 8,9 */ |
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| 195 | :1; |
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| 196 | volatile u_int ia_wake_en:1, /* 8 */ |
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| 197 | magic_pkt_dis:1, /* 8,9,!9ER */ |
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| 198 | tx_fc_dis:1, /* 8,9 */ |
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| 199 | rx_fc_restop:1, /* 8,9 */ |
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| 200 | rx_fc_restart:1, /* 8,9 */ |
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| 201 | fc_filter:1, /* 8,9 */ |
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| 202 | force_fdx:1, |
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| 203 | fdx_pin_en:1; |
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| 204 | volatile u_int :5, |
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| 205 | pri_fc_loc:1, /* 8,9 */ |
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| 206 | multi_ia:1, |
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| 207 | :1; |
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| 208 | volatile u_int :3, |
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| 209 | mc_all:1, |
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| 210 | :4; |
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| 211 | }; |
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| 212 | |
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| 213 | #define MAXMCADDR 80 |
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| 214 | struct fxp_cb_mcs { |
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| 215 | struct fxp_cb_tx *next; |
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| 216 | struct mbuf *mb_head; |
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| 217 | volatile u_int16_t cb_status; |
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| 218 | volatile u_int16_t cb_command; |
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| 219 | volatile u_int32_t link_addr; |
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| 220 | volatile u_int16_t mc_cnt; |
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| 221 | volatile u_int8_t mc_addr[MAXMCADDR][6]; |
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| 222 | }; |
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| 223 | |
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| 224 | /* |
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| 225 | * Number of DMA segments in a TxCB. Note that this is carefully |
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| 226 | * chosen to make the total struct size an even power of two. It's |
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| 227 | * critical that no TxCB be split across a page boundry since |
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| 228 | * no attempt is made to allocate physically contiguous memory. |
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[a3d3d9a] | 229 | * |
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[2b947a4] | 230 | */ |
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| 231 | #ifdef __alpha__ /* XXX - should be conditional on pointer size */ |
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| 232 | #define FXP_NTXSEG 28 |
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| 233 | #else |
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| 234 | #define FXP_NTXSEG 29 |
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| 235 | #endif |
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| 236 | |
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| 237 | struct fxp_tbd { |
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| 238 | volatile u_int32_t tb_addr; |
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| 239 | volatile u_int32_t tb_size; |
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| 240 | }; |
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| 241 | struct fxp_cb_tx { |
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| 242 | struct fxp_cb_tx *next; |
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| 243 | struct mbuf *mb_head; |
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| 244 | volatile u_int16_t cb_status; |
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| 245 | volatile u_int16_t cb_command; |
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| 246 | volatile u_int32_t link_addr; |
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| 247 | volatile u_int32_t tbd_array_addr; |
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| 248 | volatile u_int16_t byte_count; |
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| 249 | volatile u_int8_t tx_threshold; |
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| 250 | volatile u_int8_t tbd_number; |
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| 251 | /* |
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| 252 | * The following structure isn't actually part of the TxCB, |
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| 253 | * unless the extended TxCB feature is being used. In this |
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[a3d3d9a] | 254 | * case, the first two elements of the structure below are |
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[2b947a4] | 255 | * fetched along with the TxCB. |
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| 256 | */ |
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| 257 | volatile struct fxp_tbd tbd[FXP_NTXSEG]; |
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| 258 | }; |
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| 259 | |
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| 260 | /* |
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| 261 | * Control Block (CB) definitions |
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| 262 | */ |
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| 263 | |
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| 264 | /* status */ |
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| 265 | #define FXP_CB_STATUS_OK 0x2000 |
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| 266 | #define FXP_CB_STATUS_C 0x8000 |
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| 267 | /* commands */ |
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| 268 | #define FXP_CB_COMMAND_NOP 0x0 |
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| 269 | #define FXP_CB_COMMAND_IAS 0x1 |
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| 270 | #define FXP_CB_COMMAND_CONFIG 0x2 |
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| 271 | #define FXP_CB_COMMAND_MCAS 0x3 |
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| 272 | #define FXP_CB_COMMAND_XMIT 0x4 |
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| 273 | #define FXP_CB_COMMAND_RESRV 0x5 |
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| 274 | #define FXP_CB_COMMAND_DUMP 0x6 |
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| 275 | #define FXP_CB_COMMAND_DIAG 0x7 |
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| 276 | /* command flags */ |
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| 277 | #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ |
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| 278 | #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ |
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| 279 | #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ |
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| 280 | #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ |
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| 281 | |
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| 282 | /* |
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| 283 | * RFA definitions |
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| 284 | */ |
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| 285 | |
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| 286 | struct fxp_rfa { |
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| 287 | volatile u_int16_t rfa_status; |
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| 288 | volatile u_int16_t rfa_control; |
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| 289 | volatile u_int8_t link_addr[4]; |
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| 290 | volatile u_int8_t rbd_addr[4]; |
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| 291 | volatile u_int16_t actual_size; |
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| 292 | volatile u_int16_t size; |
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| 293 | }; |
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| 294 | #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ |
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| 295 | #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ |
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| 296 | #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ |
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| 297 | #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ |
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| 298 | #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ |
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| 299 | #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ |
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| 300 | #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ |
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| 301 | #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ |
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| 302 | #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ |
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| 303 | #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ |
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| 304 | #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ |
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| 305 | #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ |
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| 306 | #define FXP_RFA_CONTROL_H 0x10 /* header RFD */ |
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| 307 | #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ |
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| 308 | #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ |
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| 309 | |
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| 310 | /* |
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| 311 | * Statistics dump area definitions |
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| 312 | */ |
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| 313 | struct fxp_stats { |
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| 314 | volatile u_int32_t tx_good; |
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| 315 | volatile u_int32_t tx_maxcols; |
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| 316 | volatile u_int32_t tx_latecols; |
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| 317 | volatile u_int32_t tx_underruns; |
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| 318 | volatile u_int32_t tx_lostcrs; |
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| 319 | volatile u_int32_t tx_deffered; |
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| 320 | volatile u_int32_t tx_single_collisions; |
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| 321 | volatile u_int32_t tx_multiple_collisions; |
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| 322 | volatile u_int32_t tx_total_collisions; |
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| 323 | volatile u_int32_t rx_good; |
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| 324 | volatile u_int32_t rx_crc_errors; |
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| 325 | volatile u_int32_t rx_alignment_errors; |
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| 326 | volatile u_int32_t rx_rnr_errors; |
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| 327 | volatile u_int32_t rx_overrun_errors; |
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| 328 | volatile u_int32_t rx_cdt_errors; |
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| 329 | volatile u_int32_t rx_shortframes; |
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| 330 | volatile u_int32_t completion_status; |
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| 331 | }; |
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| 332 | #define FXP_STATS_DUMP_COMPLETE 0xa005 |
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| 333 | #define FXP_STATS_DR_COMPLETE 0xa007 |
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[a3d3d9a] | 334 | |
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[2b947a4] | 335 | /* |
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| 336 | * Serial EEPROM control register bits |
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| 337 | */ |
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| 338 | #define FXP_EEPROM_EESK 0x01 /* shift clock */ |
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| 339 | #define FXP_EEPROM_EECS 0x02 /* chip select */ |
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| 340 | #define FXP_EEPROM_EEDI 0x04 /* data in */ |
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| 341 | #define FXP_EEPROM_EEDO 0x08 /* data out */ |
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| 342 | |
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| 343 | /* |
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| 344 | * Serial EEPROM opcodes, including start bit |
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| 345 | */ |
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| 346 | #define FXP_EEPROM_OPC_ERASE 0x4 |
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| 347 | #define FXP_EEPROM_OPC_WRITE 0x5 |
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| 348 | #define FXP_EEPROM_OPC_READ 0x6 |
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| 349 | |
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| 350 | /* |
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| 351 | * Management Data Interface opcodes |
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| 352 | */ |
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| 353 | #define FXP_MDI_WRITE 0x1 |
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| 354 | #define FXP_MDI_READ 0x2 |
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| 355 | |
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| 356 | /* |
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| 357 | * PHY device types |
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| 358 | */ |
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| 359 | #define FXP_PHY_DEVICE_MASK 0x3f00 |
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| 360 | #define FXP_PHY_SERIAL_ONLY 0x8000 |
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| 361 | #define FXP_PHY_NONE 0 |
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| 362 | #define FXP_PHY_82553A 1 |
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| 363 | #define FXP_PHY_82553C 2 |
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| 364 | #define FXP_PHY_82503 3 |
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| 365 | #define FXP_PHY_DP83840 4 |
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| 366 | #define FXP_PHY_80C240 5 |
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| 367 | #define FXP_PHY_80C24 6 |
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| 368 | #define FXP_PHY_82555 7 |
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| 369 | #define FXP_PHY_DP83840A 10 |
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| 370 | #define FXP_PHY_82555B 11 |
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