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source: rtems/bsps/shared/net/if_dc.c @ efdb4a7

5

Last change on this file since efdb4a7 was efdb4a7, checked in by Sebastian Huber <sebastian.huber@…>, on 11/09/18 at 08:37:53
bsp/beatnik: Fix warnings
Property mode set to `100644`
File size: 92.8 KB

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1	/*
2	* Ported from FreeBSD --> RTEMS, december 03.
3	* Daron Chabot <daron@nucleus.usask.ca>
4	* -- only tested with i386 bsp.
5	* -- supports one card (until the PCI & IRQ APIs get sorted out ;-))
6	*
7	*
8	* Copyright (c) 1997, 1998, 1999
9	* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
10	*
11	* Redistribution and use in source and binary forms, with or without
12	* modification, are permitted provided that the following conditions
13	* are met:
14	* 1. Redistributions of source code must retain the above copyright
15	* notice, this list of conditions and the following disclaimer.
16	* 2. Redistributions in binary form must reproduce the above copyright
17	* notice, this list of conditions and the following disclaimer in the
18	* documentation and/or other materials provided with the distribution.
19	* 3. All advertising materials mentioning features or use of this software
20	* must display the following acknowledgement:
21	* This product includes software developed by Bill Paul.
22	* 4. Neither the name of the author nor the names of any co-contributors
23	* may be used to endorse or promote products derived from this software
24	* without specific prior written permission.
25	*
26	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
27	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36	* THE POSSIBILITY OF SUCH DAMAGE.
37	*
38	* $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $
39	*/
40
41	/*
42	* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
43	* series chips and several workalikes including the following:
44	*
45	* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
46	* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
47	* Lite-On 82c168/82c169 PNIC (www.litecom.com)
48	* ASIX Electronics AX88140A (www.asix.com.tw)
49	* ASIX Electronics AX88141 (www.asix.com.tw)
50	* ADMtek AL981 (www.admtek.com.tw)
51	* ADMtek AN985 (www.admtek.com.tw)
52	* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
53	* Accton EN1217 (www.accton.com)
54	* Conexant LANfinity (www.conexant.com)
55	*
56	* Datasheets for the 21143 are available at developer.intel.com.
57	* Datasheets for the clone parts can be found at their respective sites.
58	* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
59	* The PNIC II is essentially a Macronix 98715A chip; the only difference
60	* worth noting is that its multicast hash table is only 128 bits wide
61	* instead of 512.
62	*
63	* Written by Bill Paul <wpaul@ee.columbia.edu>
64	* Electrical Engineering Department
65	* Columbia University, New York City
66	*/
67
68	/*
69	* The Intel 21143 is the successor to the DEC 21140. It is basically
70	* the same as the 21140 but with a few new features. The 21143 supports
71	* three kinds of media attachments:
72	*
73	* o MII port, for 10Mbps and 100Mbps support and NWAY
74	* autonegotiation provided by an external PHY.
75	* o SYM port, for symbol mode 100Mbps support.
76	* o 10baseT port.
77	* o AUI/BNC port.
78	*
79	* The 100Mbps SYM port and 10baseT port can be used together in
80	* combination with the internal NWAY support to create a 10/100
81	* autosensing configuration.
82	*
83	* Note that not all tulip workalikes are handled in this driver: we only
84	* deal with those which are relatively well behaved. The Winbond is
85	* handled separately due to its different register offsets and the
86	* special handling needed for its various bugs. The PNIC is handled
87	* here, but I'm not thrilled about it.
88	*
89	* All of the workalike chips use some form of MII transceiver support
90	* with the exception of the Macronix chips, which also have a SYM port.
91	* The ASIX AX88140A is also documented to have a SYM port, but all
92	* the cards I've seen use an MII transceiver, probably because the
93	* AX88140A doesn't support internal NWAY.
94	*/
95
96	/*
97	* This driver only supports architectures with the new style
98	* exception processing. The following checks try to keep this
99	* from being compiled on systems which can't support this driver.
100	*/
101
102	#include <machine/rtems-bsd-kernel-space.h>
103
104	#if defined(DRIVER_SUPPORTED)
105	#undef DRIVER_SUPPORTED
106	#endif
107
108	#if defined(__i386__)
109	#define DRIVER_SUPPORTED
110	#endif
111
112	#if defined(__PPC__)
113	#define DRIVER_SUPPORTED
114	#endif
115
116	#include <bsp.h>
117
118	#if !defined(PCI_DRAM_OFFSET)
119	#undef DRIVER_SUPPORTED
120	#endif
121
122	#if defined(DRIVER_SUPPORTED) /* this covers the file "globally"... */
123	#include <rtems/pci.h>
124
125	#include <rtems/error.h>
126	#include <errno.h>
127	#include <rtems/rtems_bsdnet.h>
128
129	#include <net/if_types.h>
130
131	#include <sys/param.h>
132	#include <sys/sockio.h>
133	#include <sys/socket.h>
134	#include <sys/mbuf.h>
135	#include <net/if.h>
136	#include <netinet/in.h>
137	#include <netinet/if_ether.h>
138	#include <sys/malloc.h>
139	#include <sys/systm.h>
140	#include <bsp.h>
141
142	/* moved to cpukit/include/rtems in CVS current ! */
143	/#include "if_media.h" /
144	/#include "pci.h" /
145	#include <net/if_media.h>
146	#include <rtems/pci.h>
147	/*
148	#include <sys/kernel.h>
149	#include <sys/sysctl.h>
150	*/
151
152	#include <vm/vm.h> /* for vtophys */
153
154
155	#define vtophys(p) (uintptr_t)(p)
156
157	/*
158	#include <net/if_arp.h>
159	#include <net/if_vlan_var.h>
160	#include <net/bpf.h>
161	*/
162
163	#if 0
164	#include <vm/pmap.h> /* for vtophys */
165	#include <machine/clock.h> /* for DELAY */
166	#include <machine/bus_pio.h>
167	#include <machine/bus_memio.h>
168	#include <machine/bus.h>
169	#include <machine/resource.h>
170	#include <sys/bus.h>
171	#include <sys/rman.h>
172	#endif
173	#include <dev/mii/mii.h>
174	#if 0
175	#include <dev/mii/miivar.h>
176
177	#include <pci/pcireg.h>
178	#include <pci/pcivar.h>
179	#endif
180
181	/* NOTE: use mem space mapping (for now ...)
182	#define DC_USEIOSPACE
183	*/
184
185	#ifdef __alpha__
186	#define SRM_MEDIA
187	#endif
188
189	#include <bsp/irq.h>
190
191
192	#include <libchip/if_dcreg.h>
193
194
195	#define DRIVER_PREFIX "tl"
196	#define NDRIVER 1
197	#define IRQ_EVENT RTEMS_EVENT_13 /* Ha ... */
198	static struct dc_softc dc_softc_devs[NDRIVER];
199
200	#define UNUSED
201
202	#if 0
203	/* "controller miibus0" required. See GENERIC if you get errors here. */
204	#include "miibus_if.h"
205
206
207
208	#ifndef lint
209	static const char rcsid[] =
210	"$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $";
211	#endif
212
213	#endif
214
215
216	/*
217	* Various supported device vendors/types and their names.
218	* NOTE:
219	* -----
220	* Only the "ADMtek AN985" has been tested under RTEMS !!!
221	*/
222	static struct dc_type dc_devs[] = {
223	{ DC_VENDORID_DEC, DC_DEVICEID_21143,
224	"Intel 21143 10/100BaseTX", 0 },
225	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
226	"Davicom DM9009 10/100BaseTX", 0 },
227	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
228	"Davicom DM9100 10/100BaseTX", 0 },
229	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
230	"Davicom DM9102 10/100BaseTX", 0 },
231	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
232	"Davicom DM9102A 10/100BaseTX", 0 },
233	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
234	"ADMtek AL981 10/100BaseTX", 0 },
235	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
236	"ADMtek AN985 10/100BaseTX", 0 },
237	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
238	"ASIX AX88140A 10/100BaseTX", 0 },
239	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
240	"ASIX AX88141 10/100BaseTX", 0 },
241	{ DC_VENDORID_MX, DC_DEVICEID_98713,
242	"Macronix 98713 10/100BaseTX", 0 },
243	{ DC_VENDORID_MX, DC_DEVICEID_98713,
244	"Macronix 98713A 10/100BaseTX", 0 },
245	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
246	"Compex RL100-TX 10/100BaseTX", 0 },
247	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
248	"Compex RL100-TX 10/100BaseTX", 0 },
249	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
250	"Macronix 98715/98715A 10/100BaseTX", 0 },
251	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
252	"Macronix 98715AEC-C 10/100BaseTX", 0 },
253	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
254	"Macronix 98725 10/100BaseTX", 0 },
255	{ DC_VENDORID_MX, DC_DEVICEID_98727,
256	"Macronix 98727/98732 10/100BaseTX", 0 },
257	{ DC_VENDORID_LO, DC_DEVICEID_82C115,
258	"LC82C115 PNIC II 10/100BaseTX", 0 },
259	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
260	"82c168 PNIC 10/100BaseTX", 0 },
261	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
262	"82c169 PNIC 10/100BaseTX", 0 },
263	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
264	"Accton EN1217 10/100BaseTX", 0 },
265	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
266	"Accton EN2242 MiniPCI 10/100BaseTX", 0 },
267	{ DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
268	"Conexant LANfinity MiniPCI 10/100BaseTX", 0 },
269	{ 0, 0, NULL, 0 }
270	};
271
272	#if 0
273	static int dc_probe __P((device_t));
274	static int dc_attach __P((device_t));
275	static int dc_detach __P((device_t));
276	static int dc_suspend __P((device_t));
277	static int dc_resume __P((device_t));
278	static void dc_shutdown __P((device_t));
279	static void dc_acpi __P((device_t));
280	#endif
281
282	static struct dc_type *dc_devtype(int);
283	static int dc_newbuf(struct dc_softc , int, struct mbuf );
284	static int dc_encap(struct dc_softc , struct mbuf ,
285	u_int32_t *);
286	static int dc_coal(struct dc_softc , struct mbuf *);
287	static void dc_pnic_rx_bug_war(struct dc_softc *, int);
288	static int dc_rx_resync(struct dc_softc *);
289	static void dc_rxeof(struct dc_softc *);
290	static void dc_txeof(struct dc_softc *);
291	/static void dc_tick((void ));*/
292	static void dc_tx_underrun(struct dc_softc *);
293	static void dc_intr(void *);
294	static void dc_daemon(void *);
295	static void dc_start(struct ifnet *);
296	static int dc_ioctl(struct ifnet *, ioctl_command_t, caddr_t);
297	static void dc_init(void *);
298	static void dc_stop(struct dc_softc *);
299	static void dc_watchdog(struct ifnet *);
300	#if 0
301	static int dc_ifmedia_upd __P((struct ifnet *));
302	static void dc_ifmedia_sts __P((struct ifnet , struct ifmediareq ));
303	#endif
304
305	static void dc_delay(struct dc_softc *);
306	static void dc_eeprom_idle(struct dc_softc *);
307	static void dc_eeprom_putbyte(struct dc_softc *, int);
308	static void dc_eeprom_getword(struct dc_softc , int, u_int16_t );
309	static void dc_eeprom_getword_pnic(struct dc_softc , int, u_int16_t );
310	static void dc_eeprom_width(struct dc_softc *);
311	static void dc_read_eeprom(struct dc_softc *, caddr_t, int,int, int);
312
313	#if 0
314	static void dc_mii_writebit __P((struct dc_softc *, int));
315	static int dc_mii_readbit __P((struct dc_softc *));
316	static void dc_mii_sync __P((struct dc_softc *));
317	static void dc_mii_send __P((struct dc_softc *, u_int32_t, int));
318	static int dc_mii_readreg __P((struct dc_softc , struct dc_mii_frame ));
319	static int dc_mii_writereg __P((struct dc_softc , struct dc_mii_frame ));
320	static int dc_miibus_readreg __P((device_t, int, int));
321	static int dc_miibus_writereg __P((device_t, int, int, int));
322	static void dc_miibus_statchg __P((device_t));
323	static void dc_miibus_mediainit __P((device_t));
324	#endif
325
326	static void dc_setcfg(struct dc_softc *, int);
327	static u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
328	#ifndef UNUSED
329	static u_int32_t dc_crc_be(caddr_t);
330	#endif
331	static void dc_setfilt_21143(struct dc_softc *);
332	static void dc_setfilt_asix(struct dc_softc *);
333	static void dc_setfilt_admtek(struct dc_softc *);
334	static void dc_setfilt(struct dc_softc *);
335	static void dc_reset(struct dc_softc *);
336	static int dc_list_rx_init(struct dc_softc *);
337	static int dc_list_tx_init(struct dc_softc *);
338	static void dc_read_srom(struct dc_softc *, int);
339	static void dc_parse_21143_srom(struct dc_softc *);
340	static void dc_apply_fixup(struct dc_softc *, int);
341
342	#if 0
343	static void dc_decode_leaf_sia __P((struct dc_softc *,
344	struct dc_eblock_sia *));
345	static void dc_decode_leaf_mii __P((struct dc_softc *,
346	struct dc_eblock_mii *));
347	static void dc_decode_leaf_sym __P((struct dc_softc *,
348	struct dc_eblock_sym *));
349	#endif
350
351
352	#ifdef DC_USEIOSPACE
353	#define DC_RES SYS_RES_IOPORT
354	#define DC_RID DC_PCI_CFBIO
355	#else
356	#define DC_RES SYS_RES_MEMORY
357	#define DC_RID DC_PCI_CFBMA
358	#endif
359
360	#if 0
361	static device_method_t dc_methods[] = {
362	/* Device interface */
363	DEVMETHOD(device_probe, dc_probe),
364	DEVMETHOD(device_attach, dc_attach),
365	DEVMETHOD(device_detach, dc_detach),
366	DEVMETHOD(device_suspend, dc_suspend),
367	DEVMETHOD(device_resume, dc_resume),
368	DEVMETHOD(device_shutdown, dc_shutdown),
369
370	/* bus interface */
371	DEVMETHOD(bus_print_child, bus_generic_print_child),
372	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
373
374	/* MII interface */
375	DEVMETHOD(miibus_readreg, dc_miibus_readreg),
376	DEVMETHOD(miibus_writereg, dc_miibus_writereg),
377	DEVMETHOD(miibus_statchg, dc_miibus_statchg),
378	DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
379
380	{ 0, 0 }
381	};
382
383	static driver_t dc_driver = {
384	"dc",
385	dc_methods,
386	sizeof(struct dc_softc)
387	};
388
389	static devclass_t dc_devclass;
390	#endif
391
392
393	#ifdef __i386__
394	static int dc_quick=1;
395	#if 0
396	SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
397	&dc_quick,0,"do not mdevget in dc driver");
398	#endif
399	#endif
400
401	#if 0
402	DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
403	DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
404	#endif
405
406
407	#define DC_SETBIT(sc, reg, x) \
408	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) \| (x))
409
410	#define DC_CLRBIT(sc, reg, x) \
411	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
412
413	#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
414	#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
415
416
417	/* XXX Fixme: rtems_bsp_delay( ) for the pc386 BSP (at least)
418	* needs work... see pc386/include/bsp.h.
419	* I have "a" solution, utilizing the 2nd i8254 timer,
420	* if anyone is interested (first timer is used for clock_tick ISR)...
421	*/
422	#ifdef __i386__
423	extern void Wait_X_ms( unsigned int );
424	#define DELAY(n) Wait_X_ms( (unsigned int)((n)/100) )
425	#else
426	#define DELAY(n) rtems_bsp_delay(n)
427	#endif
428
429
430	static void dc_delay(sc)
431	struct dc_softc *sc;
432	{
433	int idx;
434
435	for (idx = (300 / 33) + 1; idx > 0; idx--)
436	CSR_READ_4(sc, DC_BUSCTL);
437	}
438
439	static void dc_eeprom_width(sc)
440	struct dc_softc *sc;
441	{
442	int i;
443
444	/* Force EEPROM to idle state. */
445	dc_eeprom_idle(sc);
446
447	/* Enter EEPROM access mode. */
448	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
449	dc_delay(sc);
450	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
451	dc_delay(sc);
452	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
453	dc_delay(sc);
454	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
455	dc_delay(sc);
456
457	for (i = 3; i--;) {
458	if (6 & (1 << i))
459	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
460	else
461	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
462	dc_delay(sc);
463	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
464	dc_delay(sc);
465	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
466	dc_delay(sc);
467	}
468
469	for (i = 1; i <= 12; i++) {
470	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
471	dc_delay(sc);
472	if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
473	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
474	dc_delay(sc);
475	break;
476	}
477	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
478	dc_delay(sc);
479	}
480
481	/* Turn off EEPROM access mode. */
482	dc_eeprom_idle(sc);
483
484	if (i < 4 \|\| i > 12)
485	sc->dc_romwidth = 6;
486	else
487	sc->dc_romwidth = i;
488
489	/* Enter EEPROM access mode. */
490	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
491	dc_delay(sc);
492	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
493	dc_delay(sc);
494	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
495	dc_delay(sc);
496	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
497	dc_delay(sc);
498
499	/* Turn off EEPROM access mode. */
500	dc_eeprom_idle(sc);
501	}
502
503	static void dc_eeprom_idle(sc)
504	struct dc_softc *sc;
505	{
506	register int i;
507
508	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
509	dc_delay(sc);
510	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
511	dc_delay(sc);
512	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
513	dc_delay(sc);
514	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
515	dc_delay(sc);
516
517	for (i = 0; i < 25; i++) {
518	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
519	dc_delay(sc);
520	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
521	dc_delay(sc);
522	}
523
524	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
525	dc_delay(sc);
526	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
527	dc_delay(sc);
528	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
529
530	return;
531	}
532
533	/*
534	* Send a read command and address to the EEPROM, check for ACK.
535	*/
536	static void dc_eeprom_putbyte(sc, addr)
537	struct dc_softc *sc;
538	int addr;
539	{
540	register int d, i;
541
542	d = DC_EECMD_READ >> 6;
543	for (i = 3; i--; ) {
544	if (d & (1 << i))
545	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
546	else
547	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
548	dc_delay(sc);
549	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
550	dc_delay(sc);
551	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
552	dc_delay(sc);
553	}
554
555	/*
556	* Feed in each bit and strobe the clock.
557	*/
558	for (i = sc->dc_romwidth; i--;) {
559	if (addr & (1 << i)) {
560	SIO_SET(DC_SIO_EE_DATAIN);
561	} else {
562	SIO_CLR(DC_SIO_EE_DATAIN);
563	}
564	dc_delay(sc);
565	SIO_SET(DC_SIO_EE_CLK);
566	dc_delay(sc);
567	SIO_CLR(DC_SIO_EE_CLK);
568	dc_delay(sc);
569	}
570
571	return;
572	}
573
574	/*
575	* Read a word of data stored in the EEPROM at address 'addr.'
576	* The PNIC 82c168/82c169 has its own non-standard way to read
577	* the EEPROM.
578	*/
579	static void dc_eeprom_getword_pnic(sc, addr, dest)
580	struct dc_softc *sc;
581	int addr;
582	u_int16_t *dest;
583	{
584	register int i;
585	u_int32_t r;
586
587	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ\|addr);
588
589	for (i = 0; i < DC_TIMEOUT; i++) {
590	DELAY(1);
591	r = CSR_READ_4(sc, DC_SIO);
592	if (!(r & DC_PN_SIOCTL_BUSY)) {
593	*dest = (u_int16_t)(r & 0xFFFF);
594	return;
595	}
596	}
597
598	return;
599	}
600
601	/*
602	* Read a word of data stored in the EEPROM at address 'addr.'
603	*/
604	static void dc_eeprom_getword(sc, addr, dest)
605	struct dc_softc *sc;
606	int addr;
607	u_int16_t *dest;
608	{
609	register int i;
610	u_int16_t word = 0;
611
612	/* Force EEPROM to idle state. */
613	dc_eeprom_idle(sc);
614
615	/* Enter EEPROM access mode. */
616	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
617	dc_delay(sc);
618	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
619	dc_delay(sc);
620	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
621	dc_delay(sc);
622	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
623	dc_delay(sc);
624
625	/*
626	* Send address of word we want to read.
627	*/
628	dc_eeprom_putbyte(sc, addr);
629
630	/*
631	* Start reading bits from EEPROM.
632	*/
633	for (i = 0x8000; i; i >>= 1) {
634	SIO_SET(DC_SIO_EE_CLK);
635	dc_delay(sc);
636	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
637	word \|= i;
638	dc_delay(sc);
639	SIO_CLR(DC_SIO_EE_CLK);
640	dc_delay(sc);
641	}
642
643	/* Turn off EEPROM access mode. */
644	dc_eeprom_idle(sc);
645
646	*dest = word;
647
648	return;
649	}
650
651	/*
652	* Read a sequence of words from the EEPROM.
653	*/
654	static void dc_read_eeprom(sc, dest, off, cnt, swap)
655	struct dc_softc *sc;
656	caddr_t dest;
657	int off;
658	int cnt;
659	int swap;
660	{
661	int i;
662	u_int16_t word = 0, *ptr;
663
664	for (i = 0; i < cnt; i++) {
665	if (DC_IS_PNIC(sc))
666	dc_eeprom_getword_pnic(sc, off + i, &word);
667	else
668	dc_eeprom_getword(sc, off + i, &word);
669	ptr = (u_int16_t )(dest + (i 2));
670	if (swap)
671	*ptr = ntohs(word);
672	else
673	*ptr = word;
674	}
675
676	return;
677	}
678
679
680	#if 0
681	/*
682	* The following two routines are taken from the Macronix 98713
683	* Application Notes pp.19-21.
684	*/
685	/*
686	* Write a bit to the MII bus.
687	*/
688	static void dc_mii_writebit(sc, bit)
689	struct dc_softc *sc;
690	int bit;
691	{
692	if (bit)
693	CSR_WRITE_4(sc, DC_SIO,
694	DC_SIO_ROMCTL_WRITE\|DC_SIO_MII_DATAOUT);
695	else
696	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
697
698	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
699	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
700
701	return;
702	}
703
704	/*
705	* Read a bit from the MII bus.
706	*/
707	static int dc_mii_readbit(sc)
708	struct dc_softc *sc;
709	{
710	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ\|DC_SIO_MII_DIR);
711	CSR_READ_4(sc, DC_SIO);
712	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
713	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
714	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
715	return(1);
716
717	return(0);
718	}
719
720	/*
721	* Sync the PHYs by setting data bit and strobing the clock 32 times.
722	*/
723	static void dc_mii_sync(sc)
724	struct dc_softc *sc;
725	{
726	register int i;
727
728	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
729
730	for (i = 0; i < 32; i++)
731	dc_mii_writebit(sc, 1);
732
733	return;
734	}
735
736	/*
737	* Clock a series of bits through the MII.
738	*/
739	static void dc_mii_send(sc, bits, cnt)
740	struct dc_softc *sc;
741	u_int32_t bits;
742	int cnt;
743	{
744	int i;
745
746	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
747	dc_mii_writebit(sc, bits & i);
748	}
749
750	/*
751	* Read an PHY register through the MII.
752	*/
753	static int dc_mii_readreg(sc, frame)
754	struct dc_softc *sc;
755	struct dc_mii_frame *frame;
756
757	{
758	int i, ack, s;
759
760
761	/*
762	* Set up frame for RX.
763	*/
764	frame->mii_stdelim = DC_MII_STARTDELIM;
765	frame->mii_opcode = DC_MII_READOP;
766	frame->mii_turnaround = 0;
767	frame->mii_data = 0;
768
769	/*
770	* Sync the PHYs.
771	*/
772	dc_mii_sync(sc);
773
774	/*
775	* Send command/address info.
776	*/
777	dc_mii_send(sc, frame->mii_stdelim, 2);
778	dc_mii_send(sc, frame->mii_opcode, 2);
779	dc_mii_send(sc, frame->mii_phyaddr, 5);
780	dc_mii_send(sc, frame->mii_regaddr, 5);
781
782	#ifdef notdef
783	/* Idle bit */
784	dc_mii_writebit(sc, 1);
785	dc_mii_writebit(sc, 0);
786	#endif
787
788	/* Check for ack */
789	ack = dc_mii_readbit(sc);
790
791	/*
792	* Now try reading data bits. If the ack failed, we still
793	* need to clock through 16 cycles to keep the PHY(s) in sync.
794	*/
795	if (ack) {
796	for(i = 0; i < 16; i++) {
797	dc_mii_readbit(sc);
798	}
799	goto fail;
800	}
801
802	for (i = 0x8000; i; i >>= 1) {
803	if (!ack) {
804	if (dc_mii_readbit(sc))
805	frame->mii_data \|= i;
806	}
807	}
808
809	fail:
810
811	dc_mii_writebit(sc, 0);
812	dc_mii_writebit(sc, 0);
813
814
815	if (ack)
816	return(1);
817	return(0);
818	}
819
820	/*
821	* Write to a PHY register through the MII.
822	*/
823	static int dc_mii_writereg(sc, frame)
824	struct dc_softc *sc;
825	struct dc_mii_frame *frame;
826
827	{
828	int s;
829
830	/*
831	* Set up frame for TX.
832	*/
833
834	frame->mii_stdelim = DC_MII_STARTDELIM;
835	frame->mii_opcode = DC_MII_WRITEOP;
836	frame->mii_turnaround = DC_MII_TURNAROUND;
837
838	/*
839	* Sync the PHYs.
840	*/
841	dc_mii_sync(sc);
842
843	dc_mii_send(sc, frame->mii_stdelim, 2);
844	dc_mii_send(sc, frame->mii_opcode, 2);
845	dc_mii_send(sc, frame->mii_phyaddr, 5);
846	dc_mii_send(sc, frame->mii_regaddr, 5);
847	dc_mii_send(sc, frame->mii_turnaround, 2);
848	dc_mii_send(sc, frame->mii_data, 16);
849
850	/* Idle bit. */
851	dc_mii_writebit(sc, 0);
852	dc_mii_writebit(sc, 0);
853
854
855	return(0);
856	}
857
858	static int dc_miibus_readreg(dev, phy, reg)
859	device_t dev;
860	int phy, reg;
861	{
862	struct dc_mii_frame frame;
863	struct dc_softc *sc;
864	int i, rval, phy_reg = 0;
865
866	sc = device_get_softc(dev);
867	bzero((char *)&frame, sizeof(frame));
868
869	/*
870	* Note: both the AL981 and AN985 have internal PHYs,
871	* however the AL981 provides direct access to the PHY
872	* registers while the AN985 uses a serial MII interface.
873	* The AN985's MII interface is also buggy in that you
874	* can read from any MII address (0 to 31), but only address 1
875	* behaves normally. To deal with both cases, we pretend
876	* that the PHY is at MII address 1.
877	*/
878	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
879	return(0);
880
881	/*
882	* Note: the ukphy probes of the RS7112 report a PHY at
883	* MII address 0 (possibly HomePNA?) and 1 (ethernet)
884	* so we only respond to correct one.
885	*/
886	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
887	return(0);
888
889	if (sc->dc_pmode != DC_PMODE_MII) {
890	if (phy == (MII_NPHY - 1)) {
891	switch(reg) {
892	case MII_BMSR:
893	/*
894	* Fake something to make the probe
895	* code think there's a PHY here.
896	*/
897	return(BMSR_MEDIAMASK);
898	break;
899	case MII_PHYIDR1:
900	if (DC_IS_PNIC(sc))
901	return(DC_VENDORID_LO);
902	return(DC_VENDORID_DEC);
903	break;
904	case MII_PHYIDR2:
905	if (DC_IS_PNIC(sc))
906	return(DC_DEVICEID_82C168);
907	return(DC_DEVICEID_21143);
908	break;
909	default:
910	return(0);
911	break;
912	}
913	} else
914	return(0);
915	}
916
917	if (DC_IS_PNIC(sc)) {
918	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ \|
919	(phy << 23) \| (reg << 18));
920	for (i = 0; i < DC_TIMEOUT; i++) {
921	DELAY(1);
922	rval = CSR_READ_4(sc, DC_PN_MII);
923	if (!(rval & DC_PN_MII_BUSY)) {
924	rval &= 0xFFFF;
925	return(rval == 0xFFFF ? 0 : rval);
926	}
927	}
928	return(0);
929	}
930
931	if (DC_IS_COMET(sc)) {
932	switch(reg) {
933	case MII_BMCR:
934	phy_reg = DC_AL_BMCR;
935	break;
936	case MII_BMSR:
937	phy_reg = DC_AL_BMSR;
938	break;
939	case MII_PHYIDR1:
940	phy_reg = DC_AL_VENID;
941	break;
942	case MII_PHYIDR2:
943	phy_reg = DC_AL_DEVID;
944	break;
945	case MII_ANAR:
946	phy_reg = DC_AL_ANAR;
947	break;
948	case MII_ANLPAR:
949	phy_reg = DC_AL_LPAR;
950	break;
951	case MII_ANER:
952	phy_reg = DC_AL_ANER;
953	break;
954	default:
955	printk("dc%d: phy_read: bad phy register %x\n",
956	sc->dc_unit, reg);
957	return(0);
958	break;
959	}
960
961	rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
962
963	if (rval == 0xFFFF)
964	return(0);
965	return(rval);
966	}
967
968	frame.mii_phyaddr = phy;
969	frame.mii_regaddr = reg;
970	if (sc->dc_type == DC_TYPE_98713) {
971	phy_reg = CSR_READ_4(sc, DC_NETCFG);
972	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
973	}
974	dc_mii_readreg(sc, &frame);
975	if (sc->dc_type == DC_TYPE_98713)
976	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
977
978	return(frame.mii_data);
979	}
980
981	static int dc_miibus_writereg(dev, phy, reg, data)
982	device_t dev;
983	int phy, reg, data;
984	{
985	struct dc_softc *sc;
986	struct dc_mii_frame frame;
987	int i, phy_reg = 0;
988
989	sc = device_get_softc(dev);
990	bzero((char *)&frame, sizeof(frame));
991
992	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
993	return(0);
994
995	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
996	return(0);
997
998	if (DC_IS_PNIC(sc)) {
999	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE \|
1000	(phy << 23) \| (reg << 10) \| data);
1001	for (i = 0; i < DC_TIMEOUT; i++) {
1002	if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
1003	break;
1004	}
1005	return(0);
1006	}
1007
1008	if (DC_IS_COMET(sc)) {
1009	switch(reg) {
1010	case MII_BMCR:
1011	phy_reg = DC_AL_BMCR;
1012	break;
1013	case MII_BMSR:
1014	phy_reg = DC_AL_BMSR;
1015	break;
1016	case MII_PHYIDR1:
1017	phy_reg = DC_AL_VENID;
1018	break;
1019	case MII_PHYIDR2:
1020	phy_reg = DC_AL_DEVID;
1021	break;
1022	case MII_ANAR:
1023	phy_reg = DC_AL_ANAR;
1024	break;
1025	case MII_ANLPAR:
1026	phy_reg = DC_AL_LPAR;
1027	break;
1028	case MII_ANER:
1029	phy_reg = DC_AL_ANER;
1030	break;
1031	default:
1032	printk("dc%d: phy_write: bad phy register %x\n",
1033	sc->dc_unit, reg);
1034	return(0);
1035	break;
1036	}
1037
1038	CSR_WRITE_4(sc, phy_reg, data);
1039	return(0);
1040	}
1041
1042	frame.mii_phyaddr = phy;
1043	frame.mii_regaddr = reg;
1044	frame.mii_data = data;
1045
1046	if (sc->dc_type == DC_TYPE_98713) {
1047	phy_reg = CSR_READ_4(sc, DC_NETCFG);
1048	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
1049	}
1050	dc_mii_writereg(sc, &frame);
1051	if (sc->dc_type == DC_TYPE_98713)
1052	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
1053
1054	return(0);
1055	}
1056
1057	static void dc_miibus_statchg(dev)
1058	device_t dev;
1059	{
1060	struct dc_softc *sc;
1061	struct mii_data *mii;
1062	struct ifmedia *ifm;
1063
1064	sc = device_get_softc(dev);
1065	if (DC_IS_ADMTEK(sc))
1066	return;
1067
1068	mii = device_get_softc(sc->dc_miibus);
1069	ifm = &mii->mii_media;
1070	if (DC_IS_DAVICOM(sc) &&
1071	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
1072	dc_setcfg(sc, ifm->ifm_media);
1073	sc->dc_if_media = ifm->ifm_media;
1074	} else {
1075	dc_setcfg(sc, mii->mii_media_active);
1076	sc->dc_if_media = mii->mii_media_active;
1077	}
1078
1079	return;
1080	}
1081
1082	/*
1083	* Special support for DM9102A cards with HomePNA PHYs. Note:
1084	* with the Davicom DM9102A/DM9801 eval board that I have, it seems
1085	* to be impossible to talk to the management interface of the DM9801
1086	* PHY (its MDIO pin is not connected to anything). Consequently,
1087	* the driver has to just 'know' about the additional mode and deal
1088	* with it itself. sigh
1089	*/
1090	static void dc_miibus_mediainit(dev)
1091	device_t dev;
1092	{
1093	struct dc_softc *sc;
1094	struct mii_data *mii;
1095	struct ifmedia *ifm;
1096	int rev;
1097
1098	rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1099
1100	sc = device_get_softc(dev);
1101	mii = device_get_softc(sc->dc_miibus);
1102	ifm = &mii->mii_media;
1103
1104	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1105	ifmedia_add(ifm, IFM_ETHER\|IFM_homePNA, 0, NULL);
1106
1107	return;
1108	}
1109	#endif
1110
1111	#define DC_POLY 0xEDB88320
1112	#define DC_BITS_512 9
1113	#define DC_BITS_128 7
1114	#define DC_BITS_64 6
1115
1116	static u_int32_t dc_crc_le(sc, addr)
1117	struct dc_softc *sc;
1118	caddr_t addr;
1119	{
1120	u_int32_t idx, bit, data, crc;
1121
1122	/* Compute CRC for the address value. */
1123	crc = 0xFFFFFFFF; /* initial value */
1124
1125	for (idx = 0; idx < 6; idx++) {
1126	for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1127	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1128	}
1129
1130	/*
1131	* The hash table on the PNIC II and the MX98715AEC-C/D/E
1132	* chips is only 128 bits wide.
1133	*/
1134	if (sc->dc_flags & DC_128BIT_HASH)
1135	return (crc & ((1 << DC_BITS_128) - 1));
1136
1137	/* The hash table on the MX98715BEC is only 64 bits wide. */
1138	if (sc->dc_flags & DC_64BIT_HASH)
1139	return (crc & ((1 << DC_BITS_64) - 1));
1140
1141	return (crc & ((1 << DC_BITS_512) - 1));
1142	}
1143
1144	#ifndef UNUSED
1145	/*
1146	* Calculate CRC of a multicast group address, return the lower 6 bits.
1147	*/
1148	static u_int32_t dc_crc_be(addr)
1149	caddr_t addr;
1150	{
1151	u_int32_t crc, carry;
1152	int i, j;
1153	u_int8_t c;
1154
1155	/* Compute CRC for the address value. */
1156	crc = 0xFFFFFFFF; /* initial value */
1157
1158	for (i = 0; i < 6; i++) {
1159	c = *(addr + i);
1160	for (j = 0; j < 8; j++) {
1161	carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1162	crc <<= 1;
1163	c >>= 1;
1164	if (carry)
1165	crc = (crc ^ 0x04c11db6) \| carry;
1166	}
1167	}
1168
1169	/* return the filter bit position */
1170	return((crc >> 26) & 0x0000003F);
1171	}
1172	#endif
1173
1174	/*
1175	* 21143-style RX filter setup routine. Filter programming is done by
1176	* downloading a special setup frame into the TX engine. 21143, Macronix,
1177	* PNIC, PNIC II and Davicom chips are programmed this way.
1178	*
1179	* We always program the chip using 'hash perfect' mode, i.e. one perfect
1180	* address (our node address) and a 512-bit hash filter for multicast
1181	* frames. We also sneak the broadcast address into the hash filter since
1182	* we need that too.
1183	*/
1184	void dc_setfilt_21143(sc)
1185	struct dc_softc *sc;
1186	{
1187	struct dc_desc *sframe;
1188	u_int32_t h, *sp;
1189	/struct ifmultiaddr ifma;*/
1190	struct ifnet *ifp;
1191	int i;
1192	u_int16_t *ac_enaddr;
1193
1194	ifp = &sc->arpcom.ac_if;
1195
1196	i = sc->dc_cdata.dc_tx_prod;
1197	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1198	sc->dc_cdata.dc_tx_cnt++;
1199	sframe = &sc->dc_ldata->dc_tx_list[i];
1200	sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1201	bzero((char *)sp, DC_SFRAME_LEN);
1202
1203	sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1204	sframe->dc_ctl = DC_SFRAME_LEN \| DC_TXCTL_SETUP \| DC_TXCTL_TLINK \|
1205	DC_FILTER_HASHPERF \| DC_TXCTL_FINT;
1206
1207	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1208
1209	/* If we want promiscuous mode, set the allframes bit. */
1210	if (ifp->if_flags & IFF_PROMISC)
1211	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1212	else
1213	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1214
1215	if (ifp->if_flags & IFF_ALLMULTI)
1216	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1217	else
1218	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1219	#if 0
1220	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1221	ifma = ifma->ifma_link.le_next) {
1222	if (ifma->ifma_addr->sa_family != AF_LINK)
1223	continue;
1224	h = dc_crc_le(sc,
1225	LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1226	sp[h >> 4] \|= 1 << (h & 0xF);
1227	}
1228	#endif
1229
1230	if (ifp->if_flags & IFF_BROADCAST) {
1231	h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
1232	sp[h >> 4] \|= 1 << (h & 0xF);
1233	}
1234
1235	/* Set our MAC address */
1236	ac_enaddr = (u_int16_t *)sc->arpcom.ac_enaddr;
1237	sp[39] = ac_enaddr[0];
1238	sp[40] = ac_enaddr[1];
1239	sp[41] = ac_enaddr[2];
1240
1241	sframe->dc_status = DC_TXSTAT_OWN;
1242	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1243
1244	/*
1245	* The PNIC takes an exceedingly long time to process its
1246	* setup frame; wait 10ms after posting the setup frame
1247	* before proceeding, just so it has time to swallow its
1248	* medicine.
1249	*/
1250	DELAY(10000);
1251
1252	ifp->if_timer = 5;
1253
1254	return;
1255	}
1256
1257	void dc_setfilt_admtek(sc)
1258	struct dc_softc *sc;
1259	{
1260	struct ifnet *ifp;
1261	#if 0
1262	int h = 0;
1263	u_int32_t hashes[2] = { 0, 0 };
1264	struct ifmultiaddr *ifma;
1265	#endif
1266	u_int32_t *ac_enaddr;
1267
1268	ifp = &sc->arpcom.ac_if;
1269
1270	/* Init our MAC address */
1271	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0];
1272	CSR_WRITE_4(sc, DC_AL_PAR0, *ac_enaddr);
1273	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4];
1274	CSR_WRITE_4(sc, DC_AL_PAR1, *ac_enaddr);
1275
1276	/* If we want promiscuous mode, set the allframes bit. */
1277	if (ifp->if_flags & IFF_PROMISC)
1278	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1279	else
1280	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1281
1282	if (ifp->if_flags & IFF_ALLMULTI)
1283	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1284	else
1285	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1286
1287	/* first, zot all the existing hash bits */
1288	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1289	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1290
1291	#if 0
1292	/*
1293	* If we're already in promisc or allmulti mode, we
1294	* don't have to bother programming the multicast filter.
1295	*/
1296	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1297	return;
1298
1299	/* now program new ones */
1300	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1301	ifma = ifma->ifma_link.le_next) {
1302	if (ifma->ifma_addr->sa_family != AF_LINK)
1303	continue;
1304	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1305	if (h < 32)
1306	hashes[0] \|= (1 << h);
1307	else
1308	hashes[1] \|= (1 << (h - 32));
1309	}
1310
1311	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1312	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1313	#endif
1314	return;
1315	}
1316
1317	void dc_setfilt_asix(sc)
1318	struct dc_softc *sc;
1319	{
1320	struct ifnet *ifp;
1321	#if 0
1322	int h = 0;
1323	u_int32_t hashes[2] = { 0, 0 };
1324	struct ifmultiaddr *ifma;
1325	#endif
1326	u_int32_t *ac_enaddr;
1327
1328	ifp = &sc->arpcom.ac_if;
1329
1330	/* Init our MAC address */
1331	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1332	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0];
1333	CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr);
1334
1335	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1336
1337	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4];
1338	CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr);
1339
1340	/* If we want promiscuous mode, set the allframes bit. */
1341	if (ifp->if_flags & IFF_PROMISC)
1342	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1343	else
1344	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1345
1346	if (ifp->if_flags & IFF_ALLMULTI)
1347	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1348	else
1349	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1350
1351	/*
1352	* The ASIX chip has a special bit to enable reception
1353	* of broadcast frames.
1354	*/
1355	if (ifp->if_flags & IFF_BROADCAST)
1356	DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1357	else
1358	DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1359
1360	/* first, zot all the existing hash bits */
1361	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1362	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1363	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1364	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1365
1366	#if 0
1367	/*
1368	* If we're already in promisc or allmulti mode, we
1369	* don't have to bother programming the multicast filter.
1370	*/
1371	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1372	return;
1373
1374	/* now program new ones */
1375	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1376	ifma = ifma->ifma_link.le_next) {
1377	if (ifma->ifma_addr->sa_family != AF_LINK)
1378	continue;
1379	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1380	if (h < 32)
1381	hashes[0] \|= (1 << h);
1382	else
1383	hashes[1] \|= (1 << (h - 32));
1384	}
1385
1386	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1387	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1388	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1389	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1390	#endif
1391	return;
1392	}
1393
1394	static void dc_setfilt(sc)
1395	struct dc_softc *sc;
1396	{
1397	if (DC_IS_INTEL(sc) \|\| DC_IS_MACRONIX(sc) \|\| DC_IS_PNIC(sc) \|\|
1398	DC_IS_PNICII(sc) \|\| DC_IS_DAVICOM(sc) \|\| DC_IS_CONEXANT(sc))
1399	dc_setfilt_21143(sc);
1400
1401	if (DC_IS_ASIX(sc))
1402	dc_setfilt_asix(sc);
1403
1404	if (DC_IS_ADMTEK(sc))
1405	dc_setfilt_admtek(sc);
1406
1407	return;
1408	}
1409
1410	/*
1411	* In order to fiddle with the
1412	* 'full-duplex' and '100Mbps' bits in the netconfig register, we
1413	* first have to put the transmit and/or receive logic in the idle state.
1414	*/
1415	static void dc_setcfg(sc, media)
1416	struct dc_softc *sc;
1417	int media;
1418	{
1419	int i, restart = 0;
1420	u_int32_t isr;
1421
1422	if (IFM_SUBTYPE(media) == IFM_NONE)
1423	return;
1424
1425	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON)) {
1426	restart = 1;
1427	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON));
1428
1429	for (i = 0; i < DC_TIMEOUT; i++) {
1430	isr = CSR_READ_4(sc, DC_ISR);
1431	if (isr & DC_ISR_TX_IDLE \|\|
1432	(isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1433	break;
1434	DELAY(10);
1435	}
1436
1437	if (i == DC_TIMEOUT)
1438	printk("dc%d: failed to force tx and "
1439	"rx to idle state\n", sc->dc_unit);
1440	}
1441
1442	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1443	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1444	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1445	if (sc->dc_pmode == DC_PMODE_MII) {
1446	int watchdogreg;
1447
1448	if (DC_IS_INTEL(sc)) {
1449	/* there's a write enable bit here that reads as 1 */
1450	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1451	watchdogreg &= ~DC_WDOG_CTLWREN;
1452	watchdogreg \|= DC_WDOG_JABBERDIS;
1453	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1454	} else {
1455	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1456	}
1457	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1458	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1459	if (sc->dc_type == DC_TYPE_98713)
1460	DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1461	DC_NETCFG_SCRAMBLER));
1462	if (!DC_IS_DAVICOM(sc))
1463	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1464	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1465	if (DC_IS_INTEL(sc))
1466	dc_apply_fixup(sc, IFM_AUTO);
1467	} else {
1468	if (DC_IS_PNIC(sc)) {
1469	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1470	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1471	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1472	}
1473	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1474	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1475	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1476	if (DC_IS_INTEL(sc))
1477	dc_apply_fixup(sc,
1478	(media & IFM_GMASK) == IFM_FDX ?
1479	IFM_100_TX\|IFM_FDX : IFM_100_TX);
1480	}
1481	}
1482
1483	if (IFM_SUBTYPE(media) == IFM_10_T) {
1484	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1485	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1486	if (sc->dc_pmode == DC_PMODE_MII) {
1487	int watchdogreg;
1488
1489	/* there's a write enable bit here that reads as 1 */
1490	if (DC_IS_INTEL(sc)) {
1491	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1492	watchdogreg &= ~DC_WDOG_CTLWREN;
1493	watchdogreg \|= DC_WDOG_JABBERDIS;
1494	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1495	} else {
1496	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1497	}
1498	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1499	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1500	if (sc->dc_type == DC_TYPE_98713)
1501	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1502	if (!DC_IS_DAVICOM(sc))
1503	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1504	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1505	if (DC_IS_INTEL(sc))
1506	dc_apply_fixup(sc, IFM_AUTO);
1507	} else {
1508	if (DC_IS_PNIC(sc)) {
1509	DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1510	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1511	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1512	}
1513	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1514	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1515	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1516	if (DC_IS_INTEL(sc)) {
1517	DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1518	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1519	if ((media & IFM_GMASK) == IFM_FDX)
1520	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1521	else
1522	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1523	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1524	DC_CLRBIT(sc, DC_10BTCTRL,
1525	DC_TCTL_AUTONEGENBL);
1526	dc_apply_fixup(sc,
1527	(media & IFM_GMASK) == IFM_FDX ?
1528	IFM_10_T\|IFM_FDX : IFM_10_T);
1529	DELAY(20000);
1530	}
1531	}
1532	}
1533
1534	#if 0
1535	/*
1536	* If this is a Davicom DM9102A card with a DM9801 HomePNA
1537	* PHY and we want HomePNA mode, set the portsel bit to turn
1538	* on the external MII port.
1539	*/
1540	if (DC_IS_DAVICOM(sc)) {
1541	if (IFM_SUBTYPE(media) == IFM_homePNA) {
1542	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1543	sc->dc_link = 1;
1544	} else {
1545	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1546	}
1547	}
1548	#endif
1549
1550	if ((media & IFM_GMASK) == IFM_FDX) {
1551	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1552	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1553	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1554	} else {
1555	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1556	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1557	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1558	}
1559
1560	if (restart)
1561	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON);
1562
1563	return;
1564	}
1565
1566	static void dc_reset(sc)
1567	struct dc_softc *sc;
1568	{
1569	register int i;
1570
1571	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1572
1573	for (i = 0; i < DC_TIMEOUT; i++) {
1574	DELAY(10);
1575	if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1576	break;
1577	}
1578
1579	if (DC_IS_ASIX(sc) \|\| DC_IS_ADMTEK(sc) \|\| DC_IS_CONEXANT(sc)) {
1580	DELAY(10000);
1581	DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1582	i = 0;
1583	}
1584
1585	if (i == DC_TIMEOUT)
1586	printk("dc%d: reset never completed!\n", sc->dc_unit);
1587
1588	/* Wait a little while for the chip to get its brains in order. */
1589	DELAY(1000);
1590
1591	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1592	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1593	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1594
1595	/*
1596	* Bring the SIA out of reset. In some cases, it looks
1597	* like failing to unreset the SIA soon enough gets it
1598	* into a state where it will never come out of reset
1599	* until we reset the whole chip again.
1600	*/
1601	if (DC_IS_INTEL(sc)) {
1602	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1603	CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1604	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1605	}
1606
1607	return;
1608	}
1609
1610	static
1611	struct dc_type *dc_devtype( int unitnum )
1612	{
1613	struct dc_type *t;
1614	uint32_t rev;
1615	int rc;
1616
1617
1618	t = dc_devs;
1619
1620	while(t->dc_name != NULL) {
1621	rc = pci_find_device(t->dc_vid, t->dc_did, \
1622	(unitnum - 1), &t->dc_bus, &t->dc_dev, &t->dc_fun);
1623	if (rc == PCIB_ERR_SUCCESS) {
1624	/* Check the PCI revision */
1625	/pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); /
1626	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1627	DC_PCI_CFRV, &rev);
1628	rev &= 0xFF;
1629
1630	if (t->dc_did == DC_DEVICEID_98713 &&
1631	rev >= DC_REVISION_98713A)
1632	t++;
1633	if (t->dc_did == DC_DEVICEID_98713_CP &&
1634	rev >= DC_REVISION_98713A)
1635	t++;
1636	if (t->dc_did == DC_DEVICEID_987x5 &&
1637	rev >= DC_REVISION_98715AEC_C)
1638	t++;
1639	if (t->dc_did == DC_DEVICEID_987x5 &&
1640	rev >= DC_REVISION_98725)
1641	t++;
1642	if (t->dc_did == DC_DEVICEID_AX88140A &&
1643	rev >= DC_REVISION_88141)
1644	t++;
1645	if (t->dc_did == DC_DEVICEID_82C168 &&
1646	rev >= DC_REVISION_82C169)
1647	t++;
1648	if (t->dc_did == DC_DEVICEID_DM9102 &&
1649	rev >= DC_REVISION_DM9102A)
1650	t++;
1651	return(t);
1652	}
1653	t++;
1654	}
1655
1656	return(NULL);
1657	}
1658
1659	#if 0
1660	/*
1661	* Probe for a 21143 or clone chip. Check the PCI vendor and device
1662	* IDs against our list and return a device name if we find a match.
1663	* We do a little bit of extra work to identify the exact type of
1664	* chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1665	* but different revision IDs. The same is true for 98715/98715A
1666	* chips and the 98725, as well as the ASIX and ADMtek chips. In some
1667	* cases, the exact chip revision affects driver behavior.
1668	*/
1669	static int dc_probe(dev)
1670	device_t dev;
1671	{
1672	struct dc_type *t;
1673
1674	t = dc_devtype(dev);
1675
1676	if (t != NULL) {
1677	device_set_desc(dev, t->dc_name);
1678	return(0);
1679	}
1680
1681	return(ENXIO);
1682	}
1683
1684
1685	static void dc_acpi(dev)
1686	device_t dev;
1687	{
1688	u_int32_t r, cptr;
1689	int unit;
1690
1691	unit = device_get_unit(dev);
1692
1693	/* Find the location of the capabilities block */
1694	cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1695
1696	r = pci_read_config(dev, cptr, 4) & 0xFF;
1697	if (r == 0x01) {
1698
1699	r = pci_read_config(dev, cptr + 4, 4);
1700	if (r & DC_PSTATE_D3) {
1701	u_int32_t iobase, membase, irq;
1702
1703	/* Save important PCI config data. */
1704	iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1705	membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1706	irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1707
1708	/* Reset the power state. */
1709	printk("dc%d: chip is in D%d power mode "
1710	"-- setting to D0\n", unit, r & DC_PSTATE_D3);
1711	r &= 0xFFFFFFFC;
1712	pci_write_config(dev, cptr + 4, r, 4);
1713
1714	/* Restore PCI config data. */
1715	pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1716	pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1717	pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1718	}
1719	}
1720	return;
1721	}
1722	#endif
1723
1724
1725	static void dc_apply_fixup(sc, media)
1726	struct dc_softc *sc;
1727	int media;
1728	{
1729	struct dc_mediainfo *m;
1730	u_int8_t *p;
1731	int i;
1732	u_int32_t reg;
1733
1734	m = sc->dc_mi;
1735
1736	while (m != NULL) {
1737	if (m->dc_media == media)
1738	break;
1739	m = m->dc_next;
1740	}
1741
1742	if (m == NULL)
1743	return;
1744
1745	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1746	reg = (p[0] \| (p[1] << 8)) << 16;
1747	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1748	}
1749
1750	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1751	reg = (p[0] \| (p[1] << 8)) << 16;
1752	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1753	}
1754
1755	return;
1756	}
1757
1758	#if 0
1759	static void dc_decode_leaf_sia(sc, l)
1760	struct dc_softc *sc;
1761	struct dc_eblock_sia *l;
1762	{
1763	struct dc_mediainfo *m;
1764
1765	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1766	bzero(m, sizeof(struct dc_mediainfo));
1767	if (l->dc_sia_code == DC_SIA_CODE_10BT)
1768	m->dc_media = IFM_10_T;
1769
1770	if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1771	m->dc_media = IFM_10_T\|IFM_FDX;
1772
1773	if (l->dc_sia_code == DC_SIA_CODE_10B2)
1774	m->dc_media = IFM_10_2;
1775
1776	if (l->dc_sia_code == DC_SIA_CODE_10B5)
1777	m->dc_media = IFM_10_5;
1778
1779	m->dc_gp_len = 2;
1780	m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1781
1782	m->dc_next = sc->dc_mi;
1783	sc->dc_mi = m;
1784
1785	sc->dc_pmode = DC_PMODE_SIA;
1786
1787	return;
1788	}
1789
1790	static void dc_decode_leaf_sym(sc, l)
1791	struct dc_softc *sc;
1792	struct dc_eblock_sym *l;
1793	{
1794	struct dc_mediainfo *m;
1795
1796	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1797	bzero(m, sizeof(struct dc_mediainfo));
1798	if (l->dc_sym_code == DC_SYM_CODE_100BT)
1799	m->dc_media = IFM_100_TX;
1800
1801	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1802	m->dc_media = IFM_100_TX\|IFM_FDX;
1803
1804	m->dc_gp_len = 2;
1805	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1806
1807	m->dc_next = sc->dc_mi;
1808	sc->dc_mi = m;
1809
1810	sc->dc_pmode = DC_PMODE_SYM;
1811
1812	return;
1813	}
1814
1815	static void dc_decode_leaf_mii(sc, l)
1816	struct dc_softc *sc;
1817	struct dc_eblock_mii *l;
1818	{
1819	u_int8_t *p;
1820	struct dc_mediainfo *m;
1821
1822	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1823	bzero(m, sizeof(struct dc_mediainfo));
1824	/* We abuse IFM_AUTO to represent MII. */
1825	m->dc_media = IFM_AUTO;
1826	m->dc_gp_len = l->dc_gpr_len;
1827
1828	p = (u_int8_t *)l;
1829	p += sizeof(struct dc_eblock_mii);
1830	m->dc_gp_ptr = p;
1831	p += 2 * l->dc_gpr_len;
1832	m->dc_reset_len = *p;
1833	p++;
1834	m->dc_reset_ptr = p;
1835
1836	m->dc_next = sc->dc_mi;
1837	sc->dc_mi = m;
1838
1839	return;
1840	}
1841	#endif
1842
1843	static void dc_read_srom(sc, bits)
1844	struct dc_softc *sc;
1845	int bits;
1846	{
1847	int size;
1848
1849	size = 2 << bits;
1850	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1851	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1852	}
1853
1854	static void dc_parse_21143_srom(sc)
1855	struct dc_softc *sc;
1856	{
1857	struct dc_leaf_hdr *lhdr;
1858	struct dc_eblock_hdr *hdr;
1859	int i, loff;
1860	char *ptr;
1861
1862	loff = sc->dc_srom[27];
1863	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1864
1865	ptr = (char *)lhdr;
1866	ptr += sizeof(struct dc_leaf_hdr) - 1;
1867	for (i = 0; i < lhdr->dc_mcnt; i++) {
1868	hdr = (struct dc_eblock_hdr *)ptr;
1869	switch(hdr->dc_type) {
1870	#if 0
1871	case DC_EBLOCK_MII:
1872	dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1873	break;
1874	case DC_EBLOCK_SIA:
1875	dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr);
1876	break;
1877	case DC_EBLOCK_SYM:
1878	dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr);
1879	break;
1880	#endif
1881	default:
1882	/* Don't care. Yet. */
1883	break;
1884	}
1885	ptr += (hdr->dc_len & 0x7F);
1886	ptr++;
1887	}
1888
1889	return;
1890	}
1891
1892
1893	static void
1894	nop(const rtems_irq_connect_data* unused)
1895	{
1896	}
1897
1898	/*
1899	* Attach the interface. Allocate softc structures, do ifmedia
1900	* setup and ethernet/BPF attach.
1901	*/
1902	int
1903	rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
1904	{
1905	int rc;
1906	u_char eaddr[ETHER_ADDR_LEN];
1907
1908	char *unitName;
1909	int unitNumber;
1910
1911	uint32_t command;
1912	struct dc_softc *sc;
1913	struct ifnet *ifp;
1914	struct dc_type *t;
1915	uint32_t revision;
1916	int mac_offset;
1917	uint32_t value;
1918
1919	/*
1920	* Get the instance number for the board we're going to configure
1921	* from the user.
1922	*/
1923	unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName);
1924	if( unitNumber < 0) {
1925	return 0;
1926	}
1927	if( strcmp(unitName, DRIVER_PREFIX) ) {
1928	printk("dec2114x : unit name '%s' not %s\n", \
1929	unitName, DRIVER_PREFIX );
1930	return 0;
1931	}
1932
1933	sc = &dc_softc_devs[unitNumber - 1];
1934	ifp = &sc->arpcom.ac_if;
1935
1936	if(ifp->if_softc != NULL) {
1937	printk("dec2114x[%d]: unit number already in use.\n", \
1938	unitNumber);
1939	return (0);
1940	}
1941	memset(sc, 0, sizeof(struct dc_softc));
1942
1943	/unit = device_get_unit(dev);/
1944	sc->dc_unit = unitNumber;
1945	sc->dc_name = unitName;
1946
1947	/*
1948	* Handle power management nonsense.
1949	*
1950	dc_acpi(dev);
1951	*/
1952
1953	/* Scan for dec2114x cards in pci config space */
1954	if( (sc->dc_info = dc_devtype(unitNumber)) == NULL) {
1955	printk("Can't find any dec2114x NICs in PCI space.\n");
1956	return 0;
1957	}
1958	t = sc->dc_info;
1959
1960
1961	/*
1962	* Map control/status registers.
1963	*/
1964	/sig = sc->dc_info->dc_devsig; /
1965	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1966	PCI_COMMAND, &command);
1967	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1968	command \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
1969	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1970	PCI_COMMAND, command);
1971	/pcib_conf_write32(sig, PCI_COMMAND, command); /
1972	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1973	PCI_COMMAND, &command);
1974	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1975
1976	#ifdef DC_USEIOSPACE
1977	if (!(command & PCI_COMMAND_IO)) {
1978	printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit);
1979	goto fail;
1980	}
1981	#else
1982	if (!(command & PCI_COMMAND_MEMORY)) {
1983	printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit);
1984	goto fail;
1985	}
1986	#endif
1987
1988	#if 0
1989	rid = DC_RID;
1990	sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1991	0, ~0, 1, RF_ACTIVE);
1992
1993	if (sc->dc_res == NULL) {
1994	printk("dc%d: couldn't map ports/memory\n", unit);
1995	goto fail;
1996	}
1997	sc->dc_btag = rman_get_bustag(sc->dc_res);
1998	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1999	#endif
2000
2001	/* sc->membase is the address of the card's CSRs !!! */
2002	/pcib_conf_read32(sig, DC_PCI_CFBMA, &value); /
2003	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2004	DC_PCI_CFBMA, &value);
2005	sc->membase = value;
2006
2007	/* Allocate interrupt */
2008	memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data));
2009	/pcib_conf_read32(sig, DC_PCI_CFIT, &value); /
2010	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2011	DC_PCI_CFIT, &value);
2012
2013	sc->irqInfo.name = value & 0xFF;
2014	sc->irqInfo.hdl = (rtems_irq_hdl)dc_intr;
2015	sc->irqInfo.handle = (void )sc; / new parameter */
2016	sc->irqInfo.on = nop;
2017	sc->irqInfo.off = nop;
2018	sc->irqInfo.isOn = NULL;
2019
2020	#ifdef BSP_SHARED_HANDLER_SUPPORT
2021	rc = BSP_install_rtems_shared_irq_handler( &sc->irqInfo );
2022	#else
2023	rc = BSP_install_rtems_irq_handler( &sc->irqInfo );
2024	#endif
2025	if(!rc) {
2026	rtems_panic("Can't install dec2114x irq handler.\n");
2027	}
2028
2029
2030	#if 0
2031	rid = 0;
2032	sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2033	RF_SHAREABLE \| RF_ACTIVE);
2034
2035	if (sc->dc_irq == NULL) {
2036	printk("dc%d: couldn't map interrupt\n", unit);
2037	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2038	goto fail;
2039	}
2040
2041	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
2042	dc_intr, sc, &sc->dc_intrhand);
2043
2044	if (error) {
2045	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2046	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2047	printk("dc%d: couldn't set up irq\n", unit);
2048	goto fail;
2049	}
2050	#endif
2051
2052
2053	/* Need this info to decide on a chip type.
2054	sc->dc_info = dc_devtype(dev);
2055	*/
2056	/pcib_conf_read32(sig, DC_PCI_CFRV, &revision); /
2057	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2058	DC_PCI_CFRV, &revision);
2059	revision &= 0x000000FF;
2060
2061	/* Get the eeprom width, but PNIC has diff eeprom */
2062	if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
2063	dc_eeprom_width(sc);
2064
2065	switch(sc->dc_info->dc_did) {
2066	case DC_DEVICEID_21143:
2067	sc->dc_type = DC_TYPE_21143;
2068	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2069	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2070	/* Save EEPROM contents so we can parse them later. */
2071	dc_read_srom(sc, sc->dc_romwidth);
2072	break;
2073	case DC_DEVICEID_DM9009:
2074	case DC_DEVICEID_DM9100:
2075	case DC_DEVICEID_DM9102:
2076	sc->dc_type = DC_TYPE_DM9102;
2077	sc->dc_flags \|= DC_TX_COALESCE\|DC_TX_INTR_ALWAYS;
2078	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_TX_STORENFWD;
2079	sc->dc_pmode = DC_PMODE_MII;
2080	/* Increase the latency timer value. */
2081	/pcib_conf_read32(sig, DC_PCI_CFLT, &command); /
2082	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2083	DC_PCI_CFLT, &command);
2084	command &= 0xFFFF00FF;
2085	command \|= 0x00008000;
2086	/pcib_conf_write32(sig, DC_PCI_CFLT, command); /
2087	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2088	DC_PCI_CFLT, command);
2089	break;
2090	case DC_DEVICEID_AL981:
2091	sc->dc_type = DC_TYPE_AL981;
2092	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2093	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2094	sc->dc_pmode = DC_PMODE_MII;
2095	dc_read_srom(sc, sc->dc_romwidth);
2096	break;
2097	case DC_DEVICEID_AN985:
2098	case DC_DEVICEID_EN2242:
2099	sc->dc_type = DC_TYPE_AN985;
2100	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2101	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2102	sc->dc_pmode = DC_PMODE_MII;
2103	dc_read_srom(sc, sc->dc_romwidth);
2104	break;
2105	case DC_DEVICEID_98713:
2106	case DC_DEVICEID_98713_CP:
2107	if (revision < DC_REVISION_98713A) {
2108	sc->dc_type = DC_TYPE_98713;
2109	}
2110	if (revision >= DC_REVISION_98713A) {
2111	sc->dc_type = DC_TYPE_98713A;
2112	sc->dc_flags \|= DC_21143_NWAY;
2113	}
2114	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2115	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2116	break;
2117	case DC_DEVICEID_987x5:
2118	case DC_DEVICEID_EN1217:
2119	/*
2120	* Macronix MX98715AEC-C/D/E parts have only a
2121	* 128-bit hash table. We need to deal with these
2122	* in the same manner as the PNIC II so that we
2123	* get the right number of bits out of the
2124	* CRC routine.
2125	*/
2126	if (revision >= DC_REVISION_98715AEC_C &&
2127	revision < DC_REVISION_98725)
2128	sc->dc_flags \|= DC_128BIT_HASH;
2129	sc->dc_type = DC_TYPE_987x5;
2130	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2131	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2132	break;
2133	case DC_DEVICEID_98727:
2134	sc->dc_type = DC_TYPE_987x5;
2135	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2136	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2137	break;
2138	case DC_DEVICEID_82C115:
2139	sc->dc_type = DC_TYPE_PNICII;
2140	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR\|DC_128BIT_HASH;
2141	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2142	break;
2143	case DC_DEVICEID_82C168:
2144	sc->dc_type = DC_TYPE_PNIC;
2145	sc->dc_flags \|= DC_TX_STORENFWD\|DC_TX_INTR_ALWAYS;
2146	sc->dc_flags \|= DC_PNIC_RX_BUG_WAR;
2147	sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2148	if (revision < DC_REVISION_82C169)
2149	sc->dc_pmode = DC_PMODE_SYM;
2150	break;
2151	case DC_DEVICEID_AX88140A:
2152	sc->dc_type = DC_TYPE_ASIX;
2153	sc->dc_flags \|= DC_TX_USE_TX_INTR\|DC_TX_INTR_FIRSTFRAG;
2154	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2155	sc->dc_pmode = DC_PMODE_MII;
2156	break;
2157	case DC_DEVICEID_RS7112:
2158	sc->dc_type = DC_TYPE_CONEXANT;
2159	sc->dc_flags \|= DC_TX_INTR_ALWAYS;
2160	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2161	sc->dc_pmode = DC_PMODE_MII;
2162	dc_read_srom(sc, sc->dc_romwidth);
2163	break;
2164	default:
2165	printk("dc%d: unknown device: %x\n", sc->dc_unit,
2166	sc->dc_info->dc_did);
2167	break;
2168	}
2169
2170	/* Save the cache line size. */
2171	if (DC_IS_DAVICOM(sc)) {
2172	sc->dc_cachesize = 0;
2173	}
2174	else {
2175	/pcib_conf_read32(sig, DC_PCI_CFLT, &value); /
2176	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2177	DC_PCI_CFLT, &value);
2178	sc->dc_cachesize = (u_int8_t)(value & 0xFF);
2179	}
2180
2181	/* Reset the adapter. */
2182	dc_reset(sc);
2183
2184	/* Take 21143 out of snooze mode */
2185	if (DC_IS_INTEL(sc)) {
2186	/pcib_conf_read32(sig, DC_PCI_CFDD, &command); /
2187	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2188	DC_PCI_CFDD, &command);
2189	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2190	/pcib_conf_write32(sig, DC_PCI_CFDD, command); /
2191	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2192	DC_PCI_CFDD, command);
2193	}
2194
2195
2196	/*
2197	* Try to learn something about the supported media.
2198	* We know that ASIX and ADMtek and Davicom devices
2199	* will always be using MII media, so that's a no-brainer.
2200	* The tricky ones are the Macronix/PNIC II and the
2201	* Intel 21143.
2202	*/
2203	if (DC_IS_INTEL(sc))
2204	dc_parse_21143_srom(sc);
2205	else if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
2206	if (sc->dc_type == DC_TYPE_98713)
2207	sc->dc_pmode = DC_PMODE_MII;
2208	else
2209	sc->dc_pmode = DC_PMODE_SYM;
2210	} else if (!sc->dc_pmode)
2211	sc->dc_pmode = DC_PMODE_MII;
2212
2213	/*
2214	* Get station address from the EEPROM.
2215	*/
2216	switch(sc->dc_type) {
2217	case DC_TYPE_98713:
2218	case DC_TYPE_98713A:
2219	case DC_TYPE_987x5:
2220	case DC_TYPE_PNICII:
2221	dc_read_eeprom(sc, (caddr_t)&mac_offset,
2222	(DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2223	dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2224	break;
2225	case DC_TYPE_PNIC:
2226	dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2227	break;
2228	case DC_TYPE_DM9102:
2229	case DC_TYPE_21143:
2230	case DC_TYPE_ASIX:
2231	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2232	break;
2233	case DC_TYPE_AL981:
2234	case DC_TYPE_AN985:
2235	bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2236	ETHER_ADDR_LEN);
2237	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2238	break;
2239	case DC_TYPE_CONEXANT:
2240	bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2241	break;
2242	default:
2243	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2244	break;
2245	}
2246
2247	/*
2248	* A 21143 or clone chip was detected. Inform the world.
2249	*/
2250	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2251	printk("dc%d: MAC address -- %02x:%02x:%02x:%02x:%02x:%02x\n", \
2252	sc->dc_unit,sc->arpcom.ac_enaddr[0], \
2253	sc->arpcom.ac_enaddr[1], sc->arpcom.ac_enaddr[2], \
2254	sc->arpcom.ac_enaddr[3], sc->arpcom.ac_enaddr[4], \
2255	sc->arpcom.ac_enaddr[5]);
2256
2257
2258	sc->dc_ldata = malloc(sizeof(struct dc_list_data), M_DEVBUF, M_NOWAIT);
2259
2260	if (sc->dc_ldata == NULL) {
2261	printk("dc%d: no memory for list buffers!\n", sc->dc_unit);
2262	if (sc->dc_pnic_rx_buf != NULL)
2263	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2264	#if 0
2265	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2266	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2267	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2268	#endif
2269	goto fail;
2270	}
2271
2272	bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2273
2274	ifp = &sc->arpcom.ac_if;
2275	ifp->if_softc = sc;
2276	ifp->if_unit = unitNumber; /sc->dc_unit;/
2277	ifp->if_name = unitName; /sc->dc_name;/
2278	ifp->if_mtu = ETHERMTU;
2279	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX; /* \| IFF_MULTICAST;*/
2280	ifp->if_ioctl = dc_ioctl;
2281	ifp->if_output = ether_output;
2282	ifp->if_start = dc_start;
2283	ifp->if_watchdog = dc_watchdog;
2284	ifp->if_init = dc_init;
2285	ifp->if_baudrate = 100000000;
2286	ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2287
2288	#if 0
2289	/*
2290	* Do MII setup. If this is a 21143, check for a PHY on the
2291	* MII bus after applying any necessary fixups to twiddle the
2292	* GPIO bits. If we don't end up finding a PHY, restore the
2293	* old selection (SIA only or SIA/SYM) and attach the dcphy
2294	* driver instead.
2295	*/
2296	if (DC_IS_INTEL(sc)) {
2297	dc_apply_fixup(sc, IFM_AUTO);
2298	tmp = sc->dc_pmode;
2299	sc->dc_pmode = DC_PMODE_MII;
2300	}
2301
2302	error = mii_phy_probe(dev, &sc->dc_miibus,
2303	dc_ifmedia_upd, dc_ifmedia_sts);
2304
2305	if (error && DC_IS_INTEL(sc)) {
2306	sc->dc_pmode = tmp;
2307	if (sc->dc_pmode != DC_PMODE_SIA)
2308	sc->dc_pmode = DC_PMODE_SYM;
2309	sc->dc_flags \|= DC_21143_NWAY;
2310	mii_phy_probe(dev, &sc->dc_miibus,
2311	dc_ifmedia_upd, dc_ifmedia_sts);
2312	/*
2313	* For non-MII cards, we need to have the 21143
2314	* drive the LEDs. Except there are some systems
2315	* like the NEC VersaPro NoteBook PC which have no
2316	* LEDs, and twiddling these bits has adverse effects
2317	* on them. (I.e. you suddenly can't get a link.)
2318	*/
2319	if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2320	sc->dc_flags \|= DC_TULIP_LEDS;
2321	error = 0;
2322	}
2323
2324	if (error) {
2325	printk("dc%d: MII without any PHY!\n", sc->dc_unit);
2326	contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2327	M_DEVBUF);
2328	if (sc->dc_pnic_rx_buf != NULL)
2329	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2330	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2331	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2332	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2333	error = ENXIO;
2334	goto fail;
2335	}
2336	#endif
2337
2338	/*
2339	* Call MI attach routine.
2340	*/
2341	if_attach(ifp);
2342	ether_ifattach(ifp);
2343	/callout_handle_init(&sc->dc_stat_ch);/
2344
2345	if (DC_IS_ADMTEK(sc)) {
2346	/*
2347	* Set automatic TX underrun recovery for the ADMtek chips
2348	*/
2349	DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2350	}
2351
2352	if(sc->daemontid == 0) {
2353	sc->daemontid = rtems_bsdnet_newproc("decD",4096, \
2354	dc_daemon,(void *)sc);
2355	printk("dec[%d]: daemon process started\n", sc->dc_unit);
2356	}
2357
2358	/*
2359	* Tell the upper layer(s) we support long frames.
2360	*
2361	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2362	*/
2363
2364	#ifdef SRM_MEDIA /* only defined if __alpha__ is defined... */
2365	sc->dc_srm_media = 0;
2366
2367	/* Remember the SRM console media setting */
2368	if (DC_IS_INTEL(sc)) {
2369	command = pci_read_config(dev, DC_PCI_CFDD, 4);
2370	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2371	switch ((command >> 8) & 0xff) {
2372	case 3:
2373	sc->dc_srm_media = IFM_10_T;
2374	break;
2375	case 4:
2376	sc->dc_srm_media = IFM_10_T \| IFM_FDX;
2377	break;
2378	case 5:
2379	sc->dc_srm_media = IFM_100_TX;
2380	break;
2381	case 6:
2382	sc->dc_srm_media = IFM_100_TX \| IFM_FDX;
2383	break;
2384	}
2385	if (sc->dc_srm_media)
2386	sc->dc_srm_media \|= IFM_ACTIVE \| IFM_ETHER;
2387	}
2388	#endif
2389
2390
2391	fail:
2392
2393	return (1); /(error);/
2394	}
2395
2396	#if 0
2397	static int dc_detach(dev)
2398	device_t dev;
2399	{
2400	struct dc_softc *sc;
2401	struct ifnet *ifp;
2402	int s;
2403	struct dc_mediainfo *m;
2404
2405
2406	sc = device_get_softc(dev);
2407	ifp = &sc->arpcom.ac_if;
2408
2409	dc_stop(sc);
2410	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2411
2412	bus_generic_detach(dev);
2413	device_delete_child(dev, sc->dc_miibus);
2414
2415	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2416	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2417	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2418
2419	contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2420	if (sc->dc_pnic_rx_buf != NULL)
2421	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2422
2423	while(sc->dc_mi != NULL) {
2424	m = sc->dc_mi->dc_next;
2425	free(sc->dc_mi, M_DEVBUF);
2426	sc->dc_mi = m;
2427	}
2428	free(sc->dc_srom, M_DEVBUF);
2429
2430
2431	return(0);
2432	}
2433	#endif
2434
2435
2436	/*
2437	* Initialize the transmit descriptors.
2438	*/
2439	static int dc_list_tx_init(sc)
2440	struct dc_softc *sc;
2441	{
2442	struct dc_chain_data *cd;
2443	struct dc_list_data *ld;
2444	int i;
2445
2446	cd = &sc->dc_cdata;
2447	ld = sc->dc_ldata;
2448	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2449	if (i == (DC_TX_LIST_CNT - 1)) {
2450	ld->dc_tx_list[i].dc_next =
2451	vtophys(&ld->dc_tx_list[0]);
2452	} else {
2453	ld->dc_tx_list[i].dc_next =
2454	vtophys(&ld->dc_tx_list[i + 1]);
2455	}
2456	cd->dc_tx_chain[i] = NULL;
2457	ld->dc_tx_list[i].dc_data = 0;
2458	ld->dc_tx_list[i].dc_ctl = 0;
2459	}
2460
2461	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2462
2463	return(0);
2464	}
2465
2466
2467	/*
2468	* Initialize the RX descriptors and allocate mbufs for them. Note that
2469	* we arrange the descriptors in a closed ring, so that the last descriptor
2470	* points back to the first.
2471	*/
2472	static int dc_list_rx_init(sc)
2473	struct dc_softc *sc;
2474	{
2475	struct dc_chain_data *cd;
2476	struct dc_list_data *ld;
2477	int i;
2478
2479	cd = &sc->dc_cdata;
2480	ld = sc->dc_ldata;
2481
2482	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2483	if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2484	return(ENOBUFS);
2485	if (i == (DC_RX_LIST_CNT - 1)) {
2486	ld->dc_rx_list[i].dc_next =
2487	vtophys(&ld->dc_rx_list[0]);
2488	} else {
2489	ld->dc_rx_list[i].dc_next =
2490	vtophys(&ld->dc_rx_list[i + 1]);
2491	}
2492	}
2493
2494	cd->dc_rx_prod = 0;
2495
2496	return(0);
2497	}
2498
2499	/*
2500	* Initialize an RX descriptor and attach an MBUF cluster.
2501	*/
2502	static int dc_newbuf(sc, i, m)
2503	struct dc_softc *sc;
2504	int i;
2505	struct mbuf *m;
2506	{
2507	struct mbuf *m_new = NULL;
2508	struct dc_desc *c;
2509
2510	c = &sc->dc_ldata->dc_rx_list[i];
2511
2512	if (m == NULL) {
2513	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2514	if (m_new == NULL)
2515	return(ENOBUFS);
2516
2517	MCLGET(m_new, M_DONTWAIT);
2518	if (!(m_new->m_flags & M_EXT)) {
2519	m_freem(m_new);
2520	return(ENOBUFS);
2521	}
2522	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2523	} else {
2524	m_new = m;
2525	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2526	m_new->m_data = m_new->m_ext.ext_buf;
2527	}
2528
2529	m_adj(m_new, sizeof(u_int64_t));
2530
2531	/*
2532	* If this is a PNIC chip, zero the buffer. This is part
2533	* of the workaround for the receive bug in the 82c168 and
2534	* 82c169 chips.
2535	*/
2536	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2537	bzero((char )mtod(m_new, char ), m_new->m_len);
2538
2539	sc->dc_cdata.dc_rx_chain[i] = m_new;
2540	c->dc_data = vtophys(mtod(m_new, caddr_t));
2541	c->dc_ctl = DC_RXCTL_RLINK \| DC_RXLEN;
2542	c->dc_status = DC_RXSTAT_OWN;
2543
2544	return(0);
2545	}
2546
2547	/*
2548	* Grrrrr.
2549	* The PNIC chip has a terrible bug in it that manifests itself during
2550	* periods of heavy activity. The exact mode of failure if difficult to
2551	* pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2552	* will happen on slow machines. The bug is that sometimes instead of
2553	* uploading one complete frame during reception, it uploads what looks
2554	* like the entire contents of its FIFO memory. The frame we want is at
2555	* the end of the whole mess, but we never know exactly how much data has
2556	* been uploaded, so salvaging the frame is hard.
2557	*
2558	* There is only one way to do it reliably, and it's disgusting.
2559	* Here's what we know:
2560	*
2561	* - We know there will always be somewhere between one and three extra
2562	* descriptors uploaded.
2563	*
2564	* - We know the desired received frame will always be at the end of the
2565	* total data upload.
2566	*
2567	* - We know the size of the desired received frame because it will be
2568	* provided in the length field of the status word in the last descriptor.
2569	*
2570	* Here's what we do:
2571	*
2572	* - When we allocate buffers for the receive ring, we bzero() them.
2573	* This means that we know that the buffer contents should be all
2574	* zeros, except for data uploaded by the chip.
2575	*
2576	* - We also force the PNIC chip to upload frames that include the
2577	* ethernet CRC at the end.
2578	*
2579	* - We gather all of the bogus frame data into a single buffer.
2580	*
2581	* - We then position a pointer at the end of this buffer and scan
2582	* backwards until we encounter the first non-zero byte of data.
2583	* This is the end of the received frame. We know we will encounter
2584	* some data at the end of the frame because the CRC will always be
2585	* there, so even if the sender transmits a packet of all zeros,
2586	* we won't be fooled.
2587	*
2588	* - We know the size of the actual received frame, so we subtract
2589	* that value from the current pointer location. This brings us
2590	* to the start of the actual received packet.
2591	*
2592	* - We copy this into an mbuf and pass it on, along with the actual
2593	* frame length.
2594	*
2595	* The performance hit is tremendous, but it beats dropping frames all
2596	* the time.
2597	*/
2598
2599	#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG\|DC_RXSTAT_LASTFRAG)
2600	static void dc_pnic_rx_bug_war(sc, idx)
2601	struct dc_softc *sc;
2602	int idx;
2603	{
2604	struct dc_desc *cur_rx;
2605	struct dc_desc *c = NULL;
2606	struct mbuf *m = NULL;
2607	unsigned char *ptr;
2608	int i, total_len;
2609	u_int32_t rxstat = 0;
2610
2611	i = sc->dc_pnic_rx_bug_save;
2612	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2613	ptr = sc->dc_pnic_rx_buf;
2614	bzero(ptr, sizeof(DC_RXLEN * 5));
2615
2616	/* Copy all the bytes from the bogus buffers. */
2617	while (1) {
2618	c = &sc->dc_ldata->dc_rx_list[i];
2619	rxstat = c->dc_status;
2620	m = sc->dc_cdata.dc_rx_chain[i];
2621	bcopy(mtod(m, char *), ptr, DC_RXLEN);
2622	ptr += DC_RXLEN;
2623	/* If this is the last buffer, break out. */
2624	if (i == idx \|\| rxstat & DC_RXSTAT_LASTFRAG)
2625	break;
2626	dc_newbuf(sc, i, m);
2627	DC_INC(i, DC_RX_LIST_CNT);
2628	}
2629
2630	/* Find the length of the actual receive frame. */
2631	total_len = DC_RXBYTES(rxstat);
2632
2633	/* Scan backwards until we hit a non-zero byte. */
2634	while(*ptr == 0x00)
2635	ptr--;
2636	#if 0
2637	/* Round off. */
2638	if ((uintptr_t)(ptr) & 0x3)
2639	ptr -= 1;
2640	#endif
2641
2642	/* Now find the start of the frame. */
2643	ptr -= total_len;
2644	if (ptr < sc->dc_pnic_rx_buf)
2645	ptr = sc->dc_pnic_rx_buf;
2646
2647	/*
2648	* Now copy the salvaged frame to the last mbuf and fake up
2649	* the status word to make it look like a successful
2650	* frame reception.
2651	*/
2652	dc_newbuf(sc, i, m);
2653	bcopy(ptr, mtod(m, char *), total_len);
2654	cur_rx->dc_status = rxstat \| DC_RXSTAT_FIRSTFRAG;
2655
2656	return;
2657	}
2658
2659	/*
2660	* This routine searches the RX ring for dirty descriptors in the
2661	* event that the rxeof routine falls out of sync with the chip's
2662	* current descriptor pointer. This may happen sometimes as a result
2663	* of a "no RX buffer available" condition that happens when the chip
2664	* consumes all of the RX buffers before the driver has a chance to
2665	* process the RX ring. This routine may need to be called more than
2666	* once to bring the driver back in sync with the chip, however we
2667	* should still be getting RX DONE interrupts to drive the search
2668	* for new packets in the RX ring, so we should catch up eventually.
2669	*/
2670	static int dc_rx_resync(sc)
2671	struct dc_softc *sc;
2672	{
2673	int i, pos;
2674	struct dc_desc *cur_rx;
2675
2676	pos = sc->dc_cdata.dc_rx_prod;
2677
2678	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2679	cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2680	if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2681	break;
2682	DC_INC(pos, DC_RX_LIST_CNT);
2683	}
2684
2685	/* If the ring really is empty, then just return. */
2686	if (i == DC_RX_LIST_CNT)
2687	return(0);
2688
2689	/* We've fallen behing the chip: catch it. */
2690	sc->dc_cdata.dc_rx_prod = pos;
2691
2692	return(EAGAIN);
2693	}
2694
2695	/*
2696	* A frame has been uploaded: pass the resulting mbuf chain up to
2697	* the higher level protocols.
2698	*/
2699	static void dc_rxeof(sc)
2700	struct dc_softc *sc;
2701	{
2702	struct ether_header *eh;
2703	struct mbuf *m;
2704	struct ifnet *ifp;
2705	struct dc_desc *cur_rx;
2706	int i, total_len = 0;
2707	u_int32_t rxstat;
2708
2709	ifp = &sc->arpcom.ac_if;
2710	i = sc->dc_cdata.dc_rx_prod;
2711
2712	while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2713
2714	#ifdef DEVICE_POLLING
2715	if (ifp->if_ipending & IFF_POLLING) {
2716	if (sc->rxcycles <= 0)
2717	break;
2718	sc->rxcycles--;
2719	}
2720	#endif /* DEVICE_POLLING */
2721	cur_rx = &sc->dc_ldata->dc_rx_list[i];
2722	rxstat = cur_rx->dc_status;
2723	m = sc->dc_cdata.dc_rx_chain[i];
2724	total_len = DC_RXBYTES(rxstat);
2725
2726	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2727	if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2728	if (rxstat & DC_RXSTAT_FIRSTFRAG)
2729	sc->dc_pnic_rx_bug_save = i;
2730	if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2731	DC_INC(i, DC_RX_LIST_CNT);
2732	continue;
2733	}
2734	dc_pnic_rx_bug_war(sc, i);
2735	rxstat = cur_rx->dc_status;
2736	total_len = DC_RXBYTES(rxstat);
2737	}
2738	}
2739
2740	sc->dc_cdata.dc_rx_chain[i] = NULL;
2741
2742	/*
2743	* If an error occurs, update stats, clear the
2744	* status word and leave the mbuf cluster in place:
2745	* it should simply get re-used next time this descriptor
2746	* comes up in the ring. However, don't report long
2747	* frames as errors since they could be vlans
2748	*/
2749	if ((rxstat & DC_RXSTAT_RXERR)){
2750	if (!(rxstat & DC_RXSTAT_GIANT) \|\|
2751	(rxstat & (DC_RXSTAT_CRCERR \| DC_RXSTAT_DRIBBLE \|
2752	DC_RXSTAT_MIIERE \| DC_RXSTAT_COLLSEEN \|
2753	DC_RXSTAT_RUNT \| DC_RXSTAT_DE))) {
2754	ifp->if_ierrors++;
2755	if (rxstat & DC_RXSTAT_COLLSEEN)
2756	ifp->if_collisions++;
2757	dc_newbuf(sc, i, m);
2758	if (rxstat & DC_RXSTAT_CRCERR) {
2759	DC_INC(i, DC_RX_LIST_CNT);
2760	continue;
2761	} else {
2762	dc_init(sc);
2763	return;
2764	}
2765	}
2766	}
2767
2768	/* No errors; receive the packet. */
2769	total_len -= ETHER_CRC_LEN;
2770
2771	#ifdef __i386__
2772	/*
2773	* On the x86 we do not have alignment problems, so try to
2774	* allocate a new buffer for the receive ring, and pass up
2775	* the one where the packet is already, saving the expensive
2776	* copy done in m_devget().
2777	* If we are on an architecture with alignment problems, or
2778	* if the allocation fails, then use m_devget and leave the
2779	* existing buffer in the receive ring.
2780	*/
2781	if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2782	m->m_pkthdr.rcvif = ifp;
2783	m->m_pkthdr.len = m->m_len = total_len;
2784	DC_INC(i, DC_RX_LIST_CNT);
2785	} else
2786	#endif
2787	{
2788	struct mbuf *m0;
2789
2790	m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2791	total_len + ETHER_ALIGN, 0, ifp, NULL);
2792	dc_newbuf(sc, i, m);
2793	DC_INC(i, DC_RX_LIST_CNT);
2794	if (m0 == NULL) {
2795	ifp->if_ierrors++;
2796	continue;
2797	}
2798	m_adj(m0, ETHER_ALIGN);
2799	m = m0;
2800	}
2801
2802	ifp->if_ipackets++;
2803	eh = mtod(m, struct ether_header *);
2804
2805	/* Remove header from mbuf and pass it on. */
2806	m_adj(m, sizeof(struct ether_header));
2807	ether_input(ifp, eh, m);
2808	}
2809
2810	sc->dc_cdata.dc_rx_prod = i;
2811	}
2812
2813	/*
2814	* A frame was downloaded to the chip. It's safe for us to clean up
2815	* the list buffers.
2816	*/
2817
2818	static void
2819	dc_txeof(sc)
2820	struct dc_softc *sc;
2821	{
2822	struct dc_desc *cur_tx = NULL;
2823	struct ifnet *ifp;
2824	int idx;
2825
2826	ifp = &sc->arpcom.ac_if;
2827
2828	/*
2829	* Go through our tx list and free mbufs for those
2830	* frames that have been transmitted.
2831	*/
2832	idx = sc->dc_cdata.dc_tx_cons;
2833	while(idx != sc->dc_cdata.dc_tx_prod) {
2834	u_int32_t txstat;
2835
2836	cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2837	txstat = cur_tx->dc_status;
2838
2839	if (txstat & DC_TXSTAT_OWN)
2840	break;
2841
2842	if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) \|\|
2843	cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2844	if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2845	/*
2846	* Yes, the PNIC is so brain damaged
2847	* that it will sometimes generate a TX
2848	* underrun error while DMAing the RX
2849	* filter setup frame. If we detect this,
2850	* we have to send the setup frame again,
2851	* or else the filter won't be programmed
2852	* correctly.
2853	*/
2854	if (DC_IS_PNIC(sc)) {
2855	if (txstat & DC_TXSTAT_ERRSUM)
2856	dc_setfilt(sc);
2857	}
2858	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2859	}
2860	sc->dc_cdata.dc_tx_cnt--;
2861	DC_INC(idx, DC_TX_LIST_CNT);
2862	continue;
2863	}
2864
2865	if (DC_IS_CONEXANT(sc)) {
2866	/*
2867	* For some reason Conexant chips like
2868	* setting the CARRLOST flag even when
2869	* the carrier is there. In CURRENT we
2870	* have the same problem for Xircom
2871	* cards !
2872	*/
2873	if (/sc->dc_type == DC_TYPE_21143 &&/
2874	sc->dc_pmode == DC_PMODE_MII &&
2875	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2876	DC_TXSTAT_NOCARRIER)))
2877	txstat &= ~DC_TXSTAT_ERRSUM;
2878	} else {
2879	if (/sc->dc_type == DC_TYPE_21143 &&/
2880	sc->dc_pmode == DC_PMODE_MII &&
2881	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2882	DC_TXSTAT_NOCARRIER\|DC_TXSTAT_CARRLOST)))
2883	txstat &= ~DC_TXSTAT_ERRSUM;
2884	}
2885
2886	if (txstat & DC_TXSTAT_ERRSUM) {
2887	ifp->if_oerrors++;
2888	if (txstat & DC_TXSTAT_EXCESSCOLL)
2889	ifp->if_collisions++;
2890	if (txstat & DC_TXSTAT_LATECOLL)
2891	ifp->if_collisions++;
2892	if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2893	dc_init(sc);
2894	return;
2895	}
2896	}
2897
2898	ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2899
2900	ifp->if_opackets++;
2901	if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2902	m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2903	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2904	}
2905
2906	sc->dc_cdata.dc_tx_cnt--;
2907	DC_INC(idx, DC_TX_LIST_CNT);
2908	}
2909
2910	if (idx != sc->dc_cdata.dc_tx_cons) {
2911	/* some buffers have been freed */
2912	sc->dc_cdata.dc_tx_cons = idx;
2913	ifp->if_flags &= ~IFF_OACTIVE;
2914	}
2915	ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2916
2917	return;
2918	}
2919
2920
2921	#if 0
2922	static void dc_tick(xsc)
2923	void *xsc;
2924	{
2925	struct dc_softc *sc;
2926	/struct mii_data mii;*/
2927	struct ifnet *ifp;
2928	int s;
2929	u_int32_t r;
2930
2931
2932	sc = xsc;
2933	ifp = &sc->arpcom.ac_if;
2934	mii = device_get_softc(sc->dc_miibus);
2935
2936	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2937	if (sc->dc_flags & DC_21143_NWAY) {
2938	r = CSR_READ_4(sc, DC_10BTSTAT);
2939	if (IFM_SUBTYPE(mii->mii_media_active) ==
2940	IFM_100_TX && (r & DC_TSTAT_LS100)) {
2941	sc->dc_link = 0;
2942	mii_mediachg(mii);
2943	}
2944	if (IFM_SUBTYPE(mii->mii_media_active) ==
2945	IFM_10_T && (r & DC_TSTAT_LS10)) {
2946	sc->dc_link = 0;
2947	mii_mediachg(mii);
2948	}
2949	if (sc->dc_link == 0)
2950	mii_tick(mii);
2951	} else {
2952	r = CSR_READ_4(sc, DC_ISR);
2953	if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2954	sc->dc_cdata.dc_tx_cnt == 0)
2955	mii_tick(mii);
2956	if (!(mii->mii_media_status & IFM_ACTIVE))
2957	sc->dc_link = 0;
2958	}
2959	} else
2960	mii_tick(mii);
2961
2962	/*
2963	* When the init routine completes, we expect to be able to send
2964	* packets right away, and in fact the network code will send a
2965	* gratuitous ARP the moment the init routine marks the interface
2966	* as running. However, even though the MAC may have been initialized,
2967	* there may be a delay of a few seconds before the PHY completes
2968	* autonegotiation and the link is brought up. Any transmissions
2969	* made during that delay will be lost. Dealing with this is tricky:
2970	* we can't just pause in the init routine while waiting for the
2971	* PHY to come ready since that would bring the whole system to
2972	* a screeching halt for several seconds.
2973	*
2974	* What we do here is prevent the TX start routine from sending
2975	* any packets until a link has been established. After the
2976	* interface has been initialized, the tick routine will poll
2977	* the state of the PHY until the IFM_ACTIVE flag is set. Until
2978	* that time, packets will stay in the send queue, and once the
2979	* link comes up, they will be flushed out to the wire.
2980	*/
2981	if (!sc->dc_link) {
2982	mii_pollstat(mii);
2983	if (mii->mii_media_status & IFM_ACTIVE &&
2984	IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2985	sc->dc_link++;
2986	if (ifp->if_snd.ifq_head != NULL)
2987	dc_start(ifp);
2988	}
2989	}
2990
2991	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2992	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
2993	else
2994	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
2995
2996	return;
2997	}
2998	#endif
2999
3000	/*
3001	* A transmit underrun has occurred. Back off the transmit threshold,
3002	* or switch to store and forward mode if we have to.
3003	*/
3004	static void dc_tx_underrun(sc)
3005	struct dc_softc *sc;
3006	{
3007	u_int32_t isr;
3008	int i;
3009
3010	if (DC_IS_DAVICOM(sc))
3011	dc_init(sc);
3012
3013	if (DC_IS_INTEL(sc)) {
3014	/*
3015	* The real 21143 requires that the transmitter be idle
3016	* in order to change the transmit threshold or store
3017	* and forward state.
3018	*/
3019	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3020
3021	for (i = 0; i < DC_TIMEOUT; i++) {
3022	isr = CSR_READ_4(sc, DC_ISR);
3023	if (isr & DC_ISR_TX_IDLE)
3024	break;
3025	DELAY(10);
3026	}
3027	if (i == DC_TIMEOUT) {
3028	printk("dc%d: failed to force tx to idle state\n",
3029	sc->dc_unit);
3030	dc_init(sc);
3031	}
3032	}
3033
3034	printk("dc%d: TX underrun -- ", sc->dc_unit);
3035	sc->dc_txthresh += DC_TXTHRESH_INC;
3036	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3037	printk("using store and forward mode\n");
3038	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3039	} else {
3040	printk("increasing TX threshold\n");
3041	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3042	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3043	}
3044
3045	if (DC_IS_INTEL(sc))
3046	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3047
3048	return;
3049	}
3050
3051	#ifdef DEVICE_POLLING
3052	static poll_handler_t dc_poll;
3053
3054	static void
3055	dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3056	{
3057	struct dc_softc *sc = ifp->if_softc;
3058
3059	if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3060	/* Re-enable interrupts. */
3061	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3062	return;
3063	}
3064	sc->rxcycles = count;
3065	dc_rxeof(sc);
3066	dc_txeof(sc);
3067	if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
3068	dc_start(ifp);
3069
3070	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3071	u_int32_t status;
3072
3073	status = CSR_READ_4(sc, DC_ISR);
3074	status &= (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF\|
3075	DC_ISR_TX_NOBUF\|DC_ISR_TX_IDLE\|DC_ISR_TX_UNDERRUN\|
3076	DC_ISR_BUS_ERR);
3077	if (!status)
3078	return ;
3079	/* ack what we have */
3080	CSR_WRITE_4(sc, DC_ISR, status);
3081
3082	if (status & (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF) ) {
3083	u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3084	ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3085
3086	if (dc_rx_resync(sc))
3087	dc_rxeof(sc);
3088	}
3089	/* restart transmit unit if necessary */
3090	if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3091	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3092
3093	if (status & DC_ISR_TX_UNDERRUN)
3094	dc_tx_underrun(sc);
3095
3096	if (status & DC_ISR_BUS_ERR) {
3097	printk("dc_poll: dc%d bus error\n", sc->dc_unit);
3098	dc_reset(sc);
3099	dc_init(sc);
3100	}
3101	}
3102	}
3103	#endif /* DEVICE_POLLING */
3104
3105	static void
3106	dc_intr(void* arg)
3107	{
3108	/* Need to make this work for multiple devices ... eventually */
3109	struct dc_softc sc = (struct dc_softc )arg;
3110
3111
3112	/* Disable interrupts. */
3113	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3114
3115	rtems_bsdnet_event_send(sc->daemontid, IRQ_EVENT);
3116	#if 0
3117	if (sc->suspended) {
3118	return;
3119	}
3120
3121	ifp = &sc->arpcom.ac_if;
3122
3123	#ifdef DEVICE_POLLING
3124	if (ifp->if_ipending & IFF_POLLING)
3125	return;
3126	if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3127	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3128	return;
3129	}
3130	#endif /* DEVICE_POLLING */
3131	if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3132	return ;
3133
3134	/* Suppress unwanted interrupts */
3135	if (!(ifp->if_flags & IFF_UP)) {
3136	if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3137	dc_stop(sc);
3138	return;
3139	}
3140	#endif
3141	}
3142
3143
3144	static void
3145	dc_daemon(void * arg)
3146	{
3147	struct dc_softc sc = (struct dc_softc )arg;
3148	struct ifnet *ifp;
3149	u_int32_t status;
3150	rtems_event_set events;
3151
3152
3153	for(;;) {
3154	rtems_bsdnet_event_receive(RTEMS_ALL_EVENTS, \
3155	RTEMS_WAIT \| RTEMS_EVENT_ANY, \
3156	RTEMS_NO_TIMEOUT,
3157	&events);
3158
3159
3160	ifp = &sc->arpcom.ac_if;
3161
3162	while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
3163
3164	CSR_WRITE_4(sc, DC_ISR, status);
3165
3166	if (status & DC_ISR_RX_OK) {
3167	int curpkts;
3168	curpkts = ifp->if_ipackets;
3169	dc_rxeof(sc);
3170	if (curpkts == ifp->if_ipackets) {
3171	while(dc_rx_resync(sc))
3172	dc_rxeof(sc);
3173	}
3174	}
3175
3176	if (status & (DC_ISR_TX_OK\|DC_ISR_TX_NOBUF))
3177	dc_txeof(sc);
3178
3179	if (status & DC_ISR_TX_IDLE) {
3180	dc_txeof(sc);
3181	if (sc->dc_cdata.dc_tx_cnt) {
3182	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3183	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3184	}
3185	}
3186
3187	if (status & DC_ISR_TX_UNDERRUN)
3188	dc_tx_underrun(sc);
3189
3190	if ((status & DC_ISR_RX_WATDOGTIMEO)
3191	\|\| (status & DC_ISR_RX_NOBUF)) {
3192	int curpkts;
3193	curpkts = ifp->if_ipackets;
3194	dc_rxeof(sc);
3195	if (curpkts == ifp->if_ipackets) {
3196	while(dc_rx_resync(sc))
3197	dc_rxeof(sc);
3198	}
3199	}
3200
3201	if (status & DC_ISR_BUS_ERR) {
3202	dc_reset(sc);
3203	dc_init(sc);
3204	}
3205	}
3206
3207	/* Make atomic !!! */
3208	/* Re-enable interrupts. */
3209	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3210
3211	if (ifp->if_snd.ifq_head != NULL)
3212	dc_start(ifp);
3213	}
3214
3215	}
3216
3217
3218	/*
3219	* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3220	* pointers to the fragment pointers.
3221	*/
3222	static int dc_encap(sc, m_head, txidx)
3223	struct dc_softc *sc;
3224	struct mbuf *m_head;
3225	u_int32_t *txidx;
3226	{
3227	struct dc_desc *f = NULL;
3228	struct mbuf *m;
3229	int frag, cur, cnt = 0;
3230
3231	/*
3232	* Start packing the mbufs in this chain into
3233	* the fragment pointers. Stop when we run out
3234	* of fragments or hit the end of the mbuf chain.
3235	*/
3236	m = m_head;
3237	cur = frag = *txidx;
3238
3239	for (m = m_head; m != NULL; m = m->m_next) {
3240	if (m->m_len != 0) {
3241	if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3242	if (*txidx != sc->dc_cdata.dc_tx_prod &&
3243	frag == (DC_TX_LIST_CNT - 1))
3244	return(ENOBUFS);
3245	}
3246	if ((DC_TX_LIST_CNT -
3247	(sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3248	return(ENOBUFS);
3249
3250	f = &sc->dc_ldata->dc_tx_list[frag];
3251	f->dc_ctl = DC_TXCTL_TLINK \| m->m_len;
3252	if (cnt == 0) {
3253	f->dc_status = 0;
3254	f->dc_ctl \|= DC_TXCTL_FIRSTFRAG;
3255	} else
3256	f->dc_status = DC_TXSTAT_OWN;
3257	f->dc_data = vtophys(mtod(m, vm_offset_t));
3258	cur = frag;
3259	DC_INC(frag, DC_TX_LIST_CNT);
3260	cnt++;
3261	}
3262	}
3263
3264	if (m != NULL)
3265	return(ENOBUFS);
3266
3267	sc->dc_cdata.dc_tx_cnt += cnt;
3268	sc->dc_cdata.dc_tx_chain[cur] = m_head;
3269	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_LASTFRAG;
3270	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3271	sc->dc_ldata->dc_tx_list[*txidx].dc_ctl \|= DC_TXCTL_FINT;
3272	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3273	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3274	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3275	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3276	sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3277	*txidx = frag;
3278
3279	return(0);
3280	}
3281
3282	/*
3283	* Coalesce an mbuf chain into a single mbuf cluster buffer.
3284	* Needed for some really badly behaved chips that just can't
3285	* do scatter/gather correctly.
3286	*/
3287	static int dc_coal(sc, m_head)
3288	struct dc_softc *sc;
3289	struct mbuf **m_head;
3290	{
3291	struct mbuf m_new, m;
3292
3293	m = *m_head;
3294	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3295	if (m_new == NULL)
3296	return(ENOBUFS);
3297	if (m->m_pkthdr.len > MHLEN) {
3298	MCLGET(m_new, M_DONTWAIT);
3299	if (!(m_new->m_flags & M_EXT)) {
3300	m_freem(m_new);
3301	return(ENOBUFS);
3302	}
3303	}
3304	m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3305	m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3306	m_freem(m);
3307	*m_head = m_new;
3308
3309	return(0);
3310	}
3311
3312	/*
3313	* Main transmit routine. To avoid having to do mbuf copies, we put pointers
3314	* to the mbuf data regions directly in the transmit lists. We also save a
3315	* copy of the pointers since the transmit list fragment pointers are
3316	* physical addresses.
3317	*/
3318
3319	static void dc_start(ifp)
3320	struct ifnet *ifp;
3321	{
3322	struct dc_softc *sc;
3323	struct mbuf *m_head = NULL;
3324	u_int32_t idx;
3325
3326	sc = ifp->if_softc;
3327	#if 0
3328	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3329	return;
3330	#endif
3331	if (ifp->if_flags & IFF_OACTIVE)
3332	return;
3333
3334	idx = sc->dc_cdata.dc_tx_prod;
3335
3336	while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3337	IF_DEQUEUE(&ifp->if_snd, m_head);
3338	if (m_head == NULL)
3339	break;
3340
3341	if (sc->dc_flags & DC_TX_COALESCE &&
3342	m_head->m_next != NULL) {
3343	/* only coalesce if have >1 mbufs */
3344	if (dc_coal(sc, &m_head)) {
3345	IF_PREPEND(&ifp->if_snd, m_head);
3346	ifp->if_flags \|= IFF_OACTIVE;
3347	break;
3348	}
3349	}
3350
3351	if (dc_encap(sc, m_head, &idx)) {
3352	IF_PREPEND(&ifp->if_snd, m_head);
3353	ifp->if_flags \|= IFF_OACTIVE;
3354	break;
3355	}
3356	#if 0
3357	/*
3358	* If there's a BPF listener, bounce a copy of this frame
3359	* to him.
3360	*/
3361	if (ifp->if_bpf)
3362	bpf_mtap(ifp, m_head);
3363	#endif
3364	if (sc->dc_flags & DC_TX_ONE) {
3365	ifp->if_flags \|= IFF_OACTIVE;
3366	break;
3367	}
3368	}
3369
3370	/* Transmit */
3371	sc->dc_cdata.dc_tx_prod = idx;
3372	if (!(sc->dc_flags & DC_TX_POLL))
3373	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3374
3375	/*
3376	* Set a timeout in case the chip goes out to lunch.
3377	*/
3378	ifp->if_timer = 5;
3379
3380	return;
3381	}
3382
3383	static void dc_init(xsc)
3384	void *xsc;
3385	{
3386	struct dc_softc *sc = xsc;
3387	struct ifnet *ifp = &sc->arpcom.ac_if;
3388	/struct mii_data mii;*/
3389
3390
3391	/mii = device_get_softc(sc->dc_miibus);/
3392
3393	/*
3394	* Cancel pending I/O and free all RX/TX buffers.
3395	*/
3396	dc_stop(sc);
3397	dc_reset(sc);
3398
3399	/*
3400	* Set cache alignment and burst length.
3401	*/
3402	if (DC_IS_ASIX(sc) \|\| DC_IS_DAVICOM(sc))
3403	CSR_WRITE_4(sc, DC_BUSCTL, 0);
3404	else
3405	CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME\|DC_BUSCTL_MRLE);
3406	/*
3407	* Evenly share the bus between receive and transmit process.
3408	*/
3409	if (DC_IS_INTEL(sc))
3410	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3411	if (DC_IS_DAVICOM(sc) \|\| DC_IS_INTEL(sc)) {
3412	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3413	} else {
3414	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3415	}
3416	if (sc->dc_flags & DC_TX_POLL)
3417	DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3418	switch(sc->dc_cachesize) {
3419	case 32:
3420	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3421	break;
3422	case 16:
3423	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3424	break;
3425	case 8:
3426	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3427	break;
3428	case 0:
3429	default:
3430	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3431	break;
3432	}
3433
3434	if (sc->dc_flags & DC_TX_STORENFWD)
3435	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3436	else {
3437	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3438	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3439	} else {
3440	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3441	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3442	}
3443	}
3444
3445	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3446	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3447
3448	if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
3449	/*
3450	* The app notes for the 98713 and 98715A say that
3451	* in order to have the chips operate properly, a magic
3452	* number must be written to CSR16. Macronix does not
3453	* document the meaning of these bits so there's no way
3454	* to know exactly what they do. The 98713 has a magic
3455	* number all its own; the rest all use a different one.
3456	*/
3457	DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3458	if (sc->dc_type == DC_TYPE_98713)
3459	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3460	else
3461	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3462	}
3463
3464	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3465	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3466
3467	/* Init circular RX list. */
3468	if (dc_list_rx_init(sc) == ENOBUFS) {
3469	printk("dc%d: initialization failed: no "
3470	"memory for rx buffers\n", sc->dc_unit);
3471	dc_stop(sc);
3472	return;
3473	}
3474
3475	/*
3476	* Init tx descriptors.
3477	*/
3478	dc_list_tx_init(sc);
3479
3480	/*
3481	* Load the address of the RX list.
3482	*/
3483	CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3484	CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3485
3486	/*
3487	* Enable interrupts.
3488	*/
3489	#ifdef DEVICE_POLLING
3490	/*
3491	* ... but only if we are not polling, and make sure they are off in
3492	* the case of polling. Some cards (e.g. fxp) turn interrupts on
3493	* after a reset.
3494	*/
3495	if (ifp->if_ipending & IFF_POLLING)
3496	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3497	else
3498	#endif
3499	/* Enable interrupts */
3500	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3501	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3502
3503	/* Enable transmitter. */
3504	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3505
3506	/*
3507	* If this is an Intel 21143 and we're not using the
3508	* MII port, program the LED control pins so we get
3509	* link and activity indications.
3510	*/
3511	if (sc->dc_flags & DC_TULIP_LEDS) {
3512	CSR_WRITE_4(sc, DC_WATCHDOG,
3513	DC_WDOG_CTLWREN\|DC_WDOG_LINK\|DC_WDOG_ACTIVITY);
3514	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3515	}
3516
3517	/*
3518	* Load the RX/multicast filter. We do this sort of late
3519	* because the filter programming scheme on the 21143 and
3520	* some clones requires DMAing a setup frame via the TX
3521	* engine, and we need the transmitter enabled for that.
3522	*/
3523	dc_setfilt(sc);
3524
3525	/* Enable receiver. */
3526	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3527	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3528
3529	/mii_mediachg(mii);/
3530	dc_setcfg(sc, sc->dc_if_media);
3531
3532	ifp->if_flags \|= IFF_RUNNING;
3533	ifp->if_flags &= ~IFF_OACTIVE;
3534
3535
3536	#if 0
3537
3538	/* Don't start the ticker if this is a homePNA link. */
3539	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3540	sc->dc_link = 1;
3541	else {
3542	if (sc->dc_flags & DC_21143_NWAY)
3543	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3544	else
3545	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3546	}
3547
3548	#ifdef SRM_MEDIA
3549	if(sc->dc_srm_media) {
3550	struct ifreq ifr;
3551
3552	ifr.ifr_media = sc->dc_srm_media;
3553	ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3554	sc->dc_srm_media = 0;
3555	}
3556	#endif
3557	#endif /* end if (0) */
3558	return;
3559	}
3560
3561
3562	#if 0
3563	/*
3564	* Set media options.
3565	*/
3566	static int dc_ifmedia_upd(ifp)
3567	struct ifnet *ifp;
3568	{
3569	struct dc_softc *sc;
3570	struct mii_data *mii;
3571	struct ifmedia *ifm;
3572
3573	sc = ifp->if_softc;
3574	mii = device_get_softc(sc->dc_miibus);
3575	mii_mediachg(mii);
3576	ifm = &mii->mii_media;
3577
3578	if (DC_IS_DAVICOM(sc) &&
3579	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3580	dc_setcfg(sc, ifm->ifm_media);
3581	else
3582	sc->dc_link = 0;
3583
3584	return(0);
3585	}
3586
3587	/*
3588	* Report current media status.
3589	*/
3590	static void dc_ifmedia_sts(ifp, ifmr)
3591	struct ifnet *ifp;
3592	struct ifmediareq *ifmr;
3593	{
3594	struct dc_softc *sc;
3595	struct mii_data *mii;
3596	struct ifmedia *ifm;
3597
3598	sc = ifp->if_softc;
3599	mii = device_get_softc(sc->dc_miibus);
3600	mii_pollstat(mii);
3601	ifm = &mii->mii_media;
3602	if (DC_IS_DAVICOM(sc)) {
3603	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3604	ifmr->ifm_active = ifm->ifm_media;
3605	ifmr->ifm_status = 0;
3606	return;
3607	}
3608	}
3609	ifmr->ifm_active = mii->mii_media_active;
3610	ifmr->ifm_status = mii->mii_media_status;
3611
3612	return;
3613	}
3614	#endif
3615
3616
3617	static int dc_ioctl(ifp, command, data)
3618	struct ifnet *ifp;
3619	ioctl_command_t command;
3620	caddr_t data;
3621	{
3622	struct dc_softc *sc = ifp->if_softc;
3623	/struct ifreq ifr = (struct ifreq *) data;
3624	struct mii_data mii;/
3625	int error = 0;
3626
3627
3628	switch(command) {
3629	case SIOCSIFADDR:
3630	case SIOCGIFADDR:
3631	case SIOCSIFMTU:
3632	error = ether_ioctl(ifp, command, data);
3633	break;
3634	case SIOCSIFFLAGS:
3635	if (ifp->if_flags & IFF_UP) {
3636	int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3637	(IFF_PROMISC \| IFF_ALLMULTI);
3638	if (ifp->if_flags & IFF_RUNNING) {
3639	if (need_setfilt)
3640	dc_setfilt(sc);
3641	} else {
3642	sc->dc_txthresh = 0;
3643	dc_init(sc);
3644	}
3645	} else {
3646	if (ifp->if_flags & IFF_RUNNING)
3647	dc_stop(sc);
3648	}
3649	sc->dc_if_flags = ifp->if_flags;
3650	error = 0;
3651	break;
3652	case SIOCADDMULTI:
3653	case SIOCDELMULTI:
3654	dc_setfilt(sc);
3655	error = 0;
3656	break;
3657	#if 0
3658	case SIOCGIFMEDIA:
3659	case SIOCSIFMEDIA:
3660	mii = device_get_softc(sc->dc_miibus);
3661	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3662	#ifdef SRM_MEDIA
3663	if (sc->dc_srm_media)
3664	sc->dc_srm_media = 0;
3665	#endif
3666	break;
3667	#endif
3668	default:
3669	error = EINVAL;
3670	break;
3671	}
3672
3673
3674	return(error);
3675	}
3676
3677	static void dc_watchdog(ifp)
3678	struct ifnet *ifp;
3679	{
3680	struct dc_softc *sc;
3681
3682	sc = ifp->if_softc;
3683
3684	ifp->if_oerrors++;
3685	printk("dc%d: watchdog timeout\n", sc->dc_unit);
3686
3687	dc_stop(sc);
3688	dc_reset(sc);
3689	dc_init(sc);
3690
3691	if (ifp->if_snd.ifq_head != NULL)
3692	dc_start(ifp);
3693
3694	return;
3695	}
3696
3697	/*
3698	* Stop the adapter and free any mbufs allocated to the
3699	* RX and TX lists.
3700	*/
3701	static void dc_stop(sc)
3702	struct dc_softc *sc;
3703	{
3704	register int i;
3705	struct ifnet *ifp;
3706
3707	ifp = &sc->arpcom.ac_if;
3708	ifp->if_timer = 0;
3709
3710	/untimeout(dc_tick, sc, sc->dc_stat_ch);/
3711
3712	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
3713	#ifdef DEVICE_POLLING
3714	ether_poll_deregister(ifp);
3715	#endif
3716
3717	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON\|DC_NETCFG_TX_ON));
3718	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3719	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3720	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3721	sc->dc_link = 0;
3722
3723	/*
3724	* Free data in the RX lists.
3725	*/
3726	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3727	if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3728	m_freem(sc->dc_cdata.dc_rx_chain[i]);
3729	sc->dc_cdata.dc_rx_chain[i] = NULL;
3730	}
3731	}
3732	bzero((char *)&sc->dc_ldata->dc_rx_list,
3733	sizeof(sc->dc_ldata->dc_rx_list));
3734
3735	/*
3736	* Free the TX list buffers.
3737	*/
3738	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3739	if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3740	if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3741	DC_TXCTL_SETUP) {
3742	sc->dc_cdata.dc_tx_chain[i] = NULL;
3743	continue;
3744	}
3745	m_freem(sc->dc_cdata.dc_tx_chain[i]);
3746	sc->dc_cdata.dc_tx_chain[i] = NULL;
3747	}
3748	}
3749
3750	bzero((char *)&sc->dc_ldata->dc_tx_list,
3751	sizeof(sc->dc_ldata->dc_tx_list));
3752
3753	return;
3754	}
3755
3756
3757	#if 0
3758	/*
3759	* Stop all chip I/O so that the kernel's probe routines don't
3760	* get confused by errant DMAs when rebooting.
3761	*/
3762	static void dc_shutdown(dev)
3763	device_t dev;
3764	{
3765	struct dc_softc *sc;
3766
3767	sc = device_get_softc(dev);
3768
3769	dc_stop(sc);
3770
3771	return;
3772	}
3773
3774	/*
3775	* Device suspend routine. Stop the interface and save some PCI
3776	* settings in case the BIOS doesn't restore them properly on
3777	* resume.
3778	*/
3779	static int dc_suspend(dev)
3780	device_t dev;
3781	{
3782	register int i;
3783	int s;
3784	struct dc_softc *sc;
3785
3786
3787	sc = device_get_softc(dev);
3788
3789	dc_stop(sc);
3790
3791	for (i = 0; i < 5; i++)
3792	sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3793	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3794	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3795	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3796	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3797
3798	sc->suspended = 1;
3799
3800	return (0);
3801	}
3802
3803	/*
3804	* Device resume routine. Restore some PCI settings in case the BIOS
3805	* doesn't, re-enable busmastering, and restart the interface if
3806	* appropriate.
3807	*/
3808	static int dc_resume(dev)
3809	device_t dev;
3810	{
3811	register int i;
3812	int s;
3813	struct dc_softc *sc;
3814	struct ifnet *ifp;
3815
3816
3817	sc = device_get_softc(dev);
3818	ifp = &sc->arpcom.ac_if;
3819
3820	dc_acpi(dev);
3821
3822	/* better way to do this? */
3823	for (i = 0; i < 5; i++)
3824	pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3825	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3826	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3827	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3828	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3829
3830	/* reenable busmastering */
3831	pci_enable_busmaster(dev);
3832	pci_enable_io(dev, DC_RES);
3833
3834	/* reinitialize interface if necessary */
3835	if (ifp->if_flags & IFF_UP)
3836	dc_init(sc);
3837
3838	sc->suspended = 0;
3839
3840	return (0);
3841	}
3842	#endif
3843
3844	#endif /* end if supported */

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