1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* This file contains the driver for the GRLIB GPTIMER timers port. The driver |
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4 | * is implemented by using the tlib.c simple timer layer and the Driver |
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5 | * Manager. |
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6 | * |
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7 | * The Driver can be configured using driver resources: |
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8 | * |
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9 | * - timerStart Timer Index if first Timer, this parameters is typically used |
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10 | * in AMP systems for resource allocation. The Timers before |
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11 | * timerStart will not be accessed. |
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12 | * - timerCnt Number of timers that the driver will use, this parameters is |
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13 | * typically used in AMP systems for resource allocation between |
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14 | * OS instances. |
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15 | * - prescaler Base prescaler, normally set by bootloader but can be |
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16 | * overridden. The default scaler reload value set by bootloader |
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17 | * is so that Timers operate in 1MHz. Setting the prescaler to a |
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18 | * lower value increase the accuracy of the timers but shortens |
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19 | * the time until underflow happens. |
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20 | * - clockTimer Used to select a particular timer to be the system clock |
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21 | * timer. This is useful when multiple GPTIMERs cores are |
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22 | * available, or in AMP systems. By default the TLIB selects the |
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23 | * first timer registered as system clock timer. |
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24 | * |
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25 | * The BSP define APBUART_INFO_AVAIL in order to add the info routine |
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26 | * used for debugging. |
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27 | * |
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28 | * COPYRIGHT (c) 2010. |
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29 | * Cobham Gaisler AB. |
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30 | * |
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31 | * Redistribution and use in source and binary forms, with or without |
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32 | * modification, are permitted provided that the following conditions |
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33 | * are met: |
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34 | * 1. Redistributions of source code must retain the above copyright |
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35 | * notice, this list of conditions and the following disclaimer. |
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36 | * 2. Redistributions in binary form must reproduce the above copyright |
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37 | * notice, this list of conditions and the following disclaimer in the |
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38 | * documentation and/or other materials provided with the distribution. |
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39 | * |
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40 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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41 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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42 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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43 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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44 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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45 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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46 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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47 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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48 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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49 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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50 | * POSSIBILITY OF SUCH DAMAGE. |
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51 | */ |
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52 | |
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53 | #include <drvmgr/drvmgr.h> |
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54 | #include <grlib/ambapp_bus.h> |
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55 | #include <grlib/gptimer.h> |
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56 | #include <grlib/gptimer-regs.h> |
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57 | #include <grlib/io.h> |
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58 | #include <grlib/tlib.h> |
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59 | |
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60 | #if defined(LEON3) |
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61 | #include <bsp/leon3.h> |
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62 | #endif |
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63 | |
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64 | #ifdef GPTIMER_INFO_AVAIL |
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65 | #include <stdio.h> |
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66 | #endif |
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67 | |
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68 | #ifdef RTEMS_SMP |
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69 | #include <rtems/score/processormask.h> |
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70 | #include <rtems/score/smpimpl.h> |
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71 | #endif |
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72 | |
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73 | #include <grlib/grlib_impl.h> |
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74 | |
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75 | #define DBG(x...) |
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76 | |
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77 | /* GPTIMER timer private */ |
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78 | struct gptimer_timer_priv { |
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79 | struct tlib_dev tdev; /* Must be first in struct */ |
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80 | gptimer_timer *tregs; |
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81 | char index; /* Timer Index in this driver */ |
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82 | char tindex; /* Timer Index In Hardware */ |
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83 | uint32_t irq_ack_mask; |
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84 | }; |
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85 | |
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86 | /* GPTIMER Core private */ |
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87 | struct gptimer_priv { |
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88 | struct drvmgr_dev *dev; |
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89 | gptimer *regs; |
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90 | unsigned int base_clk; |
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91 | unsigned int base_freq; |
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92 | unsigned int widthmask; |
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93 | char separate_interrupt; |
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94 | char isr_installed; |
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95 | |
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96 | /* Structure per Timer unit, the core supports up to 8 timers */ |
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97 | int timer_cnt; |
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98 | struct gptimer_timer_priv timers[0]; |
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99 | }; |
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100 | |
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101 | void gptimer_isr(void *data); |
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102 | |
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103 | #if 0 |
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104 | void gptimer_tlib_irq_register(struct tlib_drv *tdrv, tlib_isr_t func, void *data) |
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105 | { |
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106 | struct gptimer_priv *priv = (struct gptimer_priv *)tdrv; |
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107 | |
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108 | if ( SHARED ...) |
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109 | |
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110 | |
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111 | drvmgr_interrupt_register(); |
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112 | } |
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113 | #endif |
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114 | |
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115 | /******************* Driver manager interface ***********************/ |
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116 | |
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117 | /* Driver prototypes */ |
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118 | static struct tlib_drv gptimer_tlib_drv; |
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119 | int gptimer_device_init(struct gptimer_priv *priv); |
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120 | |
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121 | int gptimer_init1(struct drvmgr_dev *dev); |
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122 | #ifdef GPTIMER_INFO_AVAIL |
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123 | static int gptimer_info( |
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124 | struct drvmgr_dev *dev, |
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125 | void (*print_line)(void *p, char *str), |
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126 | void *p, int, char *argv[]); |
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127 | #define GTIMER_INFO_FUNC gptimer_info |
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128 | #else |
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129 | #define GTIMER_INFO_FUNC NULL |
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130 | #endif |
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131 | |
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132 | struct drvmgr_drv_ops gptimer_ops = |
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133 | { |
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134 | .init = {gptimer_init1, NULL, NULL, NULL}, |
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135 | .remove = NULL, |
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136 | .info = GTIMER_INFO_FUNC, |
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137 | }; |
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138 | |
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139 | struct amba_dev_id gptimer_ids[] = |
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140 | { |
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141 | {VENDOR_GAISLER, GAISLER_GPTIMER}, |
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142 | {VENDOR_GAISLER, GAISLER_GRTIMER}, |
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143 | {0, 0} /* Mark end of table */ |
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144 | }; |
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145 | |
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146 | struct amba_drv_info gptimer_drv_info = |
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147 | { |
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148 | { |
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149 | DRVMGR_OBJ_DRV, /* Driver */ |
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150 | NULL, /* Next driver */ |
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151 | NULL, /* Device list */ |
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152 | DRIVER_AMBAPP_GAISLER_GPTIMER_ID,/* Driver ID */ |
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153 | "GPTIMER_DRV", /* Driver Name */ |
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154 | DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */ |
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155 | &gptimer_ops, |
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156 | NULL, /* Funcs */ |
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157 | 0, /* No devices yet */ |
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158 | 0, |
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159 | }, |
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160 | &gptimer_ids[0] |
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161 | }; |
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162 | |
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163 | void gptimer_register_drv (void) |
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164 | { |
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165 | DBG("Registering GPTIMER driver\n"); |
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166 | drvmgr_drv_register(&gptimer_drv_info.general); |
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167 | } |
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168 | |
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169 | int gptimer_init1(struct drvmgr_dev *dev) |
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170 | { |
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171 | struct gptimer_priv *priv; |
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172 | gptimer *regs; |
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173 | struct amba_dev_info *ambadev; |
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174 | struct ambapp_core *pnpinfo; |
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175 | int timer_hw_cnt, timer_cnt, timer_start; |
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176 | int i, size; |
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177 | struct gptimer_timer_priv *timer; |
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178 | union drvmgr_key_value *value; |
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179 | uint32_t irq_ack_mask; |
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180 | |
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181 | /* Get device information from AMBA PnP information */ |
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182 | ambadev = (struct amba_dev_info *)dev->businfo; |
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183 | if ( ambadev == NULL ) { |
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184 | return -1; |
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185 | } |
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186 | pnpinfo = &ambadev->info; |
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187 | regs = (gptimer *)pnpinfo->apb_slv->start; |
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188 | |
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189 | DBG("GPTIMER[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name); |
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190 | |
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191 | /* Get number of Timers */ |
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192 | timer_hw_cnt = GPTIMER_CONFIG_TIMERS_GET(grlib_load_32(®s->config)); |
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193 | |
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194 | /* Let user spelect a range of timers to be used. In AMP systems |
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195 | * it is sometimes neccessary to leave timers for other CPU instances. |
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196 | * |
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197 | * The default operation in AMP is to shared the timers within the |
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198 | * first GPTIMER core as below. This can of course be overrided by |
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199 | * driver resources. |
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200 | */ |
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201 | timer_cnt = timer_hw_cnt; |
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202 | timer_start = 0; |
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203 | #if defined(RTEMS_MULTIPROCESSING) && defined(LEON3) |
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204 | if ((dev->minor_drv == 0) && drvmgr_on_rootbus(dev)) { |
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205 | timer_cnt = 1; |
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206 | timer_start = LEON3_Cpu_Index; |
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207 | } |
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208 | #endif |
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209 | value = drvmgr_dev_key_get(dev, "timerStart", DRVMGR_KT_INT); |
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210 | if ( value) { |
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211 | timer_start = value->i; |
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212 | timer_cnt = timer_hw_cnt - timer_start; |
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213 | } |
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214 | value = drvmgr_dev_key_get(dev, "timerCnt", DRVMGR_KT_INT); |
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215 | if ( value && (value->i < timer_cnt) ) { |
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216 | timer_cnt = value->i; |
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217 | } |
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218 | |
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219 | /* Allocate Common Timer Description, size depends on how many timers |
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220 | * are present. |
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221 | */ |
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222 | size = sizeof(struct gptimer_priv) + |
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223 | timer_cnt*sizeof(struct gptimer_timer_priv); |
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224 | priv = dev->priv = grlib_calloc(1, size); |
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225 | if ( !priv ) |
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226 | return DRVMGR_NOMEM; |
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227 | priv->dev = dev; |
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228 | priv->regs = regs; |
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229 | |
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230 | /* The Base Frequency of the GPTIMER core is the same as the |
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231 | * frequency of the AMBA bus it is situated on. |
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232 | */ |
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233 | drvmgr_freq_get(dev, DEV_APB_SLV, &priv->base_clk); |
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234 | |
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235 | /* This core will may provide important Timer functionality |
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236 | * to other drivers and the RTEMS kernel, the Clock driver |
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237 | * may for example use this device. So the Timer driver must be |
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238 | * initialized in the first iiitialization stage. |
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239 | */ |
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240 | |
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241 | /*** Initialize Hardware ***/ |
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242 | |
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243 | /* If user request to set prescaler, we will do that. However, note |
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244 | * that doing so for the Root-Bus GPTIMER may affect the RTEMS Clock |
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245 | * so that Clock frequency is wrong. |
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246 | */ |
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247 | value = drvmgr_dev_key_get(priv->dev, "prescaler", DRVMGR_KT_INT); |
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248 | if ( value ) |
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249 | grlib_store_32(®s->sreload, value->i); |
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250 | |
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251 | /* Get Frequency that the timers are operating in (after prescaler) */ |
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252 | priv->base_freq = priv->base_clk / (grlib_load_32(®s->sreload) + 1); |
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253 | |
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254 | /* Stop Timer and probe Pending bit. In newer hardware the |
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255 | * timer has pending bit is cleared by writing a one to it, |
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256 | * whereas older versions it is cleared with a zero. |
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257 | */ |
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258 | grlib_store_32(®s->timer[timer_start].tctrl, GPTIMER_TCTRL_IP); |
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259 | if ((grlib_load_32(®s->timer[timer_start].tctrl) & GPTIMER_TCTRL_IP) != 0) |
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260 | irq_ack_mask = ~GPTIMER_TCTRL_IP; |
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261 | else |
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262 | irq_ack_mask = ~0U; |
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263 | |
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264 | /* Probe timer register width mask */ |
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265 | grlib_store_32(®s->timer[timer_start].tcntval, 0xffffffff); |
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266 | priv->widthmask = grlib_load_32(®s->timer[timer_start].tcntval); |
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267 | |
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268 | priv->timer_cnt = timer_cnt; |
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269 | for (i=0; i<timer_cnt; i++) { |
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270 | timer = &priv->timers[i]; |
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271 | timer->index = i; |
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272 | timer->tindex = i + timer_start; |
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273 | timer->tregs = ®s->timer[(int)timer->tindex]; |
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274 | timer->tdev.drv = &gptimer_tlib_drv; |
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275 | timer->irq_ack_mask = irq_ack_mask; |
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276 | |
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277 | /* Register Timer at Timer Library */ |
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278 | tlib_dev_reg(&timer->tdev); |
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279 | } |
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280 | |
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281 | /* Check Interrupt support implementation, two cases: |
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282 | * A. All Timers share one IRQ |
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283 | * B. Each Timer have an individual IRQ. The number is: |
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284 | * BASE_IRQ + timer_index |
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285 | */ |
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286 | priv->separate_interrupt = (grlib_load_32(®s->config) & GPTIMER_CONFIG_SI) != 0; |
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287 | |
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288 | return DRVMGR_OK; |
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289 | } |
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290 | |
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291 | #ifdef GPTIMER_INFO_AVAIL |
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292 | static int gptimer_info( |
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293 | struct drvmgr_dev *dev, |
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294 | void (*print_line)(void *p, char *str), |
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295 | void *p, int argc, char *argv[]) |
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296 | { |
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297 | struct gptimer_priv *priv = dev->priv; |
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298 | struct gptimer_timer_priv *timer; |
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299 | char buf[64]; |
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300 | int i; |
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301 | |
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302 | if (priv == NULL || argc != 0) |
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303 | return -DRVMGR_EINVAL; |
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304 | |
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305 | sprintf(buf, "Timer Count: %d", priv->timer_cnt); |
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306 | print_line(p, buf); |
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307 | sprintf(buf, "REGS: 0x%08x", (unsigned int)priv->regs); |
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308 | print_line(p, buf); |
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309 | sprintf(buf, "BASE SCALER: %d", grlib_load_32(&priv->regs->sreload)); |
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310 | print_line(p, buf); |
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311 | sprintf(buf, "BASE FREQ: %dkHz", priv->base_freq / 1000); |
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312 | print_line(p, buf); |
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313 | sprintf(buf, "SeparateIRQ: %s", priv->separate_interrupt ? "YES":"NO"); |
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314 | print_line(p, buf); |
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315 | |
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316 | for (i=0; i<priv->timer_cnt; i++) { |
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317 | timer = &priv->timers[i]; |
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318 | sprintf(buf, " - TIMER HW Index %d -", timer->tindex); |
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319 | print_line(p, buf); |
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320 | sprintf(buf, " TLIB Index: %d", timer->index); |
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321 | print_line(p, buf); |
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322 | sprintf(buf, " RELOAD REG: %d", grlib_load_32(&timer->tregs->trldval)); |
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323 | print_line(p, buf); |
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324 | sprintf(buf, " CTRL REG: %d", grlib_load_32(&timer->tregs->tctrl)); |
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325 | print_line(p, buf); |
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326 | } |
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327 | |
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328 | return DRVMGR_OK; |
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329 | } |
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330 | #endif |
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331 | |
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332 | static inline struct gptimer_priv *priv_from_timer(struct gptimer_timer_priv *t) |
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333 | { |
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334 | return (struct gptimer_priv *) |
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335 | ((unsigned int)t - |
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336 | sizeof(struct gptimer_priv) - |
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337 | t->index * sizeof(struct gptimer_timer_priv)); |
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338 | } |
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339 | |
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340 | static int gptimer_tlib_int_pend(struct tlib_dev *hand, int ack) |
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341 | { |
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342 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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343 | uint32_t tctrl; |
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344 | |
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345 | tctrl = grlib_load_32(&timer->tregs->tctrl); |
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346 | |
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347 | if ((tctrl & (GPTIMER_TCTRL_IP | GPTIMER_TCTRL_IE)) == |
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348 | (GPTIMER_TCTRL_IP | GPTIMER_TCTRL_IE)) { |
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349 | /* clear Pending IRQ ? */ |
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350 | if (ack) { |
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351 | tctrl &= timer->irq_ack_mask; |
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352 | grlib_store_32(&timer->tregs->tctrl, tctrl); |
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353 | } |
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354 | return 1; /* timer generated IRQ */ |
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355 | } else |
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356 | return 0; /* was not timer causing IRQ */ |
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357 | } |
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358 | |
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359 | void gptimer_isr(void *data) |
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360 | { |
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361 | struct gptimer_priv *priv = data; |
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362 | int i; |
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363 | |
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364 | /* Check all timers for IRQ */ |
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365 | for (i=0;i<priv->timer_cnt; i++) { |
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366 | if (gptimer_tlib_int_pend((void *)&priv->timers[i], 0)) { |
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367 | /* IRQ Was generated by Timer and Pending flag has *not* |
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368 | * yet been cleared, this is to allow ISR to look at |
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369 | * pending bit. Call ISR registered. Clear pending bit. |
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370 | */ |
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371 | if (priv->timers[i].tdev.isr_func) { |
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372 | priv->timers[i].tdev.isr_func( |
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373 | priv->timers[i].tdev.isr_data); |
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374 | } |
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375 | gptimer_tlib_int_pend((void *)&priv->timers[i], 1); |
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376 | } |
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377 | } |
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378 | } |
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379 | |
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380 | static void gptimer_tlib_reset(struct tlib_dev *hand) |
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381 | { |
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382 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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383 | uint32_t tctrl; |
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384 | |
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385 | tctrl = grlib_load_32(&timer->tregs->tctrl); |
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386 | tctrl &= timer->irq_ack_mask; |
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387 | tctrl &= GPTIMER_TCTRL_IP; |
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388 | grlib_store_32(&timer->tregs->tctrl, tctrl); |
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389 | grlib_store_32(&timer->tregs->trldval, 0xffffffff); |
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390 | grlib_store_32(&timer->tregs->tctrl, GPTIMER_TCTRL_LD); |
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391 | } |
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392 | |
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393 | static void gptimer_tlib_get_freq( |
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394 | struct tlib_dev *hand, |
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395 | unsigned int *basefreq, |
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396 | unsigned int *tickrate) |
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397 | { |
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398 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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399 | struct gptimer_priv *priv = priv_from_timer(timer); |
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400 | |
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401 | /* Calculate base frequency from Timer Clock and Prescaler */ |
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402 | if ( basefreq ) |
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403 | *basefreq = priv->base_freq; |
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404 | if ( tickrate ) |
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405 | *tickrate = grlib_load_32(&timer->tregs->trldval) + 1; |
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406 | } |
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407 | |
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408 | static int gptimer_tlib_set_freq(struct tlib_dev *hand, unsigned int tickrate) |
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409 | { |
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410 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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411 | |
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412 | grlib_store_32(&timer->tregs->trldval, tickrate - 1); |
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413 | |
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414 | /*Check that value was allowed (Timer may not be as wide as expected)*/ |
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415 | if (grlib_load_32(&timer->tregs->trldval) != (tickrate - 1)) |
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416 | return -1; |
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417 | else |
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418 | return 0; |
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419 | } |
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420 | |
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421 | static void gptimer_tlib_irq_reg(struct tlib_dev *hand, tlib_isr_t func, void *data, int flags) |
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422 | { |
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423 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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424 | struct gptimer_priv *priv = priv_from_timer(timer); |
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425 | uint32_t tctrl; |
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426 | |
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427 | if ( priv->separate_interrupt ) { |
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428 | drvmgr_interrupt_register(priv->dev, timer->tindex, |
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429 | "gptimer", func, data); |
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430 | } else { |
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431 | if (priv->isr_installed == 0) { |
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432 | /* Shared IRQ handler */ |
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433 | drvmgr_interrupt_register( |
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434 | priv->dev, |
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435 | 0, |
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436 | "gptimer_shared", |
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437 | gptimer_isr, |
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438 | priv); |
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439 | } |
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440 | priv->isr_installed++; |
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441 | } |
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442 | |
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443 | #if RTEMS_SMP |
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444 | if (flags & TLIB_FLAGS_BROADCAST) { |
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445 | int tindex = 0; |
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446 | |
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447 | if (priv->separate_interrupt) { |
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448 | /* Offset interrupt number with HW subtimer index */ |
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449 | tindex = timer->tindex; |
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450 | } |
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451 | drvmgr_interrupt_set_affinity(priv->dev, tindex, |
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452 | _SMP_Get_online_processors()); |
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453 | } |
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454 | #endif |
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455 | |
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456 | tctrl = grlib_load_32(&timer->tregs->tctrl); |
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457 | tctrl |= GPTIMER_TCTRL_IE; |
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458 | grlib_store_32(&timer->tregs->tctrl, tctrl); |
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459 | } |
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460 | |
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461 | static void gptimer_tlib_irq_unreg(struct tlib_dev *hand, tlib_isr_t func, void *data) |
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462 | { |
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463 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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464 | struct gptimer_priv *priv = priv_from_timer(timer); |
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465 | uint32_t tctrl; |
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466 | |
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467 | /* Turn off IRQ at source, unregister IRQ handler */ |
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468 | tctrl = grlib_load_32(&timer->tregs->tctrl); |
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469 | tctrl &= ~GPTIMER_TCTRL_IE; |
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470 | grlib_store_32(&timer->tregs->tctrl, tctrl); |
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471 | |
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472 | if ( priv->separate_interrupt ) { |
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473 | drvmgr_interrupt_unregister(priv->dev, timer->tindex, |
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474 | func, data); |
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475 | } else { |
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476 | timer->tdev.isr_func = NULL; |
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477 | priv->isr_installed--; |
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478 | if (priv->isr_installed == 0) { |
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479 | drvmgr_interrupt_unregister(priv->dev, 0, |
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480 | gptimer_isr, priv); |
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481 | } |
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482 | } |
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483 | } |
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484 | |
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485 | static void gptimer_tlib_start(struct tlib_dev *hand, int once) |
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486 | { |
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487 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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488 | uint32_t tctrl; |
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489 | |
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490 | /* Load the selected frequency before starting Frequency */ |
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491 | tctrl = grlib_load_32(&timer->tregs->tctrl); |
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492 | tctrl &= timer->irq_ack_mask; |
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493 | tctrl &= ~GPTIMER_TCTRL_RS; |
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494 | tctrl |= GPTIMER_TCTRL_LD | GPTIMER_TCTRL_EN; |
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495 | if ( once == 0 ) |
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496 | tctrl |= GPTIMER_TCTRL_RS; /* Restart Timer */ |
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497 | grlib_store_32(&timer->tregs->tctrl, tctrl); |
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498 | } |
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499 | |
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500 | static void gptimer_tlib_stop(struct tlib_dev *hand) |
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501 | { |
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502 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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503 | uint32_t tctrl; |
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504 | |
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505 | /* Load the selected Frequency */ |
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506 | tctrl = grlib_load_32(&timer->tregs->tctrl); |
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507 | tctrl &= ~(GPTIMER_TCTRL_EN|GPTIMER_TCTRL_IP); |
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508 | grlib_store_32(&timer->tregs->tctrl, tctrl); |
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509 | } |
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510 | |
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511 | static void gptimer_tlib_restart(struct tlib_dev *hand) |
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512 | { |
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513 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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514 | uint32_t tctrl; |
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515 | |
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516 | tctrl = grlib_load_32(&timer->tregs->tctrl); |
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517 | tctrl |= GPTIMER_TCTRL_LD | GPTIMER_TCTRL_EN; |
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518 | grlib_store_32(&timer->tregs->tctrl, tctrl); |
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519 | } |
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520 | |
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521 | static void gptimer_tlib_get_counter( |
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522 | struct tlib_dev *hand, |
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523 | unsigned int *counter) |
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524 | { |
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525 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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526 | |
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527 | *counter = grlib_load_32(&timer->tregs->tcntval); |
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528 | } |
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529 | |
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530 | static void gptimer_tlib_get_widthmask( |
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531 | struct tlib_dev *hand, |
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532 | unsigned int *widthmask) |
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533 | { |
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534 | struct gptimer_timer_priv *timer = (struct gptimer_timer_priv *)hand; |
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535 | struct gptimer_priv *priv = priv_from_timer(timer); |
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536 | |
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537 | *widthmask = priv->widthmask; |
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538 | } |
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539 | |
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540 | static struct tlib_drv gptimer_tlib_drv = |
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541 | { |
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542 | .reset = gptimer_tlib_reset, |
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543 | .get_freq = gptimer_tlib_get_freq, |
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544 | .set_freq = gptimer_tlib_set_freq, |
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545 | .irq_reg = gptimer_tlib_irq_reg, |
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546 | .irq_unreg = gptimer_tlib_irq_unreg, |
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547 | .start = gptimer_tlib_start, |
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548 | .stop = gptimer_tlib_stop, |
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549 | .restart = gptimer_tlib_restart, |
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550 | .get_counter = gptimer_tlib_get_counter, |
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551 | .custom = NULL, |
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552 | .int_pend = gptimer_tlib_int_pend, |
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553 | .get_widthmask = gptimer_tlib_get_widthmask, |
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554 | }; |
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