1 | /* This file contains the GRASCS RTEMS driver |
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2 | * |
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3 | * COPYRIGHT (c) 2008. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #include <stdlib.h> |
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12 | #include <bsp.h> |
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13 | #include <grlib/ambapp.h> |
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14 | #include <grlib/grascs.h> |
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15 | #include <grlib/grlib.h> |
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16 | |
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17 | #include <grlib/grlib_impl.h> |
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18 | |
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19 | #ifndef GAISLER_ASCS |
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20 | #define GAISLER_ASCS 0x043 |
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21 | #endif |
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22 | |
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23 | #ifdef DEBUG |
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24 | #define DBG(x...) printk(x) |
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25 | #else |
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26 | #define DBG(x...) |
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27 | #endif |
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28 | |
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29 | typedef struct { |
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30 | volatile unsigned int cmd; |
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31 | volatile unsigned int clk; |
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32 | volatile unsigned int sts; |
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33 | volatile unsigned int tcd; |
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34 | volatile unsigned int tmd; |
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35 | } GRASCS_regs; |
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36 | |
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37 | typedef struct { |
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38 | unsigned char tmconf; |
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39 | unsigned char usconf; |
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40 | unsigned char nslaves; |
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41 | unsigned char dbits; |
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42 | int clkfreq; |
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43 | } GRASCS_caps; |
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44 | |
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45 | typedef struct { |
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46 | GRASCS_regs *regs; /* Pointer to core registers */ |
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47 | GRASCS_caps *caps; /* Pointer to capability struct */ |
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48 | rtems_id tcsem1, tcsem2; |
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49 | rtems_id tmsem1, tmsem2; |
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50 | volatile char running; |
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51 | int tcptr; |
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52 | int tmptr; |
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53 | int tcwords; |
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54 | int tmwords; |
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55 | } GRASCS_cfg; |
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56 | |
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57 | static GRASCS_cfg *cfg = NULL; |
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58 | |
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59 | /*------------------------------------*/ |
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60 | /* Start of internal helper functions */ |
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61 | /*------------------------------------*/ |
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62 | |
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63 | /* Function: ASCS_getaddr |
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64 | Arguments: base: Core's register base address |
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65 | irq: Core's irq |
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66 | Return values: 0 if successful, -1 if core is not found |
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67 | Description: Assigns core's register base address and |
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68 | irq to arguments. Uses AMBA plug and play to find the |
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69 | core. |
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70 | */ |
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71 | static int ASCS_get_addr(int *base, int *irq) { |
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72 | |
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73 | struct ambapp_apb_info core; |
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74 | |
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75 | if(ambapp_find_apbslv(&ambapp_plb, VENDOR_GAISLER, GAISLER_ASCS, &core) == 1) { |
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76 | *base = core.start; |
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77 | *irq = core.irq; |
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78 | DBG("ASCS_get_addr: Registerd ASCS core at 0x%x with irq %i\n",core.start, core.irq); |
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79 | return 0; |
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80 | } |
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81 | DBG("ASCS_get_addr: Failed to detect core\n"); |
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82 | return -1; |
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83 | } |
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84 | |
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85 | /* Function: ASCS_calc_clkreg |
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86 | Arguments: sysfreq: System clock frequency in kHz |
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87 | etrfreq: ETR frequency in Hz |
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88 | Return values: Value of core's CLK-register |
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89 | Description: Calculates value of core's CLK-register. See |
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90 | GRASCS IP core documentation for details. |
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91 | */ |
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92 | static int ASCS_calc_clkreg(int sysfreq, int etrfreq) { |
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93 | |
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94 | if(cfg->caps->usconf) |
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95 | return 1000000/etrfreq; |
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96 | else |
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97 | return sysfreq*1000/etrfreq; |
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98 | } |
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99 | |
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100 | /* Function: ASCS_get_sysfreq |
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101 | Arguments: - |
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102 | Return values: System clock frequency in kHz, -1 if failed |
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103 | Description: Uses AMBA plug and play to lookup system frequency |
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104 | */ |
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105 | static int ASCS_get_sysfreq(void) { |
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106 | |
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107 | struct ambapp_apb_info gpt; |
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108 | struct gptimer_regs *tregs; |
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109 | int tmp; |
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110 | |
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111 | if(ambapp_find_apbslv(&ambapp_plb, VENDOR_GAISLER, GAISLER_GPTIMER, &gpt) == 1) { |
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112 | tregs = (struct gptimer_regs *) gpt.start; |
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113 | tmp = (tregs->scaler_reload + 1)*1000; |
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114 | DBG("ASCS_get_sysfreq: Detected system frequency %i kHz\n",tmp); |
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115 | if((tmp < GRASCS_MIN_SFREQ) || (tmp > GRASCS_MAX_SFREQ)) { |
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116 | DBG("ASCS_get_sysfreq: System frequency is invalid for ASCS core\n"); |
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117 | return -1; |
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118 | } |
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119 | else |
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120 | return (tregs->scaler_reload + 1)*1000; |
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121 | } |
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122 | DBG("ASCS_get_sysfreq: Failed to detect system frequency\n"); |
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123 | return -1; |
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124 | } |
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125 | |
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126 | /* Function: ASCS_irqhandler |
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127 | Arguments: v: not used |
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128 | Return values: - |
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129 | Description: Determines the source of the interrupt, clears the |
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130 | appropriate bits in the core's STS register and releases |
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131 | the associated semaphore |
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132 | */ |
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133 | static rtems_isr ASCS_irqhandler(rtems_vector_number v) { |
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134 | |
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135 | if(cfg->regs->sts & GRASCS_STS_TCDONE) { |
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136 | /* Clear TC done bit */ |
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137 | cfg->regs->sts |= GRASCS_STS_TCDONE; |
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138 | |
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139 | if(--cfg->tcwords == 0) |
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140 | /* No more TCs to perform right now */ |
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141 | rtems_semaphore_release(cfg->tcsem2); |
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142 | else { |
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143 | /* Block not sent yet, start next TC */ |
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144 | if(cfg->caps->dbits == 8) { |
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145 | cfg->tcptr++; |
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146 | cfg->regs->tcd = *((unsigned char*)cfg->tcptr); |
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147 | } |
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148 | else if(cfg->caps->dbits == 16) { |
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149 | cfg->tcptr += 2; |
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150 | cfg->regs->tcd = *((unsigned short int*)cfg->tcptr); |
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151 | } |
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152 | else { |
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153 | cfg->tcptr += 4; |
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154 | cfg->regs->tcd = *((unsigned int*)cfg->tcptr); |
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155 | } |
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156 | } |
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157 | } |
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158 | |
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159 | if(cfg->regs->sts & GRASCS_STS_TMDONE) { |
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160 | /* Clear TM done bit */ |
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161 | cfg->regs->sts |= GRASCS_STS_TMDONE; |
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162 | |
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163 | /* Store received data */ |
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164 | if(cfg->caps->dbits == 8) { |
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165 | *((unsigned char*)cfg->tmptr) = (unsigned char)(cfg->regs->tmd & 0xFF); |
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166 | cfg->tmptr++; |
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167 | } |
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168 | else if(cfg->caps->dbits == 16) { |
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169 | *((unsigned short int*)cfg->tmptr) = (unsigned short int)(cfg->regs->tmd & 0xFFFF); |
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170 | cfg->tmptr += 2; |
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171 | } |
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172 | else { |
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173 | *((unsigned int*)cfg->tmptr) = cfg->regs->tmd; |
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174 | cfg->tmptr += 4; |
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175 | } |
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176 | |
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177 | if(--cfg->tmwords == 0) |
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178 | /* No more TMs to perform right now */ |
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179 | rtems_semaphore_release(cfg->tmsem2); |
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180 | else |
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181 | /* Block not received yet, start next TM */ |
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182 | cfg->regs->cmd |= GRASCS_CMD_SENDTM; |
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183 | } |
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184 | } |
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185 | |
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186 | /*---------------------------*/ |
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187 | /* Start of driver interface */ |
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188 | /*---------------------------*/ |
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189 | |
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190 | /* Function: ASCS_init |
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191 | Arguments: - |
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192 | Return values: 0 if successful, -1 if unsuccessful |
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193 | Description: Initializes the ASCS core |
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194 | */ |
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195 | int ASCS_init(void) { |
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196 | |
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197 | int base, irq, tmp; |
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198 | |
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199 | DBG("ASCS_init: Starting initialization of ASCS core\n"); |
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200 | |
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201 | /* Allocate memory for config, status and capability struct */ |
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202 | if((cfg = grlib_malloc(sizeof(*cfg))) == NULL) { |
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203 | DBG("ASCS_init: Could not allocate memory for cfg struc\n"); |
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204 | return -1; |
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205 | } |
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206 | |
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207 | if((cfg->caps = grlib_calloc(1,sizeof(*cfg->caps))) == NULL) { |
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208 | DBG("ASCS_init: Could not allocate memory for caps struc\n"); |
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209 | goto init_error1; |
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210 | } |
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211 | |
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212 | /* Create semaphores for blocking ASCS_TC/TM functions */ |
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213 | if(rtems_semaphore_create(rtems_build_name('A','S','C','0'),1, |
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214 | (RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE| |
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215 | RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL| |
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216 | RTEMS_NO_PRIORITY_CEILING), 0, |
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217 | &cfg->tcsem1) != RTEMS_SUCCESSFUL) { |
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218 | DBG("ASCS_init: Failed to create semaphore ASC0\n"); |
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219 | goto init_error2; |
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220 | } |
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221 | if(rtems_semaphore_create(rtems_build_name('A','S','C','1'),1, |
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222 | (RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE| |
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223 | RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL| |
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224 | RTEMS_NO_PRIORITY_CEILING), 0, |
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225 | &cfg->tmsem1) != RTEMS_SUCCESSFUL) { |
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226 | DBG("ASCS_init: Failed to create semaphore ASC1\n"); |
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227 | goto init_error2; |
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228 | } |
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229 | /* Create semaphores for waiting on ASCS_TC/TM interrupt */ |
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230 | if(rtems_semaphore_create(rtems_build_name('A','S','C','2'),0, |
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231 | (RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE| |
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232 | RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL| |
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233 | RTEMS_NO_PRIORITY_CEILING), 0, |
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234 | &cfg->tcsem2) != RTEMS_SUCCESSFUL) { |
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235 | DBG("ASCS_init: Failed to create semaphore ASC2\n"); |
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236 | goto init_error2; |
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237 | } |
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238 | if(rtems_semaphore_create(rtems_build_name('A','S','C','3'),0, |
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239 | (RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE| |
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240 | RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL| |
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241 | RTEMS_NO_PRIORITY_CEILING), 0, |
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242 | &cfg->tmsem2) != RTEMS_SUCCESSFUL) { |
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243 | DBG("ASCS_init: Failed to create semaphore ASC3\n"); |
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244 | goto init_error2; |
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245 | } |
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246 | |
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247 | /* Set pointer to core registers */ |
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248 | if(ASCS_get_addr(&base, &irq) == -1) |
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249 | goto init_error2; |
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250 | |
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251 | cfg->regs = (GRASCS_regs*)base; |
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252 | |
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253 | /* Read core capabilities */ |
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254 | tmp = cfg->regs->sts; |
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255 | cfg->caps->dbits = ((tmp >> GRASCS_STS_DBITS_BITS) & 0x1F) + 1; |
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256 | cfg->caps->nslaves = ((tmp >> GRASCS_STS_NSLAVES_BITS) & 0xF) + 1; |
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257 | cfg->caps->tmconf = (tmp >> GRASCS_STS_TMCONF_BITS) & 0x1; |
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258 | cfg->caps->usconf = (tmp >> GRASCS_STS_USCONF_BITS) & 0x1; |
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259 | |
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260 | /* Reset and configure core */ |
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261 | cfg->running = 0; |
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262 | cfg->regs->cmd |= GRASCS_CMD_RESET; |
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263 | if((tmp = ASCS_get_sysfreq()) == -1) |
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264 | goto init_error2; |
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265 | cfg->caps->clkfreq = tmp; |
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266 | while(ASCS_iface_status()) |
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267 | ; |
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268 | cfg->regs->clk = ASCS_calc_clkreg(tmp, GRASCS_DEFAULT_ETRFREQ); |
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269 | cfg->regs->cmd = GRASCS_CMD_US1C; |
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270 | cfg->regs->cmd |= (tmp/1000 << GRASCS_CMD_US1_BITS) | GRASCS_CMD_US1C | |
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271 | GRASCS_CMD_TCDONE | GRASCS_CMD_TMDONE; |
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272 | |
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273 | /* Register interrupt routine */ |
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274 | set_vector(ASCS_irqhandler,irq+0x10,2); |
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275 | |
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276 | return 0; |
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277 | |
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278 | init_error2: |
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279 | free(cfg->caps); |
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280 | init_error1: |
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281 | free(cfg); |
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282 | return -1; |
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283 | } |
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284 | |
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285 | /* Function: ASCS_input_select |
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286 | Arguments: slave: The number of the slave that is active, |
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287 | numbered from 0-15 |
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288 | Return values: 0 if successful, -GRASCS_ERROR_CAPFAULT if slave value |
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289 | is negative or too big, -GRASCS_ERROR_TRANSACTIVE if |
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290 | a TM is active. |
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291 | Description: Sets the slave_sel bits in the core's CMD register. |
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292 | they are used to choose which slave the core listens |
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293 | to when performing a TM. The bits can't be set |
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294 | during a TM, and the function will in such a case fail. |
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295 | */ |
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296 | int ASCS_input_select(int slave) { |
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297 | |
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298 | if((slave < 0) || (slave > cfg->caps->nslaves)) { |
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299 | /* Slave number is negative or too big */ |
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300 | DBG("ASCS_input_select: Wrong slave number\n"); |
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301 | return -GRASCS_ERROR_CAPFAULT; |
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302 | } |
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303 | |
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304 | if(rtems_semaphore_obtain(cfg->tmsem1,RTEMS_NO_WAIT,RTEMS_NO_TIMEOUT) != |
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305 | RTEMS_SUCCESSFUL) { |
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306 | /* Can't change active slave during a TM */ |
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307 | DBG("ASCS_input_select: Transaction active\n"); |
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308 | return -GRASCS_ERROR_TRANSACTIVE; |
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309 | } |
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310 | |
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311 | cfg->regs->cmd = ((cfg->regs->cmd &= ~GRASCS_CMD_SLAVESEL) | |
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312 | (slave << GRASCS_CMD_SLAVESEL_BITS)); |
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313 | |
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314 | rtems_semaphore_release(cfg->tmsem1); |
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315 | return 0; |
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316 | } |
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317 | |
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318 | /* Function: ASCS_etr_select |
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319 | Arguments: src: The source of the ETR signal, valid values are |
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320 | 0-GRASCS_MAX_TMS (0 = internal source, 1-GRASCS_MAX_TMS = |
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321 | external time markers 1-GRASCS_MAX_TMS). |
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322 | freq: ETR frequency in Hz. Valid values are |
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323 | GRASCS_MIN_ETRFREQ-GRASCS_MAX_ETRFREQ |
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324 | Return values: 0 if successful, -GRASCS_ERROR_CAPFAULT if src or freq values |
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325 | are invalid, -GRASCS_ERROR_STARTSTOP if synchronization interface |
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326 | isn't stopped. |
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327 | Description: Changes the source for the ETR signal. The frequency of source signal |
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328 | is assumed to be the same as the frequency of the freq input |
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329 | */ |
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330 | int ASCS_etr_select(int etr, int freq) { |
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331 | |
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332 | if((etr < 0) || (etr > GRASCS_MAX_TMS) || ((cfg->caps->tmconf == 0) && (etr > 0)) || |
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333 | (freq < GRASCS_MIN_ETRFREQ) || (freq > GRASCS_MAX_ETRFREQ)) { |
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334 | /* ETR source value or frequency is invalid */ |
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335 | DBG("ASCS_etr_select: Wrong etr src number or wrong frequency\n"); |
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336 | return -GRASCS_ERROR_CAPFAULT; |
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337 | } |
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338 | |
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339 | if(cfg->regs->sts & GRASCS_STS_ERUNNING) { |
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340 | /* Synchronization interface is running */ |
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341 | DBG("ASCS_etr_select: Synch interface is running\n"); |
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342 | return -GRASCS_ERROR_STARTSTOP; |
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343 | } |
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344 | |
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345 | cfg->regs->clk = ASCS_calc_clkreg(cfg->caps->clkfreq,freq); |
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346 | cfg->regs->cmd = ((cfg->regs->cmd &= ~GRASCS_CMD_ETRCTRL) | |
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347 | (etr << GRASCS_CMD_ETRCTRL_BITS)); |
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348 | |
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349 | return 0; |
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350 | } |
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351 | |
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352 | /* Function: ASCS_start |
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353 | Arguments: - |
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354 | Return values: - |
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355 | Description: Enables the serial interface. |
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356 | */ |
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357 | void ASCS_start(void) { |
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358 | |
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359 | /* Set register and internal status to running */ |
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360 | cfg->regs->cmd |= GRASCS_CMD_STARTSTOP; |
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361 | cfg->running = 1; |
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362 | } |
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363 | |
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364 | /* Function: ASCS_stop |
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365 | Arguments: - |
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366 | Return values: - |
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367 | Description: Disables the serial interface. This function will |
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368 | block until possible calls to TC_send(_block) and |
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369 | TM_recv(_block) has returned in order to be sure |
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370 | that started transactions will be performed. |
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371 | */ |
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372 | void ASCS_stop(void) { |
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373 | |
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374 | /* Set internal status to stopped */ |
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375 | cfg->running = 0; |
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376 | |
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377 | /* Obtain semaphores to avoid possible situation where a |
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378 | TC_send(_block) or TM_recv(_block) is aborted and driver is |
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379 | waiting forever for an interrupt */ |
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380 | rtems_semaphore_obtain(cfg->tcsem1,RTEMS_WAIT,RTEMS_NO_TIMEOUT); |
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381 | rtems_semaphore_obtain(cfg->tmsem1,RTEMS_WAIT,RTEMS_NO_TIMEOUT); |
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382 | |
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383 | /* Change actual register value */ |
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384 | cfg->regs->cmd &= ~GRASCS_CMD_STARTSTOP; |
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385 | |
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386 | /* Release the semaphores */ |
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387 | rtems_semaphore_release(cfg->tcsem1); |
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388 | rtems_semaphore_release(cfg->tmsem1); |
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389 | } |
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390 | |
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391 | /* Function: ASCS_iface_status |
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392 | Arguments: - |
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393 | Return values: 0 if both serial interface and synch interface is stopped, |
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394 | 1 if serial interface is running buth synch interface is |
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395 | stopped, 2 if serial interface is stopped but synch interface |
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396 | is running, 3 if both serial and synch interface is running |
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397 | Description: Reads the core's STS register and reports the status of the |
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398 | serial and synch interfaces |
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399 | */ |
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400 | int ASCS_iface_status(void) { |
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401 | |
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402 | return ((cfg->regs->sts & 0x3) & (0x2 | cfg->running)); |
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403 | } |
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404 | |
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405 | /* Function: ASCS_TC_send |
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406 | Arguments: word: Pointer to a word that should be sent |
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407 | Return values: 0 on success |
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408 | -GRASCS_ERROR_STARTSTOP if serial interface is stopped, |
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409 | -GRASCS_ERROR_TRANSACTIVE if another TC is in progress. |
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410 | Description: Start a TC and sends the data that word points to. |
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411 | */ |
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412 | int ASCS_TC_send(int *word) { |
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413 | |
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414 | int retval; |
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415 | |
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416 | if(rtems_semaphore_obtain(cfg->tcsem1,RTEMS_NO_WAIT,RTEMS_NO_TIMEOUT) != |
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417 | RTEMS_SUCCESSFUL) { |
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418 | /* Can't start a TC_send if another TC_send of TC_send_block is |
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419 | in progress */ |
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420 | DBG("ASCS_TC_send: Could not obtain semaphore, transcation probably in progress\n"); |
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421 | return -GRASCS_ERROR_TRANSACTIVE; |
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422 | } |
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423 | |
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424 | if(!cfg->running) { |
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425 | /* Can't start a TC if serial interface isn't started */ |
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426 | DBG("ASCS_TC_send: Serial interface is not started\n"); |
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427 | retval = -GRASCS_ERROR_STARTSTOP; |
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428 | } |
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429 | else { |
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430 | /* Start the transfer */ |
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431 | cfg->tcwords = 1; |
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432 | if(cfg->caps->dbits == 8) |
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433 | cfg->regs->tcd = *((unsigned char*)word); |
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434 | else if(cfg->caps->dbits == 16) |
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435 | cfg->regs->tcd = *((unsigned short int*)((int)word & ~1)); |
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436 | else |
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437 | cfg->regs->tcd = *((unsigned int*)((int)word & ~3)); |
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438 | |
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439 | /* Wait until transfer is complete */ |
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440 | rtems_semaphore_obtain(cfg->tcsem2,RTEMS_WAIT,RTEMS_NO_TIMEOUT); |
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441 | retval = 0; |
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442 | } |
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443 | |
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444 | rtems_semaphore_release(cfg->tcsem1); |
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445 | |
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446 | return retval; |
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447 | } |
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448 | |
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449 | /* Function: ASCS_TC_send_block |
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450 | Arguments: block: Pointer to the start of a datablock that |
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451 | should be sent. |
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452 | ntrans: Number of transfers needed to transfer |
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453 | the block. |
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454 | Return values: 0 if successfull, -GRASCS_ERROR_STARTSTOP if TC |
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455 | couldn't be started because serial interface is |
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456 | stopped, -GRASCS_ERROR_TRANSACTIVE if TC couldn't |
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457 | be started because another TC isn't done yet. |
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458 | Description: Starts ntrans TCs and sends the data that starts at the |
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459 | address that block points to. The size of each |
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460 | transaction will vary depending on whether the core is |
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461 | configured for 8, 16, or 32 bits data transfers. |
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462 | */ |
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463 | int ASCS_TC_send_block(int *block, int ntrans) { |
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464 | |
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465 | int retval; |
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466 | |
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467 | if(rtems_semaphore_obtain(cfg->tcsem1,RTEMS_NO_WAIT,RTEMS_NO_TIMEOUT) != |
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468 | RTEMS_SUCCESSFUL) { |
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469 | /* Can't start a TC_send_block if another TC_send of TC_send_block is |
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470 | in progress */ |
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471 | DBG("ASCS_TC_send_block: Could not obtain semaphore, transcation probably in progress\n"); |
---|
472 | return -GRASCS_ERROR_TRANSACTIVE; |
---|
473 | } |
---|
474 | |
---|
475 | if(!cfg->running) { |
---|
476 | /* Can't start a TC if serial interface isn't started */ |
---|
477 | DBG("ASCS_TC_send_block: Serial interface is not started\n"); |
---|
478 | retval = -GRASCS_ERROR_STARTSTOP; |
---|
479 | } |
---|
480 | else { |
---|
481 | /* Start the first transfer */ |
---|
482 | cfg->tcwords = ntrans; |
---|
483 | if(cfg->caps->dbits == 8) { |
---|
484 | cfg->tcptr = (int)block; |
---|
485 | cfg->regs->tcd = *((unsigned char*)cfg->tcptr); |
---|
486 | } |
---|
487 | else if(cfg->caps->dbits == 16) { |
---|
488 | cfg->tcptr = (int)block & ~1; |
---|
489 | cfg->regs->tcd = *((unsigned short int*)cfg->tcptr); |
---|
490 | } |
---|
491 | else { |
---|
492 | cfg->tcptr = (int)block & ~3; |
---|
493 | cfg->regs->tcd = *((unsigned int*)cfg->tcptr); |
---|
494 | } |
---|
495 | |
---|
496 | /* Wait until all transfers are complete */ |
---|
497 | rtems_semaphore_obtain(cfg->tcsem2,RTEMS_WAIT,RTEMS_NO_TIMEOUT); |
---|
498 | retval = 0; |
---|
499 | } |
---|
500 | |
---|
501 | rtems_semaphore_release(cfg->tcsem1); |
---|
502 | |
---|
503 | return retval; |
---|
504 | } |
---|
505 | |
---|
506 | /* Function: ASCS_TC_sync_start |
---|
507 | Arguments: - |
---|
508 | Return values: - |
---|
509 | Description: Starts synchronization interface. Might |
---|
510 | be delayed if a TM is in progress. SW can poll |
---|
511 | ASCS_iface_status() to find out when synch interface is |
---|
512 | started. First ETR pulse can be delay up to one ETR |
---|
513 | period depending on the source of the ETR and |
---|
514 | activity on the TM line. |
---|
515 | */ |
---|
516 | void ASCS_TC_sync_start(void) { |
---|
517 | |
---|
518 | cfg->regs->cmd |= GRASCS_CMD_ESTARTSTOP; |
---|
519 | } |
---|
520 | |
---|
521 | /* Function: ASCS_TC_sync_stop |
---|
522 | Arguments: - |
---|
523 | Return values: - |
---|
524 | Description: Stops the synchronization interface. Might |
---|
525 | be delayed for 1 us if a ETR pulse is being generated. SW |
---|
526 | can determine when synch interface has stopped by polling |
---|
527 | ASCS_iface_status(). |
---|
528 | */ |
---|
529 | void ASCS_TC_sync_stop(void) { |
---|
530 | |
---|
531 | cfg->regs->cmd &= ~GRASCS_CMD_ESTARTSTOP; |
---|
532 | } |
---|
533 | |
---|
534 | /* Function: ASCS_TM_recv |
---|
535 | Arguments: word: Pointer to where the received word should be |
---|
536 | placed |
---|
537 | Return values: 0 if successful, -GRASCS_ERROR_STARTSTOP if serial |
---|
538 | interface isn't started, -GRASCS_ERROR_TRANSACTIVE |
---|
539 | if another TM is in progress |
---|
540 | Description: Starts a TM and stores the incoming data in word. |
---|
541 | */ |
---|
542 | int ASCS_TM_recv(int *word) { |
---|
543 | |
---|
544 | int retval; |
---|
545 | |
---|
546 | if(rtems_semaphore_obtain(cfg->tmsem1,RTEMS_NO_WAIT,RTEMS_NO_TIMEOUT) != |
---|
547 | RTEMS_SUCCESSFUL) { |
---|
548 | /* Can't start a TM_recv if another TM_recv of TM_recv_block is |
---|
549 | in progress */ |
---|
550 | DBG("ASCS_TM_recv: Could not obtain semaphore, transaction probably in progress\n"); |
---|
551 | return -GRASCS_ERROR_TRANSACTIVE; |
---|
552 | } |
---|
553 | |
---|
554 | if(!cfg->running) { |
---|
555 | /* Can't start a TM if serial interface isn't started */ |
---|
556 | DBG("ASCS_TM_recv: Serial interface is not started\n"); |
---|
557 | retval = -GRASCS_ERROR_STARTSTOP; |
---|
558 | } |
---|
559 | else { |
---|
560 | /* Start transfer */ |
---|
561 | cfg->tmwords = 1; |
---|
562 | cfg->tmptr = (int)word; |
---|
563 | cfg->regs->cmd |= GRASCS_CMD_SENDTM; |
---|
564 | |
---|
565 | /* Wait until transfer finishes */ |
---|
566 | rtems_semaphore_obtain(cfg->tmsem2,RTEMS_WAIT,RTEMS_NO_TIMEOUT); |
---|
567 | retval = 0; |
---|
568 | } |
---|
569 | |
---|
570 | rtems_semaphore_release(cfg->tmsem1); |
---|
571 | |
---|
572 | return retval; |
---|
573 | } |
---|
574 | |
---|
575 | /* Function: ASCS_TM_recv_block |
---|
576 | Arguments: block: Pointer to where the received datablock |
---|
577 | should be stored. |
---|
578 | ntrans: Number of transfers needed to transfer |
---|
579 | the block. |
---|
580 | Return values: 0 if successful, -GRASCS_ERROR_STARTSTOP if serial |
---|
581 | interface isn't started, -GRASCS_ERROR_TRANSACTIVE if |
---|
582 | a performed TM hasn't been processed yet |
---|
583 | Description: Starts ntrans TMs and stores the data at the address |
---|
584 | that block points to. The size of each transaction |
---|
585 | will vary depending on whether the core is |
---|
586 | configured for 8, 16, or 32 bits data transfers. |
---|
587 | */ |
---|
588 | int ASCS_TM_recv_block(int *block, int ntrans) { |
---|
589 | |
---|
590 | int retval; |
---|
591 | |
---|
592 | if(rtems_semaphore_obtain(cfg->tmsem1,RTEMS_NO_WAIT,RTEMS_NO_TIMEOUT) != |
---|
593 | RTEMS_SUCCESSFUL) { |
---|
594 | /* Can't start a TM_recv_block if another TM_recv of TM_recv_block is |
---|
595 | in progress */ |
---|
596 | DBG("ASCS_TM_recv_block: Could not obtain semaphore, transaction probably in progress\n"); |
---|
597 | return -GRASCS_ERROR_TRANSACTIVE; |
---|
598 | } |
---|
599 | |
---|
600 | if(!cfg->running) { |
---|
601 | /* Can't start a TM if serial interface isn't started */ |
---|
602 | DBG("ASCS_TM_recv_block: Serial interface is not started\n"); |
---|
603 | retval = -GRASCS_ERROR_STARTSTOP; |
---|
604 | } |
---|
605 | else { |
---|
606 | /* Start transfer */ |
---|
607 | cfg->tmwords = ntrans; |
---|
608 | cfg->tmptr = (int)block; |
---|
609 | cfg->regs->cmd |= GRASCS_CMD_SENDTM; |
---|
610 | |
---|
611 | /* Wait until transfer finishes */ |
---|
612 | rtems_semaphore_obtain(cfg->tmsem2,RTEMS_WAIT,RTEMS_NO_TIMEOUT); |
---|
613 | retval = 0; |
---|
614 | } |
---|
615 | |
---|
616 | rtems_semaphore_release(cfg->tmsem1); |
---|
617 | |
---|
618 | return retval; |
---|
619 | } |
---|