source: rtems/bsps/shared/dev/serial/z85c30.c @ 90232bc

Last change on this file since 90232bc was 90232bc, checked in by Joel Sherrill <joel@…>, on Mar 12, 2019 at 7:33:20 PM

z85c30.c: Do not process 0 baud and return an error (CID 1399713)

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1/*
2 *  This file contains the console driver chip level routines for the
3 *  Zilog z85c30 chip.
4 *
5 *  The Zilog Z8530 is also available as:
6 *
7 *    + Intel 82530
8 *    + AMD ???
9 *
10 *  COPYRIGHT (c) 1998 by Radstone Technology
11 *
12 *
13 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
14 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
16 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
17 *
18 * You are hereby granted permission to use, copy, modify, and distribute
19 * this file, provided that this notice, plus the above copyright notice
20 * and disclaimer, appears in all copies. Radstone Technology will provide
21 * no support for this code.
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.org/license/LICENSE.
29 */
30
31#include <rtems.h>
32#include <rtems/libio.h>
33#include <rtems/score/sysstate.h>
34#include <stdlib.h>
35
36#include <libchip/serial.h>
37#include <libchip/sersupp.h>
38#include "z85c30_p.h"
39
40/*
41 * Flow control is only supported when using interrupts
42 */
43
44const console_flow z85c30_flow_RTSCTS = {
45  z85c30_negate_RTS,    /* deviceStopRemoteTx */
46  z85c30_assert_RTS     /* deviceStartRemoteTx */
47};
48
49const console_flow z85c30_flow_DTRCTS = {
50  z85c30_negate_DTR,    /* deviceStopRemoteTx */
51  z85c30_assert_DTR     /* deviceStartRemoteTx */
52};
53
54/*
55 * Exported driver function table
56 */
57
58const console_fns z85c30_fns = {
59  libchip_serial_default_probe,  /* deviceProbe */
60  z85c30_open,                   /* deviceFirstOpen */
61  NULL,                          /* deviceLastClose */
62  NULL,                          /* deviceRead */
63  z85c30_write_support_int,      /* deviceWrite */
64  z85c30_initialize_interrupts,  /* deviceInitialize */
65  z85c30_write_polled,           /* deviceWritePolled */
66  NULL,                          /* deviceSetAttributes */
67  true                           /* deviceOutputUsesInterrupts */
68};
69
70const console_fns z85c30_fns_polled = {
71  libchip_serial_default_probe,      /* deviceProbe */
72  z85c30_open,                       /* deviceFirstOpen */
73  z85c30_close,                      /* deviceLastClose */
74  z85c30_inbyte_nonblocking_polled,  /* deviceRead */
75  z85c30_write_support_polled,       /* deviceWrite */
76  z85c30_init,                       /* deviceInitialize */
77  z85c30_write_polled,               /* deviceWritePolled */
78  NULL,                              /* deviceSetAttributes */
79  false                              /* deviceOutputUsesInterrupts */
80};
81
82#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
83  extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
84#endif
85
86/*
87 *  z85c30_initialize_port
88 *
89 *  initialize a z85c30 Port
90 */
91
92Z85C30_STATIC void z85c30_initialize_port(
93  int minor
94)
95{
96  uintptr_t       ulCtrlPort;
97  uintptr_t       ulBaudDivisor;
98  setRegister_f   setReg;
99
100  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
101  setReg   = Console_Port_Tbl[minor]->setRegister;
102
103  /*
104   * Using register 4
105   * Set up the clock rate is 16 times the data
106   * rate, 8 bit sync char, 1 stop bit, no parity
107   */
108
109  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK );
110
111  /*
112   * Set up for 8 bits/character on receive with
113   * receiver disable via register 3
114   */
115  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS );
116
117  /*
118   * Set up for 8 bits/character on transmit
119   * with transmitter disable via register 5
120   */
121  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS );
122
123  /*
124   * Clear misc control bits
125   */
126  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 );
127
128  /*
129   * Setup the source of the receive and xmit
130   * clock as BRG output and the transmit clock
131   * as the output source for TRxC pin via register 11
132   */
133  (*setReg)(
134    ulCtrlPort,
135    SCC_WR0_SEL_WR11,
136    SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI |
137      SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN
138  );
139
140  ulBaudDivisor = Z85C30_Baud(
141    (uint32_t) Console_Port_Tbl[minor]->ulClock,
142    (uint32_t) ((uintptr_t)Console_Port_Tbl[minor]->pDeviceParams)
143  );
144
145  /*
146   * Setup the lower 8 bits time constants=1E.
147   * If the time constans=1E, then the desire
148   * baud rate will be equilvalent to 9600, via register 12.
149   */
150  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
151
152  /*
153   * using register 13
154   * Setup the upper 8 bits time constant
155   */
156  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
157
158  /*
159   * Enable the baud rate generator enable with clock from the
160   * SCC's PCLK input via register 14.
161   */
162  (*setReg)(
163    ulCtrlPort,
164    SCC_WR0_SEL_WR14,
165    SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL
166  );
167
168  /*
169   * We are only interested in CTS state changes
170   */
171  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE );
172
173  /*
174   * Reset errors
175   */
176  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
177
178  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST );
179
180  /*
181   * Enable the receiver via register 3
182   */
183  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN );
184
185  /*
186   * Enable the transmitter pins set via register 5.
187   */
188  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN );
189
190  /*
191   * Disable interrupts
192   */
193  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 );
194
195  /*
196   * Reset TX CRC
197   */
198  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC );
199
200  /*
201   * Reset interrupts
202   */
203  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
204}
205
206/*
207 *  z85c30_open
208 */
209
210Z85C30_STATIC int z85c30_open(
211  int   major,
212  int   minor,
213  void *arg
214)
215{
216
217  z85c30_initialize_port(minor);
218
219  /*
220   * Assert DTR
221   */
222
223  if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) {
224    z85c30_assert_DTR(minor);
225  }
226
227  return(RTEMS_SUCCESSFUL);
228}
229
230/*
231 *  z85c30_close
232 */
233
234Z85C30_STATIC int z85c30_close(
235  int   major,
236  int   minor,
237  void *arg
238)
239{
240  /*
241   * Negate DTR
242   */
243
244  if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) {
245    z85c30_negate_DTR(minor);
246  }
247
248  return(RTEMS_SUCCESSFUL);
249}
250
251/*
252 *  z85c30_init
253 */
254
255Z85C30_STATIC void z85c30_init(int minor)
256{
257  uintptr_t        ulCtrlPort;
258  z85c30_context  *pz85c30Context;
259  setRegister_f    setReg;
260  getRegister_f    getReg;
261
262  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
263  setReg     = Console_Port_Tbl[minor]->setRegister;
264  getReg     = Console_Port_Tbl[minor]->getRegister;
265
266  pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context));
267
268  Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context;
269
270  pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN;
271
272  if ( ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort2 ) {
273    /*
274     * This is channel A
275     */
276    /*
277     * Ensure port state machine is reset
278     */
279    (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
280
281    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST);
282
283  } else {
284    /*
285     * This is channel B
286     */
287    /*
288     * Ensure port state machine is reset
289     */
290    (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
291
292    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST);
293  }
294}
295
296/*
297 * These routines provide control of the RTS and DTR lines
298 */
299
300/*
301 *  z85c30_assert_RTS
302 */
303
304Z85C30_STATIC int z85c30_assert_RTS(int minor)
305{
306  rtems_interrupt_level  Irql;
307  z85c30_context        *pz85c30Context;
308  setRegister_f          setReg;
309
310  setReg = Console_Port_Tbl[minor]->setRegister;
311
312  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
313
314  /*
315   * Assert RTS
316   */
317
318  rtems_interrupt_disable(Irql);
319    pz85c30Context->ucModemCtrl|=SCC_WR5_RTS;
320    (*setReg)(
321      Console_Port_Tbl[minor]->ulCtrlPort1,
322      SCC_WR0_SEL_WR5,
323      pz85c30Context->ucModemCtrl
324    );
325  rtems_interrupt_enable(Irql);
326  return 0;
327}
328
329/*
330 *  z85c30_negate_RTS
331 */
332
333Z85C30_STATIC int z85c30_negate_RTS(int minor)
334{
335  rtems_interrupt_level  Irql;
336  z85c30_context        *pz85c30Context;
337  setRegister_f          setReg;
338
339  setReg = Console_Port_Tbl[minor]->setRegister;
340
341  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
342
343  /*
344   * Negate RTS
345   */
346
347  rtems_interrupt_disable(Irql);
348    pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS;
349    (*setReg)(
350      Console_Port_Tbl[minor]->ulCtrlPort1,
351      SCC_WR0_SEL_WR5,
352      pz85c30Context->ucModemCtrl
353    );
354  rtems_interrupt_enable(Irql);
355  return 0;
356}
357
358/*
359 * These flow control routines utilise a connection from the local DTR
360 * line to the remote CTS line
361 */
362
363/*
364 *  z85c30_assert_DTR
365 */
366
367Z85C30_STATIC int z85c30_assert_DTR(int minor)
368{
369  rtems_interrupt_level  Irql;
370  z85c30_context        *pz85c30Context;
371  setRegister_f          setReg;
372
373  setReg = Console_Port_Tbl[minor]->setRegister;
374
375  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
376
377  /*
378   * Assert DTR
379   */
380
381  rtems_interrupt_disable(Irql);
382    pz85c30Context->ucModemCtrl|=SCC_WR5_DTR;
383    (*setReg)(
384      Console_Port_Tbl[minor]->ulCtrlPort1,
385      SCC_WR0_SEL_WR5,
386      pz85c30Context->ucModemCtrl
387  );
388  rtems_interrupt_enable(Irql);
389  return 0;
390}
391
392/*
393 *  z85c30_negate_DTR
394 */
395
396Z85C30_STATIC int z85c30_negate_DTR(int minor)
397{
398  rtems_interrupt_level  Irql;
399  z85c30_context        *pz85c30Context;
400  setRegister_f          setReg;
401
402  setReg = Console_Port_Tbl[minor]->setRegister;
403
404  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
405
406  /*
407   * Negate DTR
408   */
409
410  rtems_interrupt_disable(Irql);
411    pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR;
412    (*setReg)(
413      Console_Port_Tbl[minor]->ulCtrlPort1,
414      SCC_WR0_SEL_WR5,
415      pz85c30Context->ucModemCtrl
416  );
417  rtems_interrupt_enable(Irql);
418  return 0;
419}
420
421/*
422 *  z85c30_set_attributes
423 *
424 *  This function sets the SCC channel to reflect the requested termios
425 *  port settings.
426 */
427
428Z85C30_STATIC int z85c30_set_attributes(
429  int                   minor,
430  const struct termios *t
431)
432{
433  uintptr_t              ulCtrlPort;
434  uint32_t               ulBaudDivisor;
435  uint32_t               wr3;
436  uint32_t               wr4;
437  uint32_t               wr5;
438  int                    baud_requested;
439  uint32_t               baud_number;
440  setRegister_f          setReg;
441  rtems_interrupt_level  Irql;
442
443  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
444  setReg     = Console_Port_Tbl[minor]->setRegister;
445
446  /*
447   *  Calculate the baud rate divisor
448   *
449   *  Assert ensures there is no division by 0.
450   */
451
452  baud_requested = t->c_ospeed;
453  if (!baud_requested)
454    baud_requested = B9600;              /* default to 9600 baud */
455
456  baud_number = (uint32_t) rtems_termios_baud_to_number( baud_requested );
457  _Assert( baud_number != 0 );
458
459  /*
460   * POSIX says baud rate of zero is a request to hang up or disconnect.
461   * This is not supported by this driver.
462   */
463  _Assert( baud_number != 0 );
464  if (baud_number == 0) {
465    return -1;
466  }
467
468  ulBaudDivisor = Z85C30_Baud(
469    (uint32_t) Console_Port_Tbl[minor]->ulClock,
470    baud_number
471  );
472
473  wr3 = SCC_WR3_RX_EN;
474  wr4 = SCC_WR4_16_CLOCK;
475  wr5 = SCC_WR5_TX_EN;
476
477  /*
478   *  Parity
479   */
480
481  if (t->c_cflag & PARENB) {
482    wr4 |= SCC_WR4_PAR_EN;
483    if (!(t->c_cflag & PARODD))
484      wr4 |= SCC_WR4_PAR_EVEN;
485  }
486
487  /*
488   *  Character Size
489   */
490
491  if (t->c_cflag & CSIZE) {
492    switch (t->c_cflag & CSIZE) {
493      case CS5:   break;
494      case CS6:  wr3 |= SCC_WR3_RX_6_BITS;  wr5 |= SCC_WR5_TX_6_BITS;  break;
495      case CS7:  wr3 |= SCC_WR3_RX_7_BITS;  wr5 |= SCC_WR5_TX_7_BITS;  break;
496      case CS8:  wr3 |= SCC_WR3_RX_8_BITS;  wr5 |= SCC_WR5_TX_8_BITS;  break;
497    }
498  } else {
499    wr3 |= SCC_WR3_RX_8_BITS;       /* default to 9600,8,N,1 */
500    wr5 |= SCC_WR5_TX_8_BITS;       /* default to 9600,8,N,1 */
501  }
502
503  /*
504   *  Stop Bits
505   */
506
507  if (t->c_cflag & CSTOPB) {
508    wr4 |= SCC_WR4_2_STOP;                      /* 2 stop bits */
509  } else {
510    wr4 |= SCC_WR4_1_STOP;                      /* 1 stop bits */
511  }
512
513  /*
514   *  Now actually set the chip
515   */
516
517  rtems_interrupt_disable(Irql);
518    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 );
519    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 );
520    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 );
521
522    /*
523     * Setup the lower 8 bits time constants=1E.
524     * If the time constans=1E, then the desire
525     * baud rate will be equilvalent to 9600, via register 12.
526     */
527
528    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
529
530    /*
531     * using register 13
532     * Setup the upper 8 bits time constant
533     */
534
535    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
536
537  rtems_interrupt_enable(Irql);
538
539  return 0;
540}
541
542/*
543 *  z85c30_process
544 *
545 *  This is the per port ISR handler.
546 */
547
548Z85C30_STATIC void z85c30_process(
549  int        minor,
550  uint8_t    ucIntPend
551)
552{
553  uint32_t            ulCtrlPort;
554  volatile uint8_t    z85c30_status;
555  char                cChar;
556  setRegister_f       setReg;
557  getRegister_f       getReg;
558
559  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
560  setReg     = Console_Port_Tbl[minor]->setRegister;
561  getReg     = Console_Port_Tbl[minor]->getRegister;
562
563  /*
564   * Deal with any received characters
565   */
566
567  while (ucIntPend&SCC_RR3_B_RX_IP)
568  {
569    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
570    if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
571      break;
572    }
573
574    /*
575     * Return the character read.
576     */
577
578    cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
579
580    rtems_termios_enqueue_raw_characters(
581      Console_Port_Data[minor].termios_data,
582      &cChar,
583      1
584    );
585  }
586
587  /*
588   *  There could be a race condition here if there is not yet a TX
589   *  interrupt pending but the buffer is empty.  This condition has
590   *  been seen before on other z8530 drivers but has not been seen
591   *  with this one.  The typical solution is to use "vector includes
592   *  status" or to only look at the interrupts actually pending
593   *  in RR3.
594   */
595
596  while (true) {
597    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
598    if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
599      /*
600       * We'll get another interrupt when
601       * the transmitter holding reg. becomes
602       * free again and we are clear to send
603       */
604      break;
605    }
606
607#if 0
608    if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) {
609      /*
610       * We can't transmit yet
611       */
612      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
613      /*
614       * The next state change of CTS will wake us up
615       */
616      break;
617    }
618#endif
619
620    rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1);
621    if (rtems_termios_dequeue_characters(
622         Console_Port_Data[minor].termios_data, 1)) {
623      if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) {
624        z85c30_negate_RTS(minor);
625      }
626      Console_Port_Data[minor].bActive = FALSE;
627      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
628      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
629      break;
630    }
631
632  }
633
634  if (ucIntPend & SCC_RR3_B_EXT_IP) {
635    /*
636     * Clear the external status interrupt
637     */
638    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
639    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
640  }
641
642  /*
643   * Reset interrupts
644   */
645  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS);
646}
647
648/*
649 *  z85c30_isr
650 *
651 *  This is the ISR handler for each Z8530.
652 */
653
654Z85C30_STATIC rtems_isr z85c30_isr(
655  rtems_vector_number vector
656)
657{
658  int                 minor;
659  uint32_t            ulCtrlPort;
660  volatile uint8_t    ucIntPend;
661  volatile uint8_t    ucIntPendPort;
662  getRegister_f       getReg;
663
664  for (minor=0;minor<Console_Port_Count;minor++) {
665    if(Console_Port_Tbl[minor]->ulIntVector == vector &&
666       Console_Port_Tbl[minor]->deviceType == SERIAL_Z85C30 ) {
667      ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort2;
668      getReg     = Console_Port_Tbl[minor]->getRegister;
669      do {
670        ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3);
671
672          /*
673           * If this is channel A select channel A status
674           */
675
676          if (ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort1) {
677            ucIntPendPort = ucIntPend >> 3;
678            ucIntPendPort &= 7;
679          } else {
680            ucIntPendPort = ucIntPend &= 7;
681          }
682
683          if (ucIntPendPort) {
684            z85c30_process(minor, ucIntPendPort);
685          }
686      } while (ucIntPendPort);
687    }
688  }
689}
690
691/*
692 *  z85c30_enable_interrupts
693 *
694 *  This routine enables the specified interrupts for this minor.
695 */
696
697Z85C30_STATIC void z85c30_enable_interrupts(
698  int minor,
699  int interrupt_mask
700)
701{
702  uint32_t       ulCtrlPort;
703  setRegister_f  setReg;
704
705  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
706  setReg     = Console_Port_Tbl[minor]->setRegister;
707
708  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask);
709}
710
711/*
712 *  z85c30_initialize_interrupts
713 *
714 *  This routine initializes the port to use interrupts.
715 */
716
717Z85C30_STATIC void z85c30_initialize_interrupts(
718  int minor
719)
720{
721  uint32_t       ulCtrlPort1;
722  setRegister_f  setReg;
723
724  ulCtrlPort1 = Console_Port_Tbl[minor]->ulCtrlPort1;
725  setReg      = Console_Port_Tbl[minor]->setRegister;
726
727
728  z85c30_init(minor);
729
730  Console_Port_Data[minor].bActive=FALSE;
731
732  z85c30_initialize_port( minor );
733
734  if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) {
735    z85c30_negate_RTS(minor);
736  }
737
738#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
739  set_vector(z85c30_isr, Console_Port_Tbl[minor]->ulIntVector, 1);
740#endif
741
742  z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
743
744  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0);              /* XXX vector */
745  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE);
746
747  /*
748   * Reset interrupts
749   */
750
751  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
752}
753
754/*
755 *  z85c30_write_support_int
756 *
757 *  Console Termios output entry point.
758 *
759 */
760
761Z85C30_STATIC ssize_t z85c30_write_support_int(
762  int   minor,
763  const char *buf,
764  size_t len)
765{
766  uint32_t       Irql;
767  uint32_t       ulCtrlPort;
768  setRegister_f  setReg;
769
770  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
771  setReg     = Console_Port_Tbl[minor]->setRegister;
772
773  /*
774   *  We are using interrupt driven output and termios only sends us
775   *  one character at a time.
776   */
777
778  if ( !len )
779    return 0;
780
781  /*
782   *  Put the character out and enable interrupts if necessary.
783   */
784
785  if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) {
786    z85c30_assert_RTS(minor);
787  }
788  rtems_interrupt_disable(Irql);
789    if ( Console_Port_Data[minor].bActive == FALSE) {
790      Console_Port_Data[minor].bActive = TRUE;
791      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR);
792    }
793    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf);
794  rtems_interrupt_enable(Irql);
795
796  return 0;
797}
798
799/*
800 *  z85c30_inbyte_nonblocking_polled
801 *
802 *  This routine polls for a character.
803 */
804
805Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
806  int  minor
807)
808{
809  volatile uint8_t    z85c30_status;
810  uint32_t            ulCtrlPort;
811  getRegister_f       getReg;
812
813  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
814  getReg     = Console_Port_Tbl[minor]->getRegister;
815
816  /*
817   * return -1 if a character is not available.
818   */
819  z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
820  if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
821    return -1;
822  }
823
824  /*
825   * Return the character read.
826   */
827
828  return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
829}
830
831/*
832 *  z85c30_write_support_polled
833 *
834 *  Console Termios output entry point.
835 *
836 */
837
838Z85C30_STATIC ssize_t z85c30_write_support_polled(
839  int   minor,
840  const char *buf,
841  size_t len)
842{
843  int nwrite=0;
844
845  /*
846   * poll each byte in the string out of the port.
847   */
848  while (nwrite < len) {
849    z85c30_write_polled(minor, *buf++);
850    nwrite++;
851  }
852
853  /*
854   * return the number of bytes written.
855   */
856  return nwrite;
857}
858
859/*
860 *  z85c30_write_polled
861 *
862 *  This routine transmits a character using polling.
863 */
864
865Z85C30_STATIC void z85c30_write_polled(
866  int   minor,
867  char  cChar
868)
869{
870  volatile uint8_t   z85c30_status;
871  uint32_t           ulCtrlPort;
872  getRegister_f      getReg;
873  setRegister_f      setReg;
874
875  ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1;
876  getReg     = Console_Port_Tbl[minor]->getRegister;
877  setReg     = Console_Port_Tbl[minor]->setRegister;
878
879  /*
880   * Wait for the Transmit buffer to indicate that it is empty.
881   */
882
883  z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 );
884
885  while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
886    /*
887     * Yield while we wait
888     */
889#if 0
890    if (_System_state_Is_up(_System_state_Get())) {
891      rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
892    }
893#endif
894    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
895  }
896
897  /*
898   * Write the character.
899   */
900
901  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar );
902}
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