[0737710] | 1 | /* |
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| 2 | * This file contains the console driver chip level routines for the |
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[e4acf68] | 3 | * Zilog z85c30 chip. |
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| 4 | * |
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| 5 | * The Zilog Z8530 is also available as: |
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| 6 | * |
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| 7 | * + Intel 82530 |
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| 8 | * + AMD ??? |
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[0737710] | 9 | * |
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| 10 | * COPYRIGHT (c) 1998 by Radstone Technology |
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| 11 | * |
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| 12 | * |
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| 13 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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| 14 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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| 15 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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| 16 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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| 17 | * |
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| 18 | * You are hereby granted permission to use, copy, modify, and distribute |
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| 19 | * this file, provided that this notice, plus the above copyright notice |
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| 20 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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| 21 | * no support for this code. |
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| 22 | * |
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| 23 | * COPYRIGHT (c) 1989-1997. |
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| 24 | * On-Line Applications Research Corporation (OAR). |
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| 25 | * |
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| 26 | * The license and distribution terms for this file may be |
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| 27 | * found in the file LICENSE in this distribution or at |
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[c499856] | 28 | * http://www.rtems.org/license/LICENSE. |
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[0737710] | 29 | */ |
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| 30 | |
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| 31 | #include <rtems.h> |
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| 32 | #include <rtems/libio.h> |
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[39046f7] | 33 | #include <rtems/score/sysstate.h> |
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[0737710] | 34 | #include <stdlib.h> |
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| 35 | |
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[ee3b242b] | 36 | #include <libchip/serial.h> |
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[7e05b53] | 37 | #include <libchip/sersupp.h> |
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[0737710] | 38 | #include "z85c30_p.h" |
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| 39 | |
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| 40 | /* |
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| 41 | * Flow control is only supported when using interrupts |
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| 42 | */ |
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[e4acf68] | 43 | |
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[c8bd3cd] | 44 | const console_flow z85c30_flow_RTSCTS = { |
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[0737710] | 45 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
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| 46 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
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| 47 | }; |
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| 48 | |
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[c8bd3cd] | 49 | const console_flow z85c30_flow_DTRCTS = { |
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[0737710] | 50 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
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| 51 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
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| 52 | }; |
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| 53 | |
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| 54 | /* |
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| 55 | * Exported driver function table |
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| 56 | */ |
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[e4acf68] | 57 | |
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[c8bd3cd] | 58 | const console_fns z85c30_fns = { |
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[fb32356b] | 59 | libchip_serial_default_probe, /* deviceProbe */ |
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[0737710] | 60 | z85c30_open, /* deviceFirstOpen */ |
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[04c5ac7] | 61 | NULL, /* deviceLastClose */ |
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[0737710] | 62 | NULL, /* deviceRead */ |
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| 63 | z85c30_write_support_int, /* deviceWrite */ |
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| 64 | z85c30_initialize_interrupts, /* deviceInitialize */ |
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| 65 | z85c30_write_polled, /* deviceWritePolled */ |
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[8a2d4f2b] | 66 | NULL, /* deviceSetAttributes */ |
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[6640459d] | 67 | true /* deviceOutputUsesInterrupts */ |
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[0737710] | 68 | }; |
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| 69 | |
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[c8bd3cd] | 70 | const console_fns z85c30_fns_polled = { |
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[fb32356b] | 71 | libchip_serial_default_probe, /* deviceProbe */ |
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[0737710] | 72 | z85c30_open, /* deviceFirstOpen */ |
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| 73 | z85c30_close, /* deviceLastClose */ |
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| 74 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
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| 75 | z85c30_write_support_polled, /* deviceWrite */ |
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| 76 | z85c30_init, /* deviceInitialize */ |
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| 77 | z85c30_write_polled, /* deviceWritePolled */ |
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[8a2d4f2b] | 78 | NULL, /* deviceSetAttributes */ |
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[6640459d] | 79 | false /* deviceOutputUsesInterrupts */ |
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[0737710] | 80 | }; |
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| 81 | |
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[a29909cb] | 82 | #if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE) |
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| 83 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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| 84 | #endif |
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[0737710] | 85 | |
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[a3d3d9a] | 86 | /* |
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[749c54e] | 87 | * z85c30_initialize_port |
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[0737710] | 88 | * |
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[749c54e] | 89 | * initialize a z85c30 Port |
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[0737710] | 90 | */ |
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| 91 | |
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[677a503] | 92 | Z85C30_STATIC void z85c30_initialize_port( |
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[0737710] | 93 | int minor |
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| 94 | ) |
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| 95 | { |
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[642c500] | 96 | uintptr_t ulCtrlPort; |
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| 97 | uintptr_t ulBaudDivisor; |
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[0737710] | 98 | setRegister_f setReg; |
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| 99 | |
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[229bcca8] | 100 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
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| 101 | setReg = Console_Port_Tbl[minor]->setRegister; |
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[0737710] | 102 | |
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| 103 | /* |
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| 104 | * Using register 4 |
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| 105 | * Set up the clock rate is 16 times the data |
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| 106 | * rate, 8 bit sync char, 1 stop bit, no parity |
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| 107 | */ |
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| 108 | |
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| 109 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
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| 110 | |
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| 111 | /* |
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| 112 | * Set up for 8 bits/character on receive with |
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| 113 | * receiver disable via register 3 |
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| 114 | */ |
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| 115 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
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| 116 | |
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| 117 | /* |
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| 118 | * Set up for 8 bits/character on transmit |
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| 119 | * with transmitter disable via register 5 |
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| 120 | */ |
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| 121 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
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| 122 | |
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| 123 | /* |
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| 124 | * Clear misc control bits |
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| 125 | */ |
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| 126 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
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| 127 | |
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| 128 | /* |
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| 129 | * Setup the source of the receive and xmit |
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| 130 | * clock as BRG output and the transmit clock |
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| 131 | * as the output source for TRxC pin via register 11 |
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| 132 | */ |
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| 133 | (*setReg)( |
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| 134 | ulCtrlPort, |
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| 135 | SCC_WR0_SEL_WR11, |
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[a3d3d9a] | 136 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
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[0737710] | 137 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
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| 138 | ); |
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| 139 | |
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[a3d3d9a] | 140 | ulBaudDivisor = Z85C30_Baud( |
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[229bcca8] | 141 | (uint32_t) Console_Port_Tbl[minor]->ulClock, |
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| 142 | (uint32_t) ((uintptr_t)Console_Port_Tbl[minor]->pDeviceParams) |
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[0737710] | 143 | ); |
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| 144 | |
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| 145 | /* |
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| 146 | * Setup the lower 8 bits time constants=1E. |
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| 147 | * If the time constans=1E, then the desire |
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| 148 | * baud rate will be equilvalent to 9600, via register 12. |
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| 149 | */ |
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| 150 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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| 151 | |
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| 152 | /* |
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| 153 | * using register 13 |
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| 154 | * Setup the upper 8 bits time constant |
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| 155 | */ |
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| 156 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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[a3d3d9a] | 157 | |
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[0737710] | 158 | /* |
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| 159 | * Enable the baud rate generator enable with clock from the |
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| 160 | * SCC's PCLK input via register 14. |
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| 161 | */ |
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| 162 | (*setReg)( |
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| 163 | ulCtrlPort, |
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| 164 | SCC_WR0_SEL_WR14, |
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| 165 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
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| 166 | ); |
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| 167 | |
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| 168 | /* |
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| 169 | * We are only interested in CTS state changes |
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| 170 | */ |
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| 171 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
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| 172 | |
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| 173 | /* |
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| 174 | * Reset errors |
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| 175 | */ |
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| 176 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 177 | |
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| 178 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
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| 179 | |
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| 180 | /* |
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| 181 | * Enable the receiver via register 3 |
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| 182 | */ |
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| 183 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
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| 184 | |
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| 185 | /* |
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| 186 | * Enable the transmitter pins set via register 5. |
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| 187 | */ |
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| 188 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
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| 189 | |
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| 190 | /* |
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| 191 | * Disable interrupts |
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| 192 | */ |
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| 193 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
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| 194 | |
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| 195 | /* |
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| 196 | * Reset TX CRC |
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| 197 | */ |
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| 198 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
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| 199 | |
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| 200 | /* |
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| 201 | * Reset interrupts |
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| 202 | */ |
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| 203 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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| 204 | } |
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| 205 | |
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[749c54e] | 206 | /* |
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| 207 | * z85c30_open |
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| 208 | */ |
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| 209 | |
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[677a503] | 210 | Z85C30_STATIC int z85c30_open( |
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[0737710] | 211 | int major, |
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| 212 | int minor, |
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| 213 | void *arg |
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| 214 | ) |
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| 215 | { |
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[04c5ac7] | 216 | |
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| 217 | z85c30_initialize_port(minor); |
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| 218 | |
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[0737710] | 219 | /* |
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| 220 | * Assert DTR |
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| 221 | */ |
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| 222 | |
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[229bcca8] | 223 | if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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[0737710] | 224 | z85c30_assert_DTR(minor); |
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| 225 | } |
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| 226 | |
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| 227 | return(RTEMS_SUCCESSFUL); |
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| 228 | } |
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| 229 | |
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[749c54e] | 230 | /* |
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| 231 | * z85c30_close |
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| 232 | */ |
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| 233 | |
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[677a503] | 234 | Z85C30_STATIC int z85c30_close( |
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[0737710] | 235 | int major, |
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| 236 | int minor, |
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| 237 | void *arg |
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| 238 | ) |
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| 239 | { |
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| 240 | /* |
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| 241 | * Negate DTR |
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| 242 | */ |
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| 243 | |
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[229bcca8] | 244 | if (Console_Port_Tbl[minor]->pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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[0737710] | 245 | z85c30_negate_DTR(minor); |
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| 246 | } |
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| 247 | |
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| 248 | return(RTEMS_SUCCESSFUL); |
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| 249 | } |
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| 250 | |
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| 251 | /* |
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[749c54e] | 252 | * z85c30_init |
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[0737710] | 253 | */ |
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| 254 | |
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[677a503] | 255 | Z85C30_STATIC void z85c30_init(int minor) |
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[0737710] | 256 | { |
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[642c500] | 257 | uintptr_t ulCtrlPort; |
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[0737710] | 258 | z85c30_context *pz85c30Context; |
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| 259 | setRegister_f setReg; |
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| 260 | getRegister_f getReg; |
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| 261 | |
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[229bcca8] | 262 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
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| 263 | setReg = Console_Port_Tbl[minor]->setRegister; |
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| 264 | getReg = Console_Port_Tbl[minor]->getRegister; |
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[0737710] | 265 | |
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| 266 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
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| 267 | |
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[c14a619] | 268 | Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context; |
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[0737710] | 269 | |
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| 270 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
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| 271 | |
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[229bcca8] | 272 | if ( ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort2 ) { |
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[0737710] | 273 | /* |
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| 274 | * This is channel A |
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| 275 | */ |
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| 276 | /* |
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| 277 | * Ensure port state machine is reset |
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| 278 | */ |
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[a399857] | 279 | (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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[0737710] | 280 | |
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| 281 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
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| 282 | |
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| 283 | } else { |
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| 284 | /* |
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| 285 | * This is channel B |
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| 286 | */ |
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| 287 | /* |
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| 288 | * Ensure port state machine is reset |
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| 289 | */ |
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[a399857] | 290 | (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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[0737710] | 291 | |
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| 292 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
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| 293 | } |
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| 294 | } |
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| 295 | |
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| 296 | /* |
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| 297 | * These routines provide control of the RTS and DTR lines |
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| 298 | */ |
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[e4acf68] | 299 | |
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[0737710] | 300 | /* |
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| 301 | * z85c30_assert_RTS |
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| 302 | */ |
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[e4acf68] | 303 | |
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[677a503] | 304 | Z85C30_STATIC int z85c30_assert_RTS(int minor) |
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[0737710] | 305 | { |
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| 306 | rtems_interrupt_level Irql; |
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| 307 | z85c30_context *pz85c30Context; |
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| 308 | setRegister_f setReg; |
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| 309 | |
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[229bcca8] | 310 | setReg = Console_Port_Tbl[minor]->setRegister; |
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[0737710] | 311 | |
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| 312 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 313 | |
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[0737710] | 314 | /* |
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| 315 | * Assert RTS |
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| 316 | */ |
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| 317 | |
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| 318 | rtems_interrupt_disable(Irql); |
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| 319 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
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| 320 | (*setReg)( |
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[229bcca8] | 321 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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[0737710] | 322 | SCC_WR0_SEL_WR5, |
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| 323 | pz85c30Context->ucModemCtrl |
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| 324 | ); |
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| 325 | rtems_interrupt_enable(Irql); |
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| 326 | return 0; |
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| 327 | } |
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| 328 | |
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| 329 | /* |
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| 330 | * z85c30_negate_RTS |
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| 331 | */ |
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[e4acf68] | 332 | |
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[677a503] | 333 | Z85C30_STATIC int z85c30_negate_RTS(int minor) |
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[0737710] | 334 | { |
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| 335 | rtems_interrupt_level Irql; |
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| 336 | z85c30_context *pz85c30Context; |
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| 337 | setRegister_f setReg; |
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| 338 | |
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[229bcca8] | 339 | setReg = Console_Port_Tbl[minor]->setRegister; |
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[0737710] | 340 | |
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| 341 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 342 | |
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[0737710] | 343 | /* |
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| 344 | * Negate RTS |
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| 345 | */ |
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| 346 | |
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| 347 | rtems_interrupt_disable(Irql); |
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| 348 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
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| 349 | (*setReg)( |
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[229bcca8] | 350 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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[0737710] | 351 | SCC_WR0_SEL_WR5, |
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| 352 | pz85c30Context->ucModemCtrl |
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| 353 | ); |
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| 354 | rtems_interrupt_enable(Irql); |
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| 355 | return 0; |
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| 356 | } |
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| 357 | |
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| 358 | /* |
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| 359 | * These flow control routines utilise a connection from the local DTR |
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| 360 | * line to the remote CTS line |
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| 361 | */ |
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[e4acf68] | 362 | |
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[0737710] | 363 | /* |
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| 364 | * z85c30_assert_DTR |
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| 365 | */ |
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[e4acf68] | 366 | |
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[677a503] | 367 | Z85C30_STATIC int z85c30_assert_DTR(int minor) |
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[0737710] | 368 | { |
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| 369 | rtems_interrupt_level Irql; |
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| 370 | z85c30_context *pz85c30Context; |
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| 371 | setRegister_f setReg; |
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| 372 | |
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[229bcca8] | 373 | setReg = Console_Port_Tbl[minor]->setRegister; |
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[0737710] | 374 | |
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| 375 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 376 | |
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[0737710] | 377 | /* |
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| 378 | * Assert DTR |
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| 379 | */ |
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| 380 | |
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| 381 | rtems_interrupt_disable(Irql); |
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| 382 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
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| 383 | (*setReg)( |
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[229bcca8] | 384 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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[0737710] | 385 | SCC_WR0_SEL_WR5, |
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| 386 | pz85c30Context->ucModemCtrl |
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| 387 | ); |
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| 388 | rtems_interrupt_enable(Irql); |
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| 389 | return 0; |
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| 390 | } |
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| 391 | |
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| 392 | /* |
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| 393 | * z85c30_negate_DTR |
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| 394 | */ |
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[e4acf68] | 395 | |
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[677a503] | 396 | Z85C30_STATIC int z85c30_negate_DTR(int minor) |
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[0737710] | 397 | { |
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| 398 | rtems_interrupt_level Irql; |
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| 399 | z85c30_context *pz85c30Context; |
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| 400 | setRegister_f setReg; |
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| 401 | |
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[229bcca8] | 402 | setReg = Console_Port_Tbl[minor]->setRegister; |
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[0737710] | 403 | |
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| 404 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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[a3d3d9a] | 405 | |
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[0737710] | 406 | /* |
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| 407 | * Negate DTR |
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| 408 | */ |
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| 409 | |
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| 410 | rtems_interrupt_disable(Irql); |
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| 411 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
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| 412 | (*setReg)( |
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[229bcca8] | 413 | Console_Port_Tbl[minor]->ulCtrlPort1, |
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[0737710] | 414 | SCC_WR0_SEL_WR5, |
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| 415 | pz85c30Context->ucModemCtrl |
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| 416 | ); |
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| 417 | rtems_interrupt_enable(Irql); |
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| 418 | return 0; |
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| 419 | } |
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| 420 | |
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[fb32356b] | 421 | /* |
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| 422 | * z85c30_set_attributes |
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| 423 | * |
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| 424 | * This function sets the SCC channel to reflect the requested termios |
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| 425 | * port settings. |
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| 426 | */ |
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| 427 | |
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| 428 | Z85C30_STATIC int z85c30_set_attributes( |
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| 429 | int minor, |
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| 430 | const struct termios *t |
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| 431 | ) |
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| 432 | { |
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[642c500] | 433 | uintptr_t ulCtrlPort; |
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[ee4f57d] | 434 | uint32_t ulBaudDivisor; |
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| 435 | uint32_t wr3; |
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| 436 | uint32_t wr4; |
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| 437 | uint32_t wr5; |
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[fb32356b] | 438 | int baud_requested; |
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[02958c5e] | 439 | uint32_t baud_number; |
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[fb32356b] | 440 | setRegister_f setReg; |
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| 441 | rtems_interrupt_level Irql; |
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| 442 | |
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[229bcca8] | 443 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
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| 444 | setReg = Console_Port_Tbl[minor]->setRegister; |
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[fb32356b] | 445 | |
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| 446 | /* |
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| 447 | * Calculate the baud rate divisor |
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[02958c5e] | 448 | * |
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| 449 | * Assert ensures there is no division by 0. |
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[fb32356b] | 450 | */ |
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| 451 | |
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[1c6926c1] | 452 | baud_requested = t->c_ospeed; |
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[fb32356b] | 453 | if (!baud_requested) |
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| 454 | baud_requested = B9600; /* default to 9600 baud */ |
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| 455 | |
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[02958c5e] | 456 | baud_number = (uint32_t) rtems_termios_baud_to_number( baud_requested ); |
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| 457 | _Assert( baud_number != 0 ); |
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| 458 | |
---|
[90232bc] | 459 | /* |
---|
| 460 | * POSIX says baud rate of zero is a request to hang up or disconnect. |
---|
| 461 | * This is not supported by this driver. |
---|
| 462 | */ |
---|
| 463 | _Assert( baud_number != 0 ); |
---|
| 464 | if (baud_number == 0) { |
---|
| 465 | return -1; |
---|
| 466 | } |
---|
| 467 | |
---|
[a3d3d9a] | 468 | ulBaudDivisor = Z85C30_Baud( |
---|
[229bcca8] | 469 | (uint32_t) Console_Port_Tbl[minor]->ulClock, |
---|
[02958c5e] | 470 | baud_number |
---|
[fb32356b] | 471 | ); |
---|
| 472 | |
---|
| 473 | wr3 = SCC_WR3_RX_EN; |
---|
| 474 | wr4 = SCC_WR4_16_CLOCK; |
---|
| 475 | wr5 = SCC_WR5_TX_EN; |
---|
| 476 | |
---|
| 477 | /* |
---|
| 478 | * Parity |
---|
| 479 | */ |
---|
| 480 | |
---|
| 481 | if (t->c_cflag & PARENB) { |
---|
| 482 | wr4 |= SCC_WR4_PAR_EN; |
---|
| 483 | if (!(t->c_cflag & PARODD)) |
---|
| 484 | wr4 |= SCC_WR4_PAR_EVEN; |
---|
[a3d3d9a] | 485 | } |
---|
[fb32356b] | 486 | |
---|
| 487 | /* |
---|
| 488 | * Character Size |
---|
| 489 | */ |
---|
| 490 | |
---|
| 491 | if (t->c_cflag & CSIZE) { |
---|
| 492 | switch (t->c_cflag & CSIZE) { |
---|
| 493 | case CS5: break; |
---|
| 494 | case CS6: wr3 |= SCC_WR3_RX_6_BITS; wr5 |= SCC_WR5_TX_6_BITS; break; |
---|
| 495 | case CS7: wr3 |= SCC_WR3_RX_7_BITS; wr5 |= SCC_WR5_TX_7_BITS; break; |
---|
| 496 | case CS8: wr3 |= SCC_WR3_RX_8_BITS; wr5 |= SCC_WR5_TX_8_BITS; break; |
---|
| 497 | } |
---|
| 498 | } else { |
---|
| 499 | wr3 |= SCC_WR3_RX_8_BITS; /* default to 9600,8,N,1 */ |
---|
| 500 | wr5 |= SCC_WR5_TX_8_BITS; /* default to 9600,8,N,1 */ |
---|
| 501 | } |
---|
| 502 | |
---|
| 503 | /* |
---|
| 504 | * Stop Bits |
---|
| 505 | */ |
---|
| 506 | |
---|
| 507 | if (t->c_cflag & CSTOPB) { |
---|
| 508 | wr4 |= SCC_WR4_2_STOP; /* 2 stop bits */ |
---|
| 509 | } else { |
---|
| 510 | wr4 |= SCC_WR4_1_STOP; /* 1 stop bits */ |
---|
| 511 | } |
---|
| 512 | |
---|
[b636d56] | 513 | /* |
---|
| 514 | * Now actually set the chip |
---|
| 515 | */ |
---|
| 516 | |
---|
[fb32356b] | 517 | rtems_interrupt_disable(Irql); |
---|
| 518 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 ); |
---|
| 519 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 ); |
---|
| 520 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 ); |
---|
| 521 | |
---|
| 522 | /* |
---|
| 523 | * Setup the lower 8 bits time constants=1E. |
---|
| 524 | * If the time constans=1E, then the desire |
---|
| 525 | * baud rate will be equilvalent to 9600, via register 12. |
---|
| 526 | */ |
---|
| 527 | |
---|
| 528 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
---|
| 529 | |
---|
| 530 | /* |
---|
| 531 | * using register 13 |
---|
| 532 | * Setup the upper 8 bits time constant |
---|
| 533 | */ |
---|
| 534 | |
---|
| 535 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
---|
| 536 | |
---|
| 537 | rtems_interrupt_enable(Irql); |
---|
| 538 | |
---|
| 539 | return 0; |
---|
| 540 | } |
---|
| 541 | |
---|
[0737710] | 542 | /* |
---|
[749c54e] | 543 | * z85c30_process |
---|
[0737710] | 544 | * |
---|
[749c54e] | 545 | * This is the per port ISR handler. |
---|
[0737710] | 546 | */ |
---|
| 547 | |
---|
[677a503] | 548 | Z85C30_STATIC void z85c30_process( |
---|
[0737710] | 549 | int minor, |
---|
[ee4f57d] | 550 | uint8_t ucIntPend |
---|
[0737710] | 551 | ) |
---|
| 552 | { |
---|
[ee4f57d] | 553 | uint32_t ulCtrlPort; |
---|
| 554 | volatile uint8_t z85c30_status; |
---|
[e11bf43] | 555 | char cChar; |
---|
[0737710] | 556 | setRegister_f setReg; |
---|
| 557 | getRegister_f getReg; |
---|
| 558 | |
---|
[229bcca8] | 559 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
| 560 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
| 561 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
[0737710] | 562 | |
---|
| 563 | /* |
---|
| 564 | * Deal with any received characters |
---|
| 565 | */ |
---|
[04c5ac7] | 566 | |
---|
[0737710] | 567 | while (ucIntPend&SCC_RR3_B_RX_IP) |
---|
| 568 | { |
---|
[c14a619] | 569 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 570 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 571 | break; |
---|
| 572 | } |
---|
| 573 | |
---|
| 574 | /* |
---|
| 575 | * Return the character read. |
---|
| 576 | */ |
---|
| 577 | |
---|
[c14a619] | 578 | cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
[0737710] | 579 | |
---|
| 580 | rtems_termios_enqueue_raw_characters( |
---|
| 581 | Console_Port_Data[minor].termios_data, |
---|
| 582 | &cChar, |
---|
| 583 | 1 |
---|
| 584 | ); |
---|
| 585 | } |
---|
| 586 | |
---|
[04c5ac7] | 587 | /* |
---|
| 588 | * There could be a race condition here if there is not yet a TX |
---|
| 589 | * interrupt pending but the buffer is empty. This condition has |
---|
| 590 | * been seen before on other z8530 drivers but has not been seen |
---|
| 591 | * with this one. The typical solution is to use "vector includes |
---|
| 592 | * status" or to only look at the interrupts actually pending |
---|
| 593 | * in RR3. |
---|
| 594 | */ |
---|
| 595 | |
---|
[6640459d] | 596 | while (true) { |
---|
[0737710] | 597 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
| 598 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 599 | /* |
---|
| 600 | * We'll get another interrupt when |
---|
| 601 | * the transmitter holding reg. becomes |
---|
| 602 | * free again and we are clear to send |
---|
| 603 | */ |
---|
| 604 | break; |
---|
| 605 | } |
---|
[a3d3d9a] | 606 | |
---|
[04c5ac7] | 607 | #if 0 |
---|
[0737710] | 608 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
---|
| 609 | /* |
---|
| 610 | * We can't transmit yet |
---|
| 611 | */ |
---|
| 612 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 613 | /* |
---|
| 614 | * The next state change of CTS will wake us up |
---|
| 615 | */ |
---|
| 616 | break; |
---|
| 617 | } |
---|
[04c5ac7] | 618 | #endif |
---|
[a3d3d9a] | 619 | |
---|
[bfcf4cb3] | 620 | rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1); |
---|
[692b9f7] | 621 | if (rtems_termios_dequeue_characters( |
---|
| 622 | Console_Port_Data[minor].termios_data, 1)) { |
---|
[229bcca8] | 623 | if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
[0737710] | 624 | z85c30_negate_RTS(minor); |
---|
| 625 | } |
---|
[04c5ac7] | 626 | Console_Port_Data[minor].bActive = FALSE; |
---|
| 627 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
[0737710] | 628 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
| 629 | break; |
---|
| 630 | } |
---|
| 631 | |
---|
| 632 | } |
---|
| 633 | |
---|
[04c5ac7] | 634 | if (ucIntPend & SCC_RR3_B_EXT_IP) { |
---|
[0737710] | 635 | /* |
---|
| 636 | * Clear the external status interrupt |
---|
| 637 | */ |
---|
| 638 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
[c14a619] | 639 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 640 | } |
---|
| 641 | |
---|
| 642 | /* |
---|
| 643 | * Reset interrupts |
---|
| 644 | */ |
---|
| 645 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
| 646 | } |
---|
| 647 | |
---|
[749c54e] | 648 | /* |
---|
| 649 | * z85c30_isr |
---|
| 650 | * |
---|
| 651 | * This is the ISR handler for each Z8530. |
---|
| 652 | */ |
---|
| 653 | |
---|
[677a503] | 654 | Z85C30_STATIC rtems_isr z85c30_isr( |
---|
[0737710] | 655 | rtems_vector_number vector |
---|
| 656 | ) |
---|
| 657 | { |
---|
| 658 | int minor; |
---|
[ee4f57d] | 659 | uint32_t ulCtrlPort; |
---|
| 660 | volatile uint8_t ucIntPend; |
---|
| 661 | volatile uint8_t ucIntPendPort; |
---|
[749c54e] | 662 | getRegister_f getReg; |
---|
[0737710] | 663 | |
---|
| 664 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
[229bcca8] | 665 | if(Console_Port_Tbl[minor]->ulIntVector == vector && |
---|
| 666 | Console_Port_Tbl[minor]->deviceType == SERIAL_Z85C30 ) { |
---|
| 667 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort2; |
---|
| 668 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
[0737710] | 669 | do { |
---|
[c14a619] | 670 | ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
[0737710] | 671 | |
---|
| 672 | /* |
---|
| 673 | * If this is channel A select channel A status |
---|
| 674 | */ |
---|
| 675 | |
---|
[229bcca8] | 676 | if (ulCtrlPort == Console_Port_Tbl[minor]->ulCtrlPort1) { |
---|
[973bf436] | 677 | ucIntPendPort = ucIntPend >> 3; |
---|
| 678 | ucIntPendPort &= 7; |
---|
[0737710] | 679 | } else { |
---|
| 680 | ucIntPendPort = ucIntPend &= 7; |
---|
| 681 | } |
---|
| 682 | |
---|
| 683 | if (ucIntPendPort) { |
---|
| 684 | z85c30_process(minor, ucIntPendPort); |
---|
| 685 | } |
---|
| 686 | } while (ucIntPendPort); |
---|
| 687 | } |
---|
| 688 | } |
---|
| 689 | } |
---|
| 690 | |
---|
| 691 | /* |
---|
[04c5ac7] | 692 | * z85c30_enable_interrupts |
---|
| 693 | * |
---|
| 694 | * This routine enables the specified interrupts for this minor. |
---|
[0737710] | 695 | */ |
---|
| 696 | |
---|
[04c5ac7] | 697 | Z85C30_STATIC void z85c30_enable_interrupts( |
---|
[0737710] | 698 | int minor, |
---|
[04c5ac7] | 699 | int interrupt_mask |
---|
[0737710] | 700 | ) |
---|
| 701 | { |
---|
[ee4f57d] | 702 | uint32_t ulCtrlPort; |
---|
[04c5ac7] | 703 | setRegister_f setReg; |
---|
[0737710] | 704 | |
---|
[229bcca8] | 705 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
| 706 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
[0737710] | 707 | |
---|
[04c5ac7] | 708 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask); |
---|
[0737710] | 709 | } |
---|
| 710 | |
---|
| 711 | /* |
---|
| 712 | * z85c30_initialize_interrupts |
---|
| 713 | * |
---|
[04c5ac7] | 714 | * This routine initializes the port to use interrupts. |
---|
[0737710] | 715 | */ |
---|
| 716 | |
---|
[04c5ac7] | 717 | Z85C30_STATIC void z85c30_initialize_interrupts( |
---|
[0737710] | 718 | int minor |
---|
| 719 | ) |
---|
| 720 | { |
---|
[ee4f57d] | 721 | uint32_t ulCtrlPort1; |
---|
[0737710] | 722 | setRegister_f setReg; |
---|
| 723 | |
---|
[229bcca8] | 724 | ulCtrlPort1 = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
| 725 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
[0737710] | 726 | |
---|
| 727 | |
---|
| 728 | z85c30_init(minor); |
---|
| 729 | |
---|
| 730 | Console_Port_Data[minor].bActive=FALSE; |
---|
[04c5ac7] | 731 | |
---|
| 732 | z85c30_initialize_port( minor ); |
---|
| 733 | |
---|
[229bcca8] | 734 | if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
[0737710] | 735 | z85c30_negate_RTS(minor); |
---|
| 736 | } |
---|
| 737 | |
---|
[a29909cb] | 738 | #if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE) |
---|
[229bcca8] | 739 | set_vector(z85c30_isr, Console_Port_Tbl[minor]->ulIntVector, 1); |
---|
[a29909cb] | 740 | #endif |
---|
[0737710] | 741 | |
---|
[04c5ac7] | 742 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX); |
---|
| 743 | |
---|
| 744 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0); /* XXX vector */ |
---|
| 745 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
| 746 | |
---|
| 747 | /* |
---|
| 748 | * Reset interrupts |
---|
| 749 | */ |
---|
[0737710] | 750 | |
---|
[04c5ac7] | 751 | (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
[0737710] | 752 | } |
---|
| 753 | |
---|
[a3d3d9a] | 754 | /* |
---|
[0737710] | 755 | * z85c30_write_support_int |
---|
| 756 | * |
---|
| 757 | * Console Termios output entry point. |
---|
| 758 | * |
---|
| 759 | */ |
---|
[e4acf68] | 760 | |
---|
[3ed964f9] | 761 | Z85C30_STATIC ssize_t z85c30_write_support_int( |
---|
[a3d3d9a] | 762 | int minor, |
---|
| 763 | const char *buf, |
---|
[3ed964f9] | 764 | size_t len) |
---|
[0737710] | 765 | { |
---|
[ee4f57d] | 766 | uint32_t Irql; |
---|
| 767 | uint32_t ulCtrlPort; |
---|
[04c5ac7] | 768 | setRegister_f setReg; |
---|
[0737710] | 769 | |
---|
[229bcca8] | 770 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
| 771 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
[0737710] | 772 | |
---|
| 773 | /* |
---|
[04c5ac7] | 774 | * We are using interrupt driven output and termios only sends us |
---|
| 775 | * one character at a time. |
---|
[0737710] | 776 | */ |
---|
[04c5ac7] | 777 | |
---|
| 778 | if ( !len ) |
---|
| 779 | return 0; |
---|
| 780 | |
---|
| 781 | /* |
---|
| 782 | * Put the character out and enable interrupts if necessary. |
---|
| 783 | */ |
---|
| 784 | |
---|
[229bcca8] | 785 | if (Console_Port_Tbl[minor]->pDeviceFlow != &z85c30_flow_RTSCTS) { |
---|
[04c5ac7] | 786 | z85c30_assert_RTS(minor); |
---|
[0737710] | 787 | } |
---|
[04c5ac7] | 788 | rtems_interrupt_disable(Irql); |
---|
| 789 | if ( Console_Port_Data[minor].bActive == FALSE) { |
---|
| 790 | Console_Port_Data[minor].bActive = TRUE; |
---|
| 791 | z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR); |
---|
| 792 | } |
---|
| 793 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf); |
---|
| 794 | rtems_interrupt_enable(Irql); |
---|
[0737710] | 795 | |
---|
[3ed964f9] | 796 | return 0; |
---|
[0737710] | 797 | } |
---|
| 798 | |
---|
[a3d3d9a] | 799 | /* |
---|
[0737710] | 800 | * z85c30_inbyte_nonblocking_polled |
---|
| 801 | * |
---|
| 802 | * This routine polls for a character. |
---|
| 803 | */ |
---|
[e4acf68] | 804 | |
---|
[677a503] | 805 | Z85C30_STATIC int z85c30_inbyte_nonblocking_polled( |
---|
[0737710] | 806 | int minor |
---|
| 807 | ) |
---|
| 808 | { |
---|
[ee4f57d] | 809 | volatile uint8_t z85c30_status; |
---|
| 810 | uint32_t ulCtrlPort; |
---|
[0737710] | 811 | getRegister_f getReg; |
---|
| 812 | |
---|
[229bcca8] | 813 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
| 814 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
[0737710] | 815 | |
---|
| 816 | /* |
---|
| 817 | * return -1 if a character is not available. |
---|
| 818 | */ |
---|
[c14a619] | 819 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
[0737710] | 820 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
| 821 | return -1; |
---|
| 822 | } |
---|
| 823 | |
---|
| 824 | /* |
---|
| 825 | * Return the character read. |
---|
| 826 | */ |
---|
[c14a619] | 827 | |
---|
| 828 | return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8); |
---|
[0737710] | 829 | } |
---|
| 830 | |
---|
[a3d3d9a] | 831 | /* |
---|
[0737710] | 832 | * z85c30_write_support_polled |
---|
| 833 | * |
---|
| 834 | * Console Termios output entry point. |
---|
| 835 | * |
---|
| 836 | */ |
---|
| 837 | |
---|
[3ed964f9] | 838 | Z85C30_STATIC ssize_t z85c30_write_support_polled( |
---|
[0737710] | 839 | int minor, |
---|
| 840 | const char *buf, |
---|
[3ed964f9] | 841 | size_t len) |
---|
[0737710] | 842 | { |
---|
| 843 | int nwrite=0; |
---|
| 844 | |
---|
| 845 | /* |
---|
| 846 | * poll each byte in the string out of the port. |
---|
| 847 | */ |
---|
| 848 | while (nwrite < len) { |
---|
| 849 | z85c30_write_polled(minor, *buf++); |
---|
| 850 | nwrite++; |
---|
| 851 | } |
---|
| 852 | |
---|
| 853 | /* |
---|
| 854 | * return the number of bytes written. |
---|
| 855 | */ |
---|
| 856 | return nwrite; |
---|
| 857 | } |
---|
[c14a619] | 858 | |
---|
[a3d3d9a] | 859 | /* |
---|
[c14a619] | 860 | * z85c30_write_polled |
---|
| 861 | * |
---|
| 862 | * This routine transmits a character using polling. |
---|
| 863 | */ |
---|
| 864 | |
---|
| 865 | Z85C30_STATIC void z85c30_write_polled( |
---|
| 866 | int minor, |
---|
| 867 | char cChar |
---|
| 868 | ) |
---|
| 869 | { |
---|
[ee4f57d] | 870 | volatile uint8_t z85c30_status; |
---|
| 871 | uint32_t ulCtrlPort; |
---|
[c14a619] | 872 | getRegister_f getReg; |
---|
| 873 | setRegister_f setReg; |
---|
| 874 | |
---|
[229bcca8] | 875 | ulCtrlPort = Console_Port_Tbl[minor]->ulCtrlPort1; |
---|
| 876 | getReg = Console_Port_Tbl[minor]->getRegister; |
---|
| 877 | setReg = Console_Port_Tbl[minor]->setRegister; |
---|
[c14a619] | 878 | |
---|
| 879 | /* |
---|
| 880 | * Wait for the Transmit buffer to indicate that it is empty. |
---|
| 881 | */ |
---|
| 882 | |
---|
| 883 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
---|
| 884 | |
---|
| 885 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
| 886 | /* |
---|
| 887 | * Yield while we wait |
---|
| 888 | */ |
---|
[0eb85ae] | 889 | #if 0 |
---|
[c14a619] | 890 | if (_System_state_Is_up(_System_state_Get())) { |
---|
| 891 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
| 892 | } |
---|
[0eb85ae] | 893 | #endif |
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[c14a619] | 894 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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| 895 | } |
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| 896 | |
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| 897 | /* |
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| 898 | * Write the character. |
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| 899 | */ |
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| 900 | |
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| 901 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar ); |
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| 902 | } |
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