source: rtems/bsps/shared/dev/irq/arm-gicv3.c @ 23ec04c

Last change on this file since 23ec04c was 23ec04c, checked in by Sebastian Huber <sebastian.huber@…>, on 07/06/21 at 16:39:57

bsps/irq: bsp_interrupt_get_affinity()

Return a status code for bsp_interrupt_get_affinity().

Update #3269.

  • Property mode set to 100644
File size: 13.4 KB
Line 
1/*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <dev/irq/arm-gic.h>
29#include <dev/irq/arm-gic-arch.h>
30
31#include <bsp/irq.h>
32#include <bsp/irq-generic.h>
33#include <bsp/start.h>
34
35#ifdef ARM_MULTILIB_ARCH_V4
36#include <rtems/score/armv4.h>
37#else
38#include <rtems/score/cpu_irq.h>
39#endif
40
41#define PRIORITY_DEFAULT 127
42
43#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
44#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
45#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
46#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
47#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
48#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
49#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
50#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
51#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
52
53#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
54#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)
55#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
56#define ICC_SGIR_IRM BSP_BIT32(40)
57#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)
58#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)
59#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
60#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)
61#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)
62#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)
63#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)
64#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)
65#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
66#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)
67#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)
68#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
69
70#ifdef ARM_MULTILIB_ARCH_V4
71/* cpuif->iccicr */
72#define ICC_CTLR    "p15, 0, %0, c12, c12, 4"
73
74/* cpuif->iccpmr */
75#define ICC_PMR     "p15, 0, %0,  c4,  c6, 0"
76
77/* cpuif->iccbpr */
78#define ICC_BPR0    "p15, 0, %0, c12,  c8, 3"
79#define ICC_BPR1    "p15, 0, %0, c12, c12, 3"
80
81/* cpuif->icciar */
82#define ICC_IAR0    "p15, 0, %0, c12,  c8, 0"
83#define ICC_IAR1    "p15, 0, %0, c12, c12, 0"
84
85/* cpuif->icceoir */
86#define ICC_EOIR0   "p15, 0, %0, c12,  c8, 1"
87#define ICC_EOIR1   "p15, 0, %0, c12, c12, 1"
88
89#define ICC_SRE     "p15, 0, %0, c12, c12, 5"
90
91#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
92#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
93
94#define MPIDR       "p15, 0, %0, c0, c0, 5"
95
96#define READ_SR(SR_NAME) \
97({ \
98  uint32_t value; \
99  __asm__ volatile("mrc    " SR_NAME : "=r" (value) ); \
100  value; \
101})
102
103#define WRITE_SR(SR_NAME, VALUE) \
104    __asm__ volatile("mcr    " SR_NAME "  \n" : : "r" (VALUE) );
105
106#define ICC_SGI1    "p15, 0, %Q0, %R0, c12"
107#define WRITE64_SR(SR_NAME, VALUE) \
108    __asm__ volatile("mcrr    " SR_NAME "  \n" : : "r" (VALUE) );
109
110#else /* ARM_MULTILIB_ARCH_V4 */
111
112/* AArch64 GICv3 registers are not named in GCC */
113#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
114#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
115#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
116#define ICC_PMR     "S3_0_C4_C6_0, %0"
117#define ICC_EOIR1   "S3_0_C12_C12_1, %0"
118#define ICC_SRE     "S3_0_C12_C12_5, %0"
119#define ICC_BPR0    "S3_0_C12_C8_3, %0"
120#define ICC_CTLR    "S3_0_C12_C12_4, %0"
121#define ICC_IAR1    "%0, S3_0_C12_C12_0"
122#define MPIDR       "%0, mpidr_el1"
123#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)
124#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)
125#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
126
127#define ICC_SGI1    "S3_0_C12_C11_5, %0"
128#define WRITE64_SR(SR_NAME, VALUE) \
129    __asm__ volatile("msr    " SR_NAME "  \n" : : "r" (VALUE) );
130#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)
131
132#define READ_SR(SR_NAME) \
133({ \
134  uint64_t value; \
135  __asm__ volatile("mrs    " SR_NAME : "=&r" (value) ); \
136  value; \
137})
138
139
140#endif /* ARM_MULTILIB_ARCH_V4 */
141
142static volatile gic_redist *gicv3_get_redist(uint32_t cpu_index)
143{
144  return (volatile gic_redist *)
145    ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000);
146}
147
148static volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
149{
150  return (volatile gic_sgi_ppi *)
151    ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
152}
153
154void bsp_interrupt_dispatch(void)
155{
156  uint32_t icciar = READ_SR(ICC_IAR1);
157  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
158  rtems_vector_number spurious = 1023;
159
160  if (vector != spurious) {
161    arm_interrupt_handler_dispatch(vector);
162
163    WRITE_SR(ICC_EOIR1, icciar);
164  }
165}
166
167rtems_status_code bsp_interrupt_get_attributes(
168  rtems_vector_number         vector,
169  rtems_interrupt_attributes *attributes
170)
171{
172  return RTEMS_SUCCESSFUL;
173}
174
175rtems_status_code bsp_interrupt_is_pending(
176  rtems_vector_number vector,
177  bool               *pending
178)
179{
180  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
181  bsp_interrupt_assert(pending != NULL);
182  *pending = false;
183  return RTEMS_UNSATISFIED;
184}
185
186rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
187{
188  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
189  return RTEMS_UNSATISFIED;
190}
191
192#if defined(RTEMS_SMP)
193rtems_status_code bsp_interrupt_raise_on(
194  rtems_vector_number vector,
195  uint32_t            cpu_index
196)
197{
198  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
199  return RTEMS_UNSATISFIED;
200}
201#endif
202
203rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
204{
205  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
206  return RTEMS_UNSATISFIED;
207}
208
209rtems_status_code bsp_interrupt_vector_is_enabled(
210  rtems_vector_number vector,
211  bool               *enabled
212)
213{
214  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
215  bsp_interrupt_assert(enabled != NULL);
216  *enabled = false;
217  return RTEMS_UNSATISFIED;
218}
219
220rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
221{
222
223  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
224
225  if (vector >= 32) {
226    volatile gic_dist *dist = ARM_GIC_DIST;
227    gic_id_enable(dist, vector);
228  } else {
229    volatile gic_sgi_ppi *sgi_ppi =
230      gicv3_get_sgi_ppi(_SMP_Get_current_processor());
231    /* Set interrupt group to 1 in the current security mode */
232#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE)
233    sgi_ppi->icspigrpr[0] |= 1 << (vector % 32);
234    sgi_ppi->icspigrpmodr[0] &= ~(1 << (vector % 32));
235#else
236    sgi_ppi->icspigrpr[0] &= ~(1 << (vector % 32));
237    sgi_ppi->icspigrpmodr[0] |= 1 << (vector % 32);
238#endif
239    /* Set enable */
240    sgi_ppi->icspiser[0] = 1 << (vector % 32);
241  }
242
243  return RTEMS_SUCCESSFUL;
244}
245
246rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
247{
248  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
249
250  if (vector >= 32) {
251    volatile gic_dist *dist = ARM_GIC_DIST;
252    gic_id_disable(dist, vector);
253  } else {
254    volatile gic_sgi_ppi *sgi_ppi =
255      gicv3_get_sgi_ppi(_SMP_Get_current_processor());
256    sgi_ppi->icspicer[0] = 1 << (vector % 32);
257  }
258
259  return RTEMS_SUCCESSFUL;
260}
261
262static inline uint32_t get_id_count(volatile gic_dist *dist)
263{
264  uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr);
265
266  id_count = 32 * (id_count + 1);
267  id_count = id_count <= 1020 ? id_count : 1020;
268
269  return id_count;
270}
271
272static void gicv3_init_cpu_interface(void)
273{
274  uint32_t cpu_index = _SMP_Get_current_processor();
275  uint32_t sre_value = 0x7;
276  WRITE_SR(ICC_SRE, sre_value);
277  WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff));
278  WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0));
279
280  volatile gic_redist *redist = gicv3_get_redist(cpu_index);
281  uint32_t waker = redist->icrwaker;
282  uint32_t waker_mask = GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP;
283  waker &= ~waker_mask;
284  redist->icrwaker = waker;
285
286  volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
287  /* Set interrupt group to 1 in the current security mode */
288#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE)
289  sgi_ppi->icspigrpr[0] = 0xffffffff;
290  sgi_ppi->icspigrpmodr[0] = 0;
291#else
292  sgi_ppi->icspigrpr[0] = 0x0;
293  sgi_ppi->icspigrpmodr[0] = 0xffffffff;
294#endif
295  for (int id = 0; id < 32; id++) {
296    sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT;
297  }
298
299  /* Enable interrupt groups 0 and 1 */
300  WRITE_SR(ICC_IGRPEN0, 0x1);
301  WRITE_SR(ICC_IGRPEN1, 0x1);
302  WRITE_SR(ICC_CTLR, 0x0);
303}
304
305rtems_status_code bsp_interrupt_facility_initialize(void)
306{
307  volatile gic_dist *dist = ARM_GIC_DIST;
308  uint32_t id_count = get_id_count(dist);
309  uint32_t id;
310
311  arm_interrupt_facility_set_exception_handler();
312
313  dist->icddcr = GIC_DIST_ICDDCR_ARE_NS | GIC_DIST_ICDDCR_ARE_S
314               | GIC_DIST_ICDDCR_ENABLE_GRP1S | GIC_DIST_ICDDCR_ENABLE_GRP1NS
315               | GIC_DIST_ICDDCR_ENABLE_GRP0;
316
317  for (id = 0; id < id_count; id += 32) {
318    /* Disable all interrupts */
319    dist->icdicer[id / 32] = 0xffffffff;
320
321    /* Set interrupt group to 1 in the current security mode */
322#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE)
323    dist->icdigr[id / 32] = 0xffffffff;
324    dist->icdigmr[id / 32] = 0;
325#else
326    dist->icdigr[id / 32] = 0;
327    dist->icdigmr[id / 32] = 0xffffffff;
328#endif
329  }
330
331  for (id = 0; id < id_count; ++id) {
332    gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
333  }
334
335  for (id = 32; id < id_count; ++id) {
336    gic_id_set_targets(dist, id, 0x01);
337  }
338
339  gicv3_init_cpu_interface();
340  return RTEMS_SUCCESSFUL;
341}
342
343#ifdef RTEMS_SMP
344BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
345{
346  volatile gic_dist *dist = ARM_GIC_DIST;
347
348  while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
349    /* Wait */
350  }
351
352  gicv3_init_cpu_interface();
353}
354#endif
355
356rtems_status_code arm_gic_irq_set_priority(
357  rtems_vector_number vector,
358  uint8_t priority
359)
360{
361  rtems_status_code sc = RTEMS_SUCCESSFUL;
362
363  if (bsp_interrupt_is_valid_vector(vector)) {
364    if (vector >= 32) {
365      volatile gic_dist *dist = ARM_GIC_DIST;
366      gic_id_set_priority(dist, vector, priority);
367    } else {
368      volatile gic_sgi_ppi *sgi_ppi =
369        gicv3_get_sgi_ppi(_SMP_Get_current_processor());
370      sgi_ppi->icspiprior[vector] = priority;
371    }
372  } else {
373    sc = RTEMS_INVALID_ID;
374  }
375
376  return sc;
377}
378
379rtems_status_code arm_gic_irq_get_priority(
380  rtems_vector_number vector,
381  uint8_t *priority
382)
383{
384  rtems_status_code sc = RTEMS_SUCCESSFUL;
385
386  if (bsp_interrupt_is_valid_vector(vector)) {
387    if (vector >= 32) {
388      volatile gic_dist *dist = ARM_GIC_DIST;
389      *priority = gic_id_get_priority(dist, vector);
390    } else {
391      volatile gic_sgi_ppi *sgi_ppi =
392        gicv3_get_sgi_ppi(_SMP_Get_current_processor());
393      *priority = sgi_ppi->icspiprior[vector];
394    }
395  } else {
396    sc = RTEMS_INVALID_ID;
397  }
398
399  return sc;
400}
401
402void bsp_interrupt_set_affinity(
403  rtems_vector_number vector,
404  const Processor_mask *affinity
405)
406{
407  volatile gic_dist *dist = ARM_GIC_DIST;
408  uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
409
410  gic_id_set_targets(dist, vector, targets);
411}
412
413rtems_status_code bsp_interrupt_get_affinity(
414  rtems_vector_number vector,
415  Processor_mask *affinity
416)
417{
418  volatile gic_dist *dist = ARM_GIC_DIST;
419  uint8_t targets = gic_id_get_targets(dist, vector);
420
421  _Processor_mask_From_uint32_t(affinity, targets, 0);
422  return RTEMS_SUCCESSFUL;
423}
424
425void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
426{
427#ifndef ARM_MULTILIB_ARCH_V4
428  uint64_t mpidr;
429#else
430  uint32_t mpidr;
431#endif
432  mpidr = READ_SR(MPIDR);
433  uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
434                 | ICC_SGIR_INTID(vector)
435                 | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
436                 | ICC_SGIR_CPU_TARGET_LIST(targets);
437#ifndef ARM_MULTILIB_ARCH_V4
438  value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
439#endif
440  WRITE64_SR(ICC_SGI1, value);
441}
442
443uint32_t arm_gic_irq_processor_count(void)
444{
445  volatile gic_dist *dist = ARM_GIC_DIST;
446  uint32_t cpu_count;
447
448  if ((dist->icddcr & GIC_DIST_ICDDCR_ARE_S) == 0) {
449    cpu_count = GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
450  } else {
451    int i;
452
453    /* Assume that an interrupt export port exists */
454    cpu_count = 0;
455
456    for (i = 0; i < CPU_MAXIMUM_PROCESSORS; ++i) {
457      volatile gic_redist *redist = gicv3_get_redist(i);
458
459      if ((redist->icrtyper & GIC_REDIST_ICRTYPER_LAST) != 0) {
460        break;
461      }
462
463      ++cpu_count;
464    }
465  }
466
467  return cpu_count;
468}
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