1 | /* |
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2 | * Cache Manager |
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3 | * |
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4 | * Copyright (C) 2014, 2018 embedded brains GmbH |
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5 | * |
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6 | * COPYRIGHT (c) 1989-1999. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.org/license/LICENSE. |
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12 | */ |
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13 | |
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14 | /* |
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15 | * The functions in this file implement the API to the RTEMS Cache Manager. |
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16 | * This file is intended to be included in a cache implemention source file |
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17 | * provided by the architecture or BSP, e.g. |
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18 | * |
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19 | * - bsps/${RTEMS_CPU}/shared/cache/cache.c |
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20 | * - bsps/${RTEMS_CPU}/${RTEMS_BSP_FAMILY}/start/cache.c |
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21 | * |
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22 | * In this file a couple of defines and inline functions may be provided and |
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23 | * afterwards this file is included, e.g. |
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24 | * |
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25 | * #define CPU_DATA_CACHE_ALIGNMENT XYZ |
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26 | * ... |
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27 | * #include "../../../bsps/shared/cache/cacheimpl.h" |
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28 | * |
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29 | * The cache implementation source file shall define |
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30 | * |
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31 | * #define CPU_DATA_CACHE_ALIGNMENT <POSITIVE INTEGER> |
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32 | * |
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33 | * to enable the data cache support. |
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34 | * |
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35 | * The cache implementation source file shall define |
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36 | * |
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37 | * #define CPU_INSTRUCTION_CACHE_ALIGNMENT <POSITIVE INTEGER> |
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38 | * |
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39 | * to enable the instruction cache support. |
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40 | * |
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41 | * The cache implementation source file shall define |
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42 | * |
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43 | * #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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44 | * |
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45 | * if it provides cache maintenance functions which operate on multiple lines. |
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46 | * Otherwise a generic loop with single line operations will be used. It is |
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47 | * strongly recommended to provide the implementation in terms of static inline |
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48 | * functions for performance reasons. |
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49 | * |
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50 | * The cache implementation source file shall define |
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51 | * |
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52 | * #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |
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53 | * |
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54 | * if it provides functions to get the data and instruction cache sizes by |
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55 | * level. |
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56 | * |
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57 | * The cache implementation source file shall define |
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58 | * |
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59 | * #define CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION |
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60 | * |
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61 | * if special instructions must be used to synchronize the instruction caches |
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62 | * after a code change. |
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63 | * |
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64 | * The cache implementation source file shall define |
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65 | * |
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66 | * #define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA |
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67 | * |
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68 | * if an external implementation of rtems_cache_disable_data() is provided, |
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69 | * e.g. as an implementation in assembly code. |
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70 | * |
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71 | * The cache implementation source file shall define |
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72 | * |
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73 | * #define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING |
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74 | * |
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75 | * if the hardware provides no instruction cache snooping and the instruction |
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76 | * cache invalidation needs software support. |
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77 | * |
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78 | * The functions below are implemented with inline routines found in the cache |
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79 | * implementation source file for each architecture or BSP. In the event that |
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80 | * not support for a specific function for a cache is provided, the API routine |
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81 | * does nothing (but does exist). |
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82 | */ |
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83 | |
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84 | #include <rtems.h> |
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85 | |
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86 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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87 | #include <rtems/score/smpimpl.h> |
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88 | #include <rtems/score/threaddispatch.h> |
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89 | #endif |
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90 | |
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91 | #if CPU_DATA_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES |
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92 | #error "CPU_DATA_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" |
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93 | #endif |
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94 | |
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95 | #if CPU_INSTRUCTION_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES |
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96 | #error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" |
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97 | #endif |
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98 | |
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99 | /* |
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100 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE |
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101 | */ |
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102 | |
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103 | /* |
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104 | * This function is called to flush the data cache by performing cache |
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105 | * copybacks. It must determine how many cache lines need to be copied |
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106 | * back and then perform the copybacks. |
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107 | */ |
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108 | void |
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109 | rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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110 | { |
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111 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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112 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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113 | _CPU_cache_flush_data_range( d_addr, n_bytes ); |
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114 | #else |
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115 | const void * final_address; |
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116 | |
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117 | /* |
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118 | * Set d_addr to the beginning of the cache line; final_address indicates |
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119 | * the last address_t which needs to be pushed. Increment d_addr and push |
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120 | * the resulting line until final_address is passed. |
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121 | */ |
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122 | |
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123 | if( n_bytes == 0 ) |
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124 | /* Do nothing if number of bytes to flush is zero */ |
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125 | return; |
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126 | |
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127 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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128 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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129 | while( d_addr <= final_address ) { |
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130 | _CPU_cache_flush_1_data_line( d_addr ); |
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131 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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132 | } |
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133 | #endif |
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134 | #endif |
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135 | } |
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136 | |
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137 | /* |
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138 | * This function is responsible for performing a data cache invalidate. |
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139 | * It must determine how many cache lines need to be invalidated and then |
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140 | * perform the invalidations. |
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141 | */ |
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142 | void |
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143 | rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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144 | { |
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145 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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146 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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147 | _CPU_cache_invalidate_data_range( d_addr, n_bytes ); |
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148 | #else |
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149 | const void * final_address; |
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150 | |
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151 | /* |
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152 | * Set d_addr to the beginning of the cache line; final_address indicates |
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153 | * the last address_t which needs to be invalidated. Increment d_addr and |
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154 | * invalidate the resulting line until final_address is passed. |
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155 | */ |
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156 | |
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157 | if( n_bytes == 0 ) |
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158 | /* Do nothing if number of bytes to invalidate is zero */ |
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159 | return; |
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160 | |
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161 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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162 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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163 | while( final_address >= d_addr ) { |
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164 | _CPU_cache_invalidate_1_data_line( d_addr ); |
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165 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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166 | } |
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167 | #endif |
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168 | #endif |
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169 | } |
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170 | |
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171 | /* |
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172 | * This function is responsible for performing a data cache flush. |
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173 | * It flushes the entire cache. |
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174 | */ |
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175 | void |
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176 | rtems_cache_flush_entire_data( void ) |
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177 | { |
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178 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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179 | /* |
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180 | * Call the CPU-specific routine |
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181 | */ |
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182 | _CPU_cache_flush_entire_data(); |
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183 | #endif |
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184 | } |
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185 | |
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186 | /* |
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187 | * This function is responsible for performing a data cache |
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188 | * invalidate. It invalidates the entire cache. |
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189 | */ |
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190 | void |
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191 | rtems_cache_invalidate_entire_data( void ) |
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192 | { |
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193 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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194 | /* |
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195 | * Call the CPU-specific routine |
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196 | */ |
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197 | |
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198 | _CPU_cache_invalidate_entire_data(); |
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199 | #endif |
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200 | } |
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201 | |
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202 | /* |
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203 | * This function returns the data cache granularity. |
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204 | */ |
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205 | size_t |
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206 | rtems_cache_get_data_line_size( void ) |
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207 | { |
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208 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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209 | return CPU_DATA_CACHE_ALIGNMENT; |
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210 | #else |
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211 | return 0; |
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212 | #endif |
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213 | } |
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214 | |
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215 | size_t |
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216 | rtems_cache_get_data_cache_size( uint32_t level ) |
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217 | { |
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218 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) |
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219 | return _CPU_cache_get_data_cache_size( level ); |
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220 | #else |
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221 | return 0; |
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222 | #endif |
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223 | } |
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224 | |
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225 | /* |
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226 | * This function freezes the data cache; cache lines |
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227 | * are not replaced. |
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228 | */ |
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229 | void |
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230 | rtems_cache_freeze_data( void ) |
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231 | { |
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232 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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233 | _CPU_cache_freeze_data(); |
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234 | #endif |
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235 | } |
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236 | |
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237 | void rtems_cache_unfreeze_data( void ) |
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238 | { |
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239 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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240 | _CPU_cache_unfreeze_data(); |
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241 | #endif |
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242 | } |
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243 | |
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244 | void |
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245 | rtems_cache_enable_data( void ) |
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246 | { |
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247 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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248 | _CPU_cache_enable_data(); |
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249 | #endif |
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250 | } |
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251 | |
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252 | #if !defined(CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA) |
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253 | void |
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254 | rtems_cache_disable_data( void ) |
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255 | { |
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256 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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257 | _CPU_cache_disable_data(); |
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258 | #endif |
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259 | } |
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260 | #endif |
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261 | |
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262 | /* |
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263 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE |
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264 | */ |
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265 | |
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266 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ |
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267 | && defined(RTEMS_SMP) \ |
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268 | && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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269 | |
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270 | typedef struct { |
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271 | const void *addr; |
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272 | size_t size; |
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273 | } smp_cache_area; |
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274 | |
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275 | static void smp_cache_inst_inv(void *arg) |
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276 | { |
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277 | smp_cache_area *area = arg; |
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278 | |
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279 | _CPU_cache_invalidate_instruction_range(area->addr, area->size); |
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280 | } |
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281 | |
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282 | static void smp_cache_inst_inv_all(void *arg) |
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283 | { |
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284 | _CPU_cache_invalidate_entire_instruction(); |
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285 | } |
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286 | |
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287 | static void smp_cache_broadcast( SMP_Action_handler handler, void *arg ) |
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288 | { |
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289 | uint32_t isr_level; |
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290 | Per_CPU_Control *cpu_self; |
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291 | |
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292 | isr_level = _ISR_Get_level(); |
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293 | |
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294 | if ( isr_level == 0 ) { |
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295 | cpu_self = _Thread_Dispatch_disable(); |
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296 | } else { |
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297 | cpu_self = _Per_CPU_Get(); |
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298 | } |
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299 | |
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300 | _SMP_Broadcast_action( handler, arg ); |
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301 | |
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302 | if ( isr_level == 0 ) { |
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303 | _Thread_Dispatch_enable( cpu_self ); |
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304 | } |
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305 | } |
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306 | |
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307 | #endif |
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308 | |
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309 | /* |
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310 | * This function is responsible for performing an instruction cache |
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311 | * invalidate. It must determine how many cache lines need to be invalidated |
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312 | * and then perform the invalidations. |
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313 | */ |
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314 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ |
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315 | && !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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316 | static void |
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317 | _CPU_cache_invalidate_instruction_range( |
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318 | const void * i_addr, |
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319 | size_t n_bytes |
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320 | ) |
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321 | { |
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322 | const void * final_address; |
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323 | |
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324 | /* |
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325 | * Set i_addr to the beginning of the cache line; final_address indicates |
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326 | * the last address_t which needs to be invalidated. Increment i_addr and |
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327 | * invalidate the resulting line until final_address is passed. |
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328 | */ |
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329 | |
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330 | if( n_bytes == 0 ) |
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331 | /* Do nothing if number of bytes to invalidate is zero */ |
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332 | return; |
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333 | |
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334 | final_address = (void *)((size_t)i_addr + n_bytes - 1); |
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335 | i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); |
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336 | while( final_address >= i_addr ) { |
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337 | _CPU_cache_invalidate_1_instruction_line( i_addr ); |
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338 | i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); |
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339 | } |
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340 | } |
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341 | #endif |
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342 | |
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343 | void |
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344 | rtems_cache_invalidate_multiple_instruction_lines( |
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345 | const void * i_addr, |
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346 | size_t n_bytes |
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347 | ) |
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348 | { |
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349 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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350 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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351 | smp_cache_area area = { i_addr, n_bytes }; |
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352 | |
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353 | smp_cache_broadcast( smp_cache_inst_inv, &area ); |
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354 | #else |
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355 | _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); |
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356 | #endif |
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357 | #endif |
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358 | } |
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359 | |
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360 | /* |
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361 | * This function is responsible for performing an instruction cache |
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362 | * invalidate. It invalidates the entire cache. |
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363 | */ |
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364 | void |
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365 | rtems_cache_invalidate_entire_instruction( void ) |
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366 | { |
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367 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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368 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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369 | smp_cache_broadcast( smp_cache_inst_inv_all, NULL ); |
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370 | #else |
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371 | _CPU_cache_invalidate_entire_instruction(); |
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372 | #endif |
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373 | #endif |
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374 | } |
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375 | |
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376 | /* |
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377 | * This function returns the instruction cache granularity. |
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378 | */ |
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379 | size_t |
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380 | rtems_cache_get_instruction_line_size( void ) |
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381 | { |
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382 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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383 | return CPU_INSTRUCTION_CACHE_ALIGNMENT; |
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384 | #else |
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385 | return 0; |
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386 | #endif |
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387 | } |
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388 | |
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389 | size_t |
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390 | rtems_cache_get_instruction_cache_size( uint32_t level ) |
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391 | { |
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392 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) |
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393 | return _CPU_cache_get_instruction_cache_size( level ); |
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394 | #else |
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395 | return 0; |
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396 | #endif |
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397 | } |
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398 | |
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399 | /* |
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400 | * This function freezes the instruction cache; cache lines |
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401 | * are not replaced. |
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402 | */ |
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403 | void |
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404 | rtems_cache_freeze_instruction( void ) |
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405 | { |
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406 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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407 | _CPU_cache_freeze_instruction(); |
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408 | #endif |
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409 | } |
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410 | |
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411 | void rtems_cache_unfreeze_instruction( void ) |
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412 | { |
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413 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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414 | _CPU_cache_unfreeze_instruction(); |
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415 | #endif |
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416 | } |
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417 | |
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418 | void |
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419 | rtems_cache_enable_instruction( void ) |
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420 | { |
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421 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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422 | _CPU_cache_enable_instruction(); |
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423 | #endif |
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424 | } |
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425 | |
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426 | void |
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427 | rtems_cache_disable_instruction( void ) |
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428 | { |
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429 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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430 | _CPU_cache_disable_instruction(); |
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431 | #endif |
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432 | } |
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433 | |
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434 | /* Returns the maximal cache line size of all cache kinds in bytes. */ |
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435 | size_t rtems_cache_get_maximal_line_size( void ) |
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436 | { |
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437 | #if defined(CPU_MAXIMAL_CACHE_ALIGNMENT) |
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438 | return CPU_MAXIMAL_CACHE_ALIGNMENT; |
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439 | #endif |
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440 | size_t max_line_size = 0; |
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441 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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442 | { |
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443 | size_t data_line_size = CPU_DATA_CACHE_ALIGNMENT; |
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444 | if ( max_line_size < data_line_size ) |
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445 | max_line_size = data_line_size; |
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446 | } |
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447 | #endif |
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448 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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449 | { |
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450 | size_t instruction_line_size = CPU_INSTRUCTION_CACHE_ALIGNMENT; |
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451 | if ( max_line_size < instruction_line_size ) |
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452 | max_line_size = instruction_line_size; |
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453 | } |
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454 | #endif |
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455 | return max_line_size; |
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456 | } |
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457 | |
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458 | /* |
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459 | * Purpose is to synchronize caches after code has been loaded |
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460 | * or self modified. Actual implementation is simple only |
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461 | * but it can and should be repaced by optimized version |
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462 | * which does not need flush and invalidate all cache levels |
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463 | * when code is changed. |
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464 | */ |
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465 | void rtems_cache_instruction_sync_after_code_change( |
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466 | const void *code_addr, |
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467 | size_t n_bytes |
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468 | ) |
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469 | { |
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470 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION) |
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471 | _CPU_cache_instruction_sync_after_code_change( code_addr, n_bytes ); |
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472 | #else |
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473 | rtems_cache_flush_multiple_data_lines( code_addr, n_bytes ); |
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474 | rtems_cache_invalidate_multiple_instruction_lines( code_addr, n_bytes ); |
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475 | #endif |
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476 | } |
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