[cf1f72e] | 1 | /* |
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[8ef3818] | 2 | * Cache Manager |
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| 3 | * |
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| 4 | * COPYRIGHT (c) 1989-1999. |
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| 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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[c499856] | 9 | * http://www.rtems.org/license/LICENSE. |
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[8ef3818] | 10 | * |
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[359e537] | 11 | * |
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[cf1f72e] | 12 | * The functions in this file implement the API to the RTEMS Cache Manager and |
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[8ef3818] | 13 | * are divided into data cache and instruction cache functions. Data cache |
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[5e77d129] | 14 | * functions only have bodies if a data cache is supported. Instruction |
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| 15 | * cache functions only have bodies if an instruction cache is supported. |
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| 16 | * Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is |
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| 17 | * defined, where x E {DATA, INSTRUCTION}. These definitions are found in |
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| 18 | * the Cache Manager Wrapper header files, often |
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[359e537] | 19 | * |
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[5e77d129] | 20 | * rtems/c/src/lib/libcpu/CPU/cache_.h |
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[359e537] | 21 | * |
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[2bd440e] | 22 | * The cache implementation header file can define |
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[4bf2a6aa] | 23 | * |
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| 24 | * #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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| 25 | * |
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[2bd440e] | 26 | * if it provides cache maintenance functions which operate on multiple lines. |
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[4bf2a6aa] | 27 | * Otherwise a generic loop with single line operations will be used. It is |
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| 28 | * strongly recommended to provide the implementation in terms of static |
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| 29 | * inline functions for performance reasons. |
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[2bd440e] | 30 | * |
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[8ef3818] | 31 | * The functions below are implemented with CPU dependent inline routines |
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[5e77d129] | 32 | * found in the cache.c files for each CPU. In the event that a CPU does |
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| 33 | * not support a specific function for a cache it has, the CPU dependent |
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| 34 | * routine does nothing (but does exist). |
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[359e537] | 35 | * |
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[8ef3818] | 36 | * At this point, the Cache Manager makes no considerations, and provides no |
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| 37 | * support for BSP specific issues such as a secondary cache. In such a system, |
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| 38 | * the CPU dependent routines would have to be modified, or a BSP layer added |
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| 39 | * to this Manager. |
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| 40 | */ |
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| 41 | |
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[cf1f72e] | 42 | #include <rtems.h> |
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[ddbc3f8d] | 43 | |
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[5bf0c1a] | 44 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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| 45 | #include <rtems/score/smpimpl.h> |
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| 46 | #endif |
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| 47 | |
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[a8865f8] | 48 | #if CPU_DATA_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES |
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| 49 | #error "CPU_DATA_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" |
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| 50 | #endif |
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| 51 | |
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| 52 | #if CPU_INSTRUCTION_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES |
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| 53 | #error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" |
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| 54 | #endif |
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| 55 | |
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[8ef3818] | 56 | /* |
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[cf1f72e] | 57 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE |
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[8ef3818] | 58 | */ |
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| 59 | |
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| 60 | /* |
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| 61 | * This function is called to flush the data cache by performing cache |
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| 62 | * copybacks. It must determine how many cache lines need to be copied |
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| 63 | * back and then perform the copybacks. |
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| 64 | */ |
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| 65 | void |
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[5e77d129] | 66 | rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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[8ef3818] | 67 | { |
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[5e77d129] | 68 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[2bd440e] | 69 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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| 70 | _CPU_cache_flush_data_range( d_addr, n_bytes ); |
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| 71 | #else |
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[cf1f72e] | 72 | const void * final_address; |
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| 73 | |
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| 74 | /* |
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| 75 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 76 | * the last address_t which needs to be pushed. Increment d_addr and push |
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| 77 | * the resulting line until final_address is passed. |
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| 78 | */ |
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| 79 | |
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[d2978ee9] | 80 | if( n_bytes == 0 ) |
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| 81 | /* Do nothing if number of bytes to flush is zero */ |
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| 82 | return; |
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[359e537] | 83 | |
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[cf1f72e] | 84 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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[5e77d129] | 85 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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[cf1f72e] | 86 | while( d_addr <= final_address ) { |
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[5e77d129] | 87 | _CPU_cache_flush_1_data_line( d_addr ); |
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| 88 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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[cf1f72e] | 89 | } |
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| 90 | #endif |
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[2bd440e] | 91 | #endif |
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[8ef3818] | 92 | } |
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| 93 | |
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| 94 | /* |
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| 95 | * This function is responsible for performing a data cache invalidate. |
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| 96 | * It must determine how many cache lines need to be invalidated and then |
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| 97 | * perform the invalidations. |
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| 98 | */ |
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| 99 | void |
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[5e77d129] | 100 | rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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[8ef3818] | 101 | { |
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[5e77d129] | 102 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[2bd440e] | 103 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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| 104 | _CPU_cache_invalidate_data_range( d_addr, n_bytes ); |
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| 105 | #else |
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[cf1f72e] | 106 | const void * final_address; |
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| 107 | |
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| 108 | /* |
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| 109 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 110 | * the last address_t which needs to be invalidated. Increment d_addr and |
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| 111 | * invalidate the resulting line until final_address is passed. |
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| 112 | */ |
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| 113 | |
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[d2978ee9] | 114 | if( n_bytes == 0 ) |
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| 115 | /* Do nothing if number of bytes to invalidate is zero */ |
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| 116 | return; |
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[359e537] | 117 | |
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[cf1f72e] | 118 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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[5e77d129] | 119 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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[ec45e86] | 120 | while( final_address >= d_addr ) { |
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[5e77d129] | 121 | _CPU_cache_invalidate_1_data_line( d_addr ); |
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| 122 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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[cf1f72e] | 123 | } |
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| 124 | #endif |
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[2bd440e] | 125 | #endif |
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[8ef3818] | 126 | } |
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| 127 | |
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| 128 | /* |
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| 129 | * This function is responsible for performing a data cache flush. |
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| 130 | * It flushes the entire cache. |
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| 131 | */ |
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| 132 | void |
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[5e77d129] | 133 | rtems_cache_flush_entire_data( void ) |
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[8ef3818] | 134 | { |
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[5e77d129] | 135 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[8ef3818] | 136 | /* |
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| 137 | * Call the CPU-specific routine |
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| 138 | */ |
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[5e77d129] | 139 | _CPU_cache_flush_entire_data(); |
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[cf1f72e] | 140 | #endif |
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[8ef3818] | 141 | } |
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| 142 | |
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| 143 | /* |
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| 144 | * This function is responsible for performing a data cache |
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| 145 | * invalidate. It invalidates the entire cache. |
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| 146 | */ |
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| 147 | void |
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[5e77d129] | 148 | rtems_cache_invalidate_entire_data( void ) |
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[8ef3818] | 149 | { |
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[5e77d129] | 150 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[cf1f72e] | 151 | /* |
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| 152 | * Call the CPU-specific routine |
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| 153 | */ |
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| 154 | |
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[5e77d129] | 155 | _CPU_cache_invalidate_entire_data(); |
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[cf1f72e] | 156 | #endif |
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[8ef3818] | 157 | } |
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| 158 | |
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| 159 | /* |
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| 160 | * This function returns the data cache granularity. |
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| 161 | */ |
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[e7549ff4] | 162 | size_t |
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[5e77d129] | 163 | rtems_cache_get_data_line_size( void ) |
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[8ef3818] | 164 | { |
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[5e77d129] | 165 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 166 | return CPU_DATA_CACHE_ALIGNMENT; |
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[cf1f72e] | 167 | #else |
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| 168 | return 0; |
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| 169 | #endif |
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[8ef3818] | 170 | } |
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| 171 | |
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[e1d7bf0] | 172 | size_t |
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| 173 | rtems_cache_get_data_cache_size( uint32_t level ) |
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| 174 | { |
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| 175 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) |
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| 176 | return _CPU_cache_get_data_cache_size( level ); |
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| 177 | #else |
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| 178 | return 0; |
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| 179 | #endif |
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| 180 | } |
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| 181 | |
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[8ef3818] | 182 | /* |
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| 183 | * This function freezes the data cache; cache lines |
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| 184 | * are not replaced. |
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| 185 | */ |
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| 186 | void |
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[5e77d129] | 187 | rtems_cache_freeze_data( void ) |
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[8ef3818] | 188 | { |
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[5e77d129] | 189 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 190 | _CPU_cache_freeze_data(); |
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[cf1f72e] | 191 | #endif |
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[8ef3818] | 192 | } |
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| 193 | |
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[5e77d129] | 194 | void rtems_cache_unfreeze_data( void ) |
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[8ef3818] | 195 | { |
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[5e77d129] | 196 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 197 | _CPU_cache_unfreeze_data(); |
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[cf1f72e] | 198 | #endif |
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[8ef3818] | 199 | } |
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| 200 | |
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| 201 | void |
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[5e77d129] | 202 | rtems_cache_enable_data( void ) |
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[8ef3818] | 203 | { |
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[5e77d129] | 204 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 205 | _CPU_cache_enable_data(); |
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[cf1f72e] | 206 | #endif |
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[8ef3818] | 207 | } |
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| 208 | |
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| 209 | void |
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[5e77d129] | 210 | rtems_cache_disable_data( void ) |
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[8ef3818] | 211 | { |
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[5e77d129] | 212 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 213 | _CPU_cache_disable_data(); |
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[8ef3818] | 214 | #endif |
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[cf1f72e] | 215 | } |
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[8ef3818] | 216 | |
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| 217 | /* |
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[cf1f72e] | 218 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE |
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[8ef3818] | 219 | */ |
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| 220 | |
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[26c142e5] | 221 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ |
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| 222 | && defined(RTEMS_SMP) \ |
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| 223 | && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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| 224 | |
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[5bf0c1a] | 225 | typedef struct { |
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| 226 | const void *addr; |
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| 227 | size_t size; |
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| 228 | } smp_cache_area; |
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| 229 | |
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[26c142e5] | 230 | static void smp_cache_inst_inv(void *arg) |
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| 231 | { |
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| 232 | smp_cache_area *area = arg; |
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[ddbc3f8d] | 233 | |
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[26c142e5] | 234 | _CPU_cache_invalidate_instruction_range(area->addr, area->size); |
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| 235 | } |
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| 236 | |
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| 237 | static void smp_cache_inst_inv_all(void *arg) |
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| 238 | { |
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| 239 | _CPU_cache_invalidate_entire_instruction(); |
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| 240 | } |
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| 241 | |
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| 242 | #endif |
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[ddbc3f8d] | 243 | |
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[8ef3818] | 244 | /* |
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| 245 | * This function is responsible for performing an instruction cache |
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| 246 | * invalidate. It must determine how many cache lines need to be invalidated |
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| 247 | * and then perform the invalidations. |
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| 248 | */ |
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[26c142e5] | 249 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ |
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| 250 | && !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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[ddbc3f8d] | 251 | static void |
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[26c142e5] | 252 | _CPU_cache_invalidate_instruction_range( |
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[ddbc3f8d] | 253 | const void * i_addr, |
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| 254 | size_t n_bytes |
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| 255 | ) |
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[8ef3818] | 256 | { |
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[cf1f72e] | 257 | const void * final_address; |
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| 258 | |
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| 259 | /* |
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| 260 | * Set i_addr to the beginning of the cache line; final_address indicates |
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| 261 | * the last address_t which needs to be invalidated. Increment i_addr and |
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| 262 | * invalidate the resulting line until final_address is passed. |
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| 263 | */ |
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| 264 | |
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[d2978ee9] | 265 | if( n_bytes == 0 ) |
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| 266 | /* Do nothing if number of bytes to invalidate is zero */ |
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| 267 | return; |
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[359e537] | 268 | |
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[cf1f72e] | 269 | final_address = (void *)((size_t)i_addr + n_bytes - 1); |
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[5e77d129] | 270 | i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); |
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[fc6a0ae] | 271 | while( final_address >= i_addr ) { |
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[5e77d129] | 272 | _CPU_cache_invalidate_1_instruction_line( i_addr ); |
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| 273 | i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); |
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[cf1f72e] | 274 | } |
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[ddbc3f8d] | 275 | } |
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| 276 | #endif |
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| 277 | |
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| 278 | void |
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| 279 | rtems_cache_invalidate_multiple_instruction_lines( |
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| 280 | const void * i_addr, |
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| 281 | size_t n_bytes |
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| 282 | ) |
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| 283 | { |
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| 284 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 285 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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[26c142e5] | 286 | smp_cache_area area = { i_addr, n_bytes }; |
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[ddbc3f8d] | 287 | |
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[26c142e5] | 288 | _SMP_Multicast_action( 0, NULL, smp_cache_inst_inv, &area ); |
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[ddbc3f8d] | 289 | #else |
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[26c142e5] | 290 | _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); |
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[cf1f72e] | 291 | #endif |
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[2bd440e] | 292 | #endif |
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[8ef3818] | 293 | } |
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| 294 | |
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| 295 | /* |
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| 296 | * This function is responsible for performing an instruction cache |
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| 297 | * invalidate. It invalidates the entire cache. |
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| 298 | */ |
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| 299 | void |
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[5e77d129] | 300 | rtems_cache_invalidate_entire_instruction( void ) |
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[8ef3818] | 301 | { |
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[5e77d129] | 302 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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[ddbc3f8d] | 303 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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[26c142e5] | 304 | _SMP_Multicast_action( 0, NULL, smp_cache_inst_inv_all, NULL ); |
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[ddbc3f8d] | 305 | #else |
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[5e77d129] | 306 | _CPU_cache_invalidate_entire_instruction(); |
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[cf1f72e] | 307 | #endif |
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[ddbc3f8d] | 308 | #endif |
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[8ef3818] | 309 | } |
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| 310 | |
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| 311 | /* |
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| 312 | * This function returns the instruction cache granularity. |
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| 313 | */ |
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[e7549ff4] | 314 | size_t |
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[5e77d129] | 315 | rtems_cache_get_instruction_line_size( void ) |
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[8ef3818] | 316 | { |
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[5e77d129] | 317 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 318 | return CPU_INSTRUCTION_CACHE_ALIGNMENT; |
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[cf1f72e] | 319 | #else |
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| 320 | return 0; |
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| 321 | #endif |
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[8ef3818] | 322 | } |
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| 323 | |
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[e1d7bf0] | 324 | size_t |
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| 325 | rtems_cache_get_instruction_cache_size( uint32_t level ) |
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| 326 | { |
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| 327 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) |
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| 328 | return _CPU_cache_get_instruction_cache_size( level ); |
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| 329 | #else |
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| 330 | return 0; |
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| 331 | #endif |
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| 332 | } |
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| 333 | |
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[8ef3818] | 334 | /* |
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| 335 | * This function freezes the instruction cache; cache lines |
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| 336 | * are not replaced. |
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| 337 | */ |
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| 338 | void |
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[5e77d129] | 339 | rtems_cache_freeze_instruction( void ) |
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[8ef3818] | 340 | { |
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[5e77d129] | 341 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 342 | _CPU_cache_freeze_instruction(); |
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[cf1f72e] | 343 | #endif |
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[8ef3818] | 344 | } |
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| 345 | |
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[5e77d129] | 346 | void rtems_cache_unfreeze_instruction( void ) |
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[8ef3818] | 347 | { |
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[5e77d129] | 348 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 349 | _CPU_cache_unfreeze_instruction(); |
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[cf1f72e] | 350 | #endif |
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[8ef3818] | 351 | } |
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| 352 | |
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| 353 | void |
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[5e77d129] | 354 | rtems_cache_enable_instruction( void ) |
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[8ef3818] | 355 | { |
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[5e77d129] | 356 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 357 | _CPU_cache_enable_instruction(); |
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[cf1f72e] | 358 | #endif |
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[8ef3818] | 359 | } |
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| 360 | |
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| 361 | void |
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[5e77d129] | 362 | rtems_cache_disable_instruction( void ) |
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[8ef3818] | 363 | { |
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[5e77d129] | 364 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 365 | _CPU_cache_disable_instruction(); |
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[8ef3818] | 366 | #endif |
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[cf1f72e] | 367 | } |
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[0e507d55] | 368 | |
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| 369 | /* Returns the maximal cache line size of all cache kinds in bytes. */ |
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| 370 | size_t rtems_cache_get_maximal_line_size( void ) |
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| 371 | { |
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| 372 | #if defined(CPU_MAXIMAL_CACHE_ALIGNMENT) |
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| 373 | return CPU_MAXIMAL_CACHE_ALIGNMENT; |
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| 374 | #endif |
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| 375 | size_t max_line_size = 0; |
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| 376 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 377 | { |
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| 378 | size_t data_line_size = CPU_DATA_CACHE_ALIGNMENT; |
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| 379 | if ( max_line_size < data_line_size ) |
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| 380 | max_line_size = data_line_size; |
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| 381 | } |
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| 382 | #endif |
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| 383 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 384 | { |
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| 385 | size_t instruction_line_size = CPU_INSTRUCTION_CACHE_ALIGNMENT; |
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| 386 | if ( max_line_size < instruction_line_size ) |
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| 387 | max_line_size = instruction_line_size; |
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| 388 | } |
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| 389 | #endif |
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| 390 | return max_line_size; |
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| 391 | } |
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| 392 | |
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| 393 | /* |
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| 394 | * Purpose is to synchronize caches after code has been loaded |
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| 395 | * or self modified. Actual implementation is simple only |
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| 396 | * but it can and should be repaced by optimized version |
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| 397 | * which does not need flush and invalidate all cache levels |
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| 398 | * when code is changed. |
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| 399 | */ |
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[a6f70e1] | 400 | void rtems_cache_instruction_sync_after_code_change( |
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| 401 | const void *code_addr, |
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| 402 | size_t n_bytes |
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| 403 | ) |
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[0e507d55] | 404 | { |
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| 405 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION) |
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| 406 | _CPU_cache_instruction_sync_after_code_change( code_addr, n_bytes ); |
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| 407 | #else |
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| 408 | rtems_cache_flush_multiple_data_lines( code_addr, n_bytes ); |
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| 409 | rtems_cache_invalidate_multiple_instruction_lines( code_addr, n_bytes ); |
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| 410 | #endif |
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| 411 | } |
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