1 | /* |
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2 | * SH-7750 memory-mapped registers |
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3 | * This file based on information provided in the following document: |
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4 | * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S) |
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5 | * Hardware Manual" |
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6 | * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd. |
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7 | * |
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8 | * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia |
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9 | * Author: Alexandra Kossovsky <sasha@oktet.ru> |
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10 | * Victor V. Vengerov <vvv@oktet.ru> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/license/LICENSE. |
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15 | */ |
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16 | |
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17 | #ifndef __SH7750_REGS_H__ |
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18 | #define __SH7750_REGS_H__ |
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19 | |
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20 | /* |
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21 | * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and |
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22 | * in 0x1f000000 - 0x1fffffff (area 7 address) |
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23 | */ |
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24 | #define SH7750_P4_BASE 0xff000000 /* Accessable only in |
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25 | priveleged mode */ |
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26 | #define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */ |
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27 | |
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28 | #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs)) |
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29 | #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs)) |
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30 | |
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31 | /* |
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32 | * MMU Registers |
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33 | */ |
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34 | |
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35 | /* Page Table Entry High register - PTEH */ |
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36 | #define SH7750_PTEH_REGOFS 0x000000 /* offset */ |
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37 | #define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS) |
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38 | #define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS) |
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39 | #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */ |
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40 | #define SH7750_PTEH_VPN_S 10 |
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41 | #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */ |
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42 | #define SH7750_PTEH_ASID_S 0 |
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43 | |
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44 | /* Page Table Entry Low register - PTEL */ |
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45 | #define SH7750_PTEL_REGOFS 0x000004 /* offset */ |
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46 | #define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS) |
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47 | #define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS) |
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48 | #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */ |
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49 | #define SH7750_PTEL_PPN_S 10 |
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50 | #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */ |
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51 | #define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */ |
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52 | #define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */ |
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53 | #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */ |
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54 | #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */ |
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55 | #define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */ |
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56 | #define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */ |
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57 | #define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */ |
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58 | #define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */ |
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59 | #define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */ |
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60 | #define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode*/ |
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61 | #define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode*/ |
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62 | #define SH7750_PTEL_C 0x00000008 /* Cacheability |
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63 | (0 - page not cacheable) */ |
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64 | #define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been |
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65 | performed to a page) */ |
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66 | #define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are |
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67 | shared by processes) */ |
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68 | #define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the |
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69 | cache write mode: |
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70 | 0 - Copy-back mode |
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71 | 1 - Write-through mode */ |
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72 | |
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73 | /* Page Table Entry Assistance register - PTEA */ |
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74 | #define SH7750_PTEA_REGOFS 0x000034 /* offset */ |
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75 | #define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS) |
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76 | #define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS) |
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77 | #define SH7750_PTEA_TC 0x00000008 /* Timing Control bit |
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78 | 0 - use area 5 wait states |
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79 | 1 - use area 6 wait states */ |
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80 | #define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */ |
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81 | #define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */ |
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82 | #define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */ |
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83 | #define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */ |
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84 | #define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */ |
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85 | #define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space*/ |
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86 | #define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space*/ |
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87 | #define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */ |
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88 | #define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */ |
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89 | |
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90 | |
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91 | /* Translation table base register */ |
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92 | #define SH7750_TTB_REGOFS 0x000008 /* offset */ |
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93 | #define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS) |
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94 | #define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS) |
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95 | |
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96 | /* TLB exeption address register - TEA */ |
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97 | #define SH7750_TEA_REGOFS 0x00000c /* offset */ |
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98 | #define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS) |
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99 | #define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS) |
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100 | |
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101 | /* MMU control register - MMUCR */ |
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102 | #define SH7750_MMUCR_REGOFS 0x000010 /* offset */ |
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103 | #define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS) |
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104 | #define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS) |
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105 | #define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */ |
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106 | #define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */ |
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107 | #define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */ |
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108 | #define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */ |
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109 | #define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */ |
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110 | #define SH7750_MMUCR_URC_S 10 |
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111 | #define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */ |
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112 | #define SH7750_MMUCR_URB_S 18 |
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113 | #define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */ |
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114 | #define SH7750_MMUCR_LRUI_S 26 |
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115 | |
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116 | |
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117 | |
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118 | |
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119 | /* |
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120 | * Cache registers |
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121 | * IC -- instructions cache |
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122 | * OC -- operand cache |
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123 | */ |
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124 | |
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125 | /* Cache Control Register - CCR */ |
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126 | #define SH7750_CCR_REGOFS 0x00001c /* offset */ |
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127 | #define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS) |
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128 | #define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS) |
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129 | |
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130 | #define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */ |
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131 | #define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: |
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132 | set it to clear IC */ |
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133 | #define SH7750_CCR_ICE 0x00000100 /* IC enable bit */ |
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134 | #define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */ |
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135 | #define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit |
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136 | if you set OCE = 0, |
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137 | you should set ORA = 0 */ |
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138 | #define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */ |
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139 | #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */ |
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140 | #define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */ |
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141 | #define SH7750_CCR_OCE 0x00000001 /* OC enable bit */ |
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142 | |
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143 | /* Queue address control register 0 - QACR0 */ |
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144 | #define SH7750_QACR0_REGOFS 0x000038 /* offset */ |
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145 | #define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS) |
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146 | #define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS) |
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147 | |
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148 | /* Queue address control register 1 - QACR1 */ |
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149 | #define SH7750_QACR1_REGOFS 0x00003c /* offset */ |
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150 | #define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS) |
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151 | #define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS) |
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152 | |
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153 | |
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154 | /* |
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155 | * Exeption-related registers |
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156 | */ |
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157 | |
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158 | /* Immediate data for TRAPA instuction - TRA */ |
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159 | #define SH7750_TRA_REGOFS 0x000020 /* offset */ |
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160 | #define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS) |
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161 | #define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS) |
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162 | |
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163 | #define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */ |
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164 | #define SH7750_TRA_IMM_S 2 |
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165 | |
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166 | /* Exeption event register - EXPEVT */ |
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167 | #define SH7750_EXPEVT_REGOFS 0x000024 |
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168 | #define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS) |
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169 | #define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS) |
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170 | |
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171 | #define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */ |
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172 | #define SH7750_EXPEVT_EX_S 0 |
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173 | |
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174 | /* Interrupt event register */ |
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175 | #define SH7750_INTEVT_REGOFS 0x000028 |
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176 | #define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS) |
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177 | #define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS) |
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178 | #define SH7750_INTEVT_EX 0x00000fff /* Exeption code */ |
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179 | #define SH7750_INTEVT_EX_S 0 |
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180 | |
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181 | /* |
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182 | * Exception/interrupt codes |
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183 | */ |
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184 | #define SH7750_EVT_TO_NUM(evt) ((evt) >> 5) |
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185 | |
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186 | /* Reset exception category */ |
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187 | #define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */ |
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188 | #define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */ |
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189 | #define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */ |
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190 | |
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191 | /* General exception category */ |
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192 | #define SH7750_EVT_USER_BREAK 0x1E0 /* User break */ |
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193 | #define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */ |
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194 | #define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception / |
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195 | DTLB miss exception (read) */ |
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196 | #define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation / |
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197 | DTLB protection violation (read)*/ |
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198 | #define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction |
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199 | exception */ |
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200 | #define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction |
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201 | exception */ |
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202 | #define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception*/ |
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203 | #define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */ |
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204 | #define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */ |
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205 | #define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */ |
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206 | #define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */ |
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207 | #define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation |
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208 | exception (write) */ |
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209 | #define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */ |
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210 | #define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */ |
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211 | #define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ |
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212 | |
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213 | /* Interrupt exception category */ |
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214 | #define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */ |
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215 | #define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */ |
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216 | #define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */ |
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217 | #define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */ |
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218 | #define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */ |
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219 | #define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */ |
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220 | #define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */ |
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221 | #define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */ |
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222 | #define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */ |
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223 | #define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */ |
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224 | #define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */ |
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225 | #define SH7750_EVT_IRQA 0x340 /* External Interrupt A */ |
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226 | #define SH7750_EVT_IRQB 0x360 /* External Interrupt B */ |
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227 | #define SH7750_EVT_IRQC 0x380 /* External Interrupt C */ |
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228 | #define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */ |
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229 | #define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */ |
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230 | |
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231 | /* Peripheral Module Interrupts - Timer Unit (TMU) */ |
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232 | #define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */ |
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233 | #define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */ |
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234 | #define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */ |
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235 | #define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2*/ |
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236 | |
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237 | /* Peripheral Module Interrupts - Real-Time Clock (RTC) */ |
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238 | #define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */ |
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239 | #define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */ |
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240 | #define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */ |
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241 | |
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242 | /* Peripheral Module Interrupts - Serial Communication Interface (SCI) */ |
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243 | #define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */ |
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244 | #define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */ |
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245 | #define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */ |
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246 | #define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */ |
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247 | |
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248 | /* Peripheral Module Interrupts - Watchdog Timer (WDT) */ |
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249 | #define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt |
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250 | (used when WDT operates in |
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251 | interval timer mode) */ |
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252 | |
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253 | /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */ |
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254 | #define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */ |
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255 | #define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow |
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256 | interrupt */ |
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257 | |
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258 | /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */ |
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259 | #define SH7750_EVT_HUDI 0x600 /* UDI interrupt */ |
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260 | |
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261 | /* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */ |
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262 | #define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */ |
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263 | |
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264 | /* Peripheral Module Interrupts - DMA Controller (DMAC) */ |
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265 | #define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt*/ |
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266 | #define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt*/ |
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267 | #define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt*/ |
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268 | #define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt*/ |
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269 | #define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */ |
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270 | |
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271 | /* Peripheral Module Interrupts - Serial Communication Interface with FIFO */ |
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272 | /* (SCIF) */ |
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273 | #define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */ |
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274 | #define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or |
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275 | Receive Data ready interrupt */ |
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276 | #define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */ |
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277 | #define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */ |
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278 | |
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279 | /* |
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280 | * Power Management |
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281 | */ |
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282 | #define SH7750_STBCR_REGOFS 0xC00004 /* offset */ |
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283 | #define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS) |
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284 | #define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS) |
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285 | |
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286 | #define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode: |
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287 | 0 - Transition to SLEEP mode on SLEEP |
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288 | 1 - Transition to STANDBY mode on SLEEP*/ |
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289 | #define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in |
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290 | standby mode: |
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291 | 0 - normal state |
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292 | 1 - high-impendance state */ |
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293 | |
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294 | #define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls*/ |
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295 | #define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */ |
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296 | #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4 |
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297 | #define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */ |
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298 | #define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3 |
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299 | #define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */ |
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300 | #define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2 |
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301 | #define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */ |
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302 | #define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1 |
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303 | #define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */ |
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304 | #define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0 |
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305 | |
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306 | #define SH7750_STBCR_STBY 0x80 |
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307 | |
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308 | |
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309 | #define SH7750_STBCR2_REGOFS 0xC00010 /* offset */ |
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310 | #define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS) |
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311 | #define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS) |
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312 | |
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313 | #define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode: |
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314 | 0 - transition to sleep or standby mode |
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315 | as it is specified in STBY bit |
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316 | 1 - transition to deep sleep mode on |
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317 | execution of SLEEP instruction */ |
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318 | #define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to Store Queue |
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319 | in the cache controller */ |
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320 | #define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6 |
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321 | #define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the User |
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322 | Break Controller (UBC) */ |
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323 | #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5 |
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324 | |
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325 | /* |
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326 | * Clock Pulse Generator (CPG) |
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327 | */ |
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328 | #define SH7750_FRQCR_REGOFS 0xC00000 /* offset */ |
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329 | #define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS) |
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330 | #define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS) |
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331 | |
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332 | #define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable |
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333 | 0 - CKIO pin goes to HiZ/pullup |
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334 | 1 - Clock is output from CKIO */ |
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335 | #define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */ |
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336 | #define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */ |
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337 | |
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338 | #define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */ |
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339 | #define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */ |
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340 | #define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */ |
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341 | #define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */ |
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342 | #define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */ |
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343 | #define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */ |
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344 | #define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */ |
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345 | |
---|
346 | #define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */ |
---|
347 | #define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */ |
---|
348 | #define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */ |
---|
349 | #define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */ |
---|
350 | #define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */ |
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351 | #define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */ |
---|
352 | #define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */ |
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353 | |
---|
354 | #define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency |
---|
355 | division ratio: */ |
---|
356 | #define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */ |
---|
357 | #define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */ |
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358 | #define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */ |
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359 | #define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */ |
---|
360 | #define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */ |
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361 | |
---|
362 | /* |
---|
363 | * Watchdog Timer (WDT) |
---|
364 | */ |
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365 | |
---|
366 | /* Watchdog Timer Counter register - WTCNT */ |
---|
367 | #define SH7750_WTCNT_REGOFS 0xC00008 /* offset */ |
---|
368 | #define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS) |
---|
369 | #define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS) |
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370 | #define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written, |
---|
371 | you have to set the upper byte to |
---|
372 | 0x5A */ |
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373 | |
---|
374 | /* Watchdog Timer Control/Status register - WTCSR */ |
---|
375 | #define SH7750_WTCSR_REGOFS 0xC0000C /* offset */ |
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376 | #define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS) |
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377 | #define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS) |
---|
378 | #define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written, |
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379 | you have to set the upper byte to |
---|
380 | 0xA5 */ |
---|
381 | #define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */ |
---|
382 | #define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */ |
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383 | #define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */ |
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384 | #define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */ |
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385 | #define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */ |
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386 | #define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */ |
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387 | #define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */ |
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388 | #define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */ |
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389 | #define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */ |
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390 | #define SH7750_WTCSR_CKS 0x07 /* Clock Select: */ |
---|
391 | #define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */ |
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392 | #define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */ |
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393 | #define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */ |
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394 | #define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */ |
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395 | #define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */ |
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396 | #define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */ |
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397 | #define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */ |
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398 | #define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */ |
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399 | |
---|
400 | /* |
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401 | * Real-Time Clock (RTC) |
---|
402 | */ |
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403 | /* 64-Hz Counter Register (byte, read-only) - R64CNT */ |
---|
404 | #define SH7750_R64CNT_REGOFS 0xC80000 /* offset */ |
---|
405 | #define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS) |
---|
406 | #define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS) |
---|
407 | |
---|
408 | /* Second Counter Register (byte, BCD-coded) - RSECCNT */ |
---|
409 | #define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */ |
---|
410 | #define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS) |
---|
411 | #define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS) |
---|
412 | |
---|
413 | /* Minute Counter Register (byte, BCD-coded) - RMINCNT */ |
---|
414 | #define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */ |
---|
415 | #define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS) |
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416 | #define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS) |
---|
417 | |
---|
418 | /* Hour Counter Register (byte, BCD-coded) - RHRCNT */ |
---|
419 | #define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */ |
---|
420 | #define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS) |
---|
421 | #define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS) |
---|
422 | |
---|
423 | /* Day-of-Week Counter Register (byte) - RWKCNT */ |
---|
424 | #define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */ |
---|
425 | #define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS) |
---|
426 | #define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS) |
---|
427 | |
---|
428 | #define SH7750_RWKCNT_SUN 0 /* Sunday */ |
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429 | #define SH7750_RWKCNT_MON 1 /* Monday */ |
---|
430 | #define SH7750_RWKCNT_TUE 2 /* Tuesday */ |
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431 | #define SH7750_RWKCNT_WED 3 /* Wednesday */ |
---|
432 | #define SH7750_RWKCNT_THU 4 /* Thursday */ |
---|
433 | #define SH7750_RWKCNT_FRI 5 /* Friday */ |
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434 | #define SH7750_RWKCNT_SAT 6 /* Saturday */ |
---|
435 | |
---|
436 | /* Day Counter Register (byte, BCD-coded) - RDAYCNT */ |
---|
437 | #define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */ |
---|
438 | #define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS) |
---|
439 | #define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS) |
---|
440 | |
---|
441 | /* Month Counter Register (byte, BCD-coded) - RMONCNT */ |
---|
442 | #define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */ |
---|
443 | #define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS) |
---|
444 | #define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS) |
---|
445 | |
---|
446 | /* Year Counter Register (half, BCD-coded) - RYRCNT */ |
---|
447 | #define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */ |
---|
448 | #define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS) |
---|
449 | #define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS) |
---|
450 | |
---|
451 | /* Second Alarm Register (byte, BCD-coded) - RSECAR */ |
---|
452 | #define SH7750_RSECAR_REGOFS 0xC80020 /* offset */ |
---|
453 | #define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS) |
---|
454 | #define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS) |
---|
455 | #define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */ |
---|
456 | |
---|
457 | /* Minute Alarm Register (byte, BCD-coded) - RMINAR */ |
---|
458 | #define SH7750_RMINAR_REGOFS 0xC80024 /* offset */ |
---|
459 | #define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS) |
---|
460 | #define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS) |
---|
461 | #define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */ |
---|
462 | |
---|
463 | /* Hour Alarm Register (byte, BCD-coded) - RHRAR */ |
---|
464 | #define SH7750_RHRAR_REGOFS 0xC80028 /* offset */ |
---|
465 | #define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS) |
---|
466 | #define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS) |
---|
467 | #define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */ |
---|
468 | |
---|
469 | /* Day-of-Week Alarm Register (byte) - RWKAR */ |
---|
470 | #define SH7750_RWKAR_REGOFS 0xC8002C /* offset */ |
---|
471 | #define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS) |
---|
472 | #define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS) |
---|
473 | #define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */ |
---|
474 | |
---|
475 | #define SH7750_RWKAR_SUN 0 /* Sunday */ |
---|
476 | #define SH7750_RWKAR_MON 1 /* Monday */ |
---|
477 | #define SH7750_RWKAR_TUE 2 /* Tuesday */ |
---|
478 | #define SH7750_RWKAR_WED 3 /* Wednesday */ |
---|
479 | #define SH7750_RWKAR_THU 4 /* Thursday */ |
---|
480 | #define SH7750_RWKAR_FRI 5 /* Friday */ |
---|
481 | #define SH7750_RWKAR_SAT 6 /* Saturday */ |
---|
482 | |
---|
483 | /* Day Alarm Register (byte, BCD-coded) - RDAYAR */ |
---|
484 | #define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */ |
---|
485 | #define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS) |
---|
486 | #define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS) |
---|
487 | #define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */ |
---|
488 | |
---|
489 | /* Month Counter Register (byte, BCD-coded) - RMONAR */ |
---|
490 | #define SH7750_RMONAR_REGOFS 0xC80034 /* offset */ |
---|
491 | #define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS) |
---|
492 | #define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS) |
---|
493 | #define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */ |
---|
494 | |
---|
495 | /* RTC Control Register 1 (byte) - RCR1 */ |
---|
496 | #define SH7750_RCR1_REGOFS 0xC80038 /* offset */ |
---|
497 | #define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS) |
---|
498 | #define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS) |
---|
499 | #define SH7750_RCR1_CF 0x80 /* Carry Flag */ |
---|
500 | #define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */ |
---|
501 | #define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */ |
---|
502 | #define SH7750_RCR1_AF 0x01 /* Alarm Flag */ |
---|
503 | |
---|
504 | /* RTC Control Register 2 (byte) - RCR2 */ |
---|
505 | #define SH7750_RCR2_REGOFS 0xC8003C /* offset */ |
---|
506 | #define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS) |
---|
507 | #define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS) |
---|
508 | #define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */ |
---|
509 | #define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */ |
---|
510 | #define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */ |
---|
511 | #define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */ |
---|
512 | #define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */ |
---|
513 | #define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */ |
---|
514 | #define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */ |
---|
515 | #define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */ |
---|
516 | #define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */ |
---|
517 | #define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */ |
---|
518 | #define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */ |
---|
519 | #define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */ |
---|
520 | #define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset*/ |
---|
521 | #define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month, |
---|
522 | year counters are stopped |
---|
523 | 1 - sec, min, hr, day-of-week, month, |
---|
524 | year counters operate normally */ |
---|
525 | |
---|
526 | |
---|
527 | /* |
---|
528 | * Timer Unit (TMU) |
---|
529 | */ |
---|
530 | /* Timer Output Control Register (byte) - TOCR */ |
---|
531 | #define SH7750_TOCR_REGOFS 0xD80000 /* offset */ |
---|
532 | #define SH7750_TOCR SH7750_P4_REG32(SH7750_TOCR_REGOFS) |
---|
533 | #define SH7750_TOCR_A7 SH7750_A7_REG32(SH7750_TOCR_REGOFS) |
---|
534 | #define SH7750_TOCR_TCOE 0x01 /* Timer Clock Pin Control: |
---|
535 | 0 - TCLK is used as external clock |
---|
536 | input or input capture control |
---|
537 | 1 - TCLK is used as on-chip RTC |
---|
538 | output clock pin */ |
---|
539 | |
---|
540 | /* Timer Start Register (byte) - TSTR */ |
---|
541 | #define SH7750_TSTR_REGOFS 0xD80004 /* offset */ |
---|
542 | #define SH7750_TSTR SH7750_P4_REG32(SH7750_TSTR_REGOFS) |
---|
543 | #define SH7750_TSTR_A7 SH7750_A7_REG32(SH7750_TSTR_REGOFS) |
---|
544 | #define SH7750_TSTR_STR2 0x04 /* TCNT2 performs count operations */ |
---|
545 | #define SH7750_TSTR_STR1 0x02 /* TCNT1 performs count operations */ |
---|
546 | #define SH7750_TSTR_STR0 0x01 /* TCNT0 performs count operations */ |
---|
547 | #define SH7750_TSTR_STR(n) (1 << (n)) |
---|
548 | |
---|
549 | /* Timer Constant Register - TCOR0, TCOR1, TCOR2 */ |
---|
550 | #define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12)) /* offset */ |
---|
551 | #define SH7750_TCOR(n) SH7750_P4_REG32(SH7750_TCOR_REGOFS(n)) |
---|
552 | #define SH7750_TCOR_A7(n) SH7750_A7_REG32(SH7750_TCOR_REGOFS(n)) |
---|
553 | #define SH7750_TCOR0 SH7750_TCOR(0) |
---|
554 | #define SH7750_TCOR1 SH7750_TCOR(1) |
---|
555 | #define SH7750_TCOR2 SH7750_TCOR(2) |
---|
556 | #define SH7750_TCOR0_A7 SH7750_TCOR_A7(0) |
---|
557 | #define SH7750_TCOR1_A7 SH7750_TCOR_A7(1) |
---|
558 | #define SH7750_TCOR2_A7 SH7750_TCOR_A7(2) |
---|
559 | |
---|
560 | /* Timer Counter Register - TCNT0, TCNT1, TCNT2 */ |
---|
561 | #define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12)) /* offset */ |
---|
562 | #define SH7750_TCNT(n) SH7750_P4_REG32(SH7750_TCNT_REGOFS(n)) |
---|
563 | #define SH7750_TCNT_A7(n) SH7750_A7_REG32(SH7750_TCNT_REGOFS(n)) |
---|
564 | #define SH7750_TCNT0 SH7750_TCNT(0) |
---|
565 | #define SH7750_TCNT1 SH7750_TCNT(1) |
---|
566 | #define SH7750_TCNT2 SH7750_TCNT(2) |
---|
567 | #define SH7750_TCNT0_A7 SH7750_TCNT_A7(0) |
---|
568 | #define SH7750_TCNT1_A7 SH7750_TCNT_A7(1) |
---|
569 | #define SH7750_TCNT2_A7 SH7750_TCNT_A7(2) |
---|
570 | |
---|
571 | /* Timer Control Register (half) - TCR0, TCR1, TCR2 */ |
---|
572 | #define SH7750_TCR_REGOFS(n) (0xD80010 + ((n)*12)) /* offset */ |
---|
573 | #define SH7750_TCR(n) SH7750_P4_REG32(SH7750_TCR_REGOFS(n)) |
---|
574 | #define SH7750_TCR_A7(n) SH7750_A7_REG32(SH7750_TCR_REGOFS(n)) |
---|
575 | #define SH7750_TCR0 SH7750_TCR(0) |
---|
576 | #define SH7750_TCR1 SH7750_TCR(1) |
---|
577 | #define SH7750_TCR2 SH7750_TCR(2) |
---|
578 | #define SH7750_TCR0_A7 SH7750_TCR_A7(0) |
---|
579 | #define SH7750_TCR1_A7 SH7750_TCR_A7(1) |
---|
580 | #define SH7750_TCR2_A7 SH7750_TCR_A7(2) |
---|
581 | |
---|
582 | #define SH7750_TCR2_ICPF 0x200 /* Input Capture Interrupt Flag |
---|
583 | (1 - input capture has occured) */ |
---|
584 | #define SH7750_TCR_UNF 0x100 /* Underflow flag */ |
---|
585 | #define SH7750_TCR2_ICPE 0x0C0 /* Input Capture Control: */ |
---|
586 | #define SH7750_TCR2_ICPE_DIS 0x000 /* Input Capture function is not used*/ |
---|
587 | #define SH7750_TCR2_ICPE_NOINT 0x080 /* Input Capture function is used, but |
---|
588 | input capture interrupt is not |
---|
589 | enabled */ |
---|
590 | #define SH7750_TCR2_ICPE_INT 0x0C0 /* Input Capture function is used, |
---|
591 | input capture interrupt enabled */ |
---|
592 | #define SH7750_TCR_UNIE 0x020 /* Underflow Interrupt Control |
---|
593 | (1 - underflow interrupt enabled) */ |
---|
594 | #define SH7750_TCR_CKEG 0x018 /* Clock Edge selection: */ |
---|
595 | #define SH7750_TCR_CKEG_RAISE 0x000 /* Count/capture on rising edge */ |
---|
596 | #define SH7750_TCR_CKEG_FALL 0x008 /* Count/capture on falling edge */ |
---|
597 | #define SH7750_TCR_CKEG_BOTH 0x018 /* Count/capture on both rising and |
---|
598 | falling edges */ |
---|
599 | #define SH7750_TCR_TPSC 0x007 /* Timer prescaler */ |
---|
600 | #define SH7750_TCR_TPSC_DIV4 0x000 /* Counts on peripheral clock/4 */ |
---|
601 | #define SH7750_TCR_TPSC_DIV16 0x001 /* Counts on peripheral clock/16 */ |
---|
602 | #define SH7750_TCR_TPSC_DIV64 0x002 /* Counts on peripheral clock/64 */ |
---|
603 | #define SH7750_TCR_TPSC_DIV256 0x003 /* Counts on peripheral clock/256 */ |
---|
604 | #define SH7750_TCR_TPSC_DIV1024 0x004 /* Counts on peripheral clock/1024 */ |
---|
605 | #define SH7750_TCR_TPSC_RTC 0x006 /* Counts on on-chip RTC output clk*/ |
---|
606 | #define SH7750_TCR_TPSC_EXT 0x007 /* Counts on external clock */ |
---|
607 | |
---|
608 | /* Input Capture Register (read-only) - TCPR2 */ |
---|
609 | #define SH7750_TCPR2_REGOFS 0xD8002C /* offset */ |
---|
610 | #define SH7750_TCPR2 SH7750_P4_REG32(SH7750_TCPR2_REGOFS) |
---|
611 | #define SH7750_TCPR2_A7 SH7750_A7_REG32(SH7750_TCPR2_REGOFS) |
---|
612 | |
---|
613 | /* |
---|
614 | * Bus State Controller - BSC |
---|
615 | */ |
---|
616 | /* Bus Control Register 1 - BCR1 */ |
---|
617 | #define SH7750_BCR1_REGOFS 0x800000 /* offset */ |
---|
618 | #define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS) |
---|
619 | #define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS) |
---|
620 | #define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */ |
---|
621 | #define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */ |
---|
622 | #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ |
---|
623 | #define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: |
---|
624 | 0 - pull-up resistor is on for |
---|
625 | control input pins |
---|
626 | 1 - pull-up resistor is off */ |
---|
627 | #define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control: |
---|
628 | 0 - pull-up resistor is on for |
---|
629 | control output pins |
---|
630 | 1 - pull-up resistor is off */ |
---|
631 | #define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: |
---|
632 | 0 - Area 1 SRAM is set to |
---|
633 | normal mode |
---|
634 | 1 - Area 1 SRAM is set to byte |
---|
635 | control mode */ |
---|
636 | #define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: |
---|
637 | 0 - Area 4 SRAM is set to |
---|
638 | normal mode |
---|
639 | 1 - Area 4 SRAM is set to byte |
---|
640 | control mode */ |
---|
641 | #define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable: |
---|
642 | 0 - External requests are not |
---|
643 | accepted |
---|
644 | 1 - External requests are |
---|
645 | accepted */ |
---|
646 | #define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit: |
---|
647 | 0 - Master Mode |
---|
648 | 1 - Partial-sharing Mode */ |
---|
649 | #define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: |
---|
650 | 0 - SRAM/burst ROM interface |
---|
651 | 1 - MPX interface */ |
---|
652 | #define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. Specifies |
---|
653 | the state of A[25:0], BS\, CSn\, |
---|
654 | RD/WR\, CE2A\, CE2B\ in standby |
---|
655 | mode and when bus is released: |
---|
656 | 0 - signals go to High-Z mode |
---|
657 | 1 - signals driven */ |
---|
658 | #define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. Specifies |
---|
659 | the state of the RAS\, RAS2\, WEn\, |
---|
660 | CASn\, DQMn, RD\, CASS\, FRAME\, |
---|
661 | RD2\ signals in standby mode and |
---|
662 | when bus is released: |
---|
663 | 0 - signals go to High-Z mode |
---|
664 | 1 - signals driven */ |
---|
665 | #define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */ |
---|
666 | #define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */ |
---|
667 | #define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM |
---|
668 | interface, 4 cosequtive access*/ |
---|
669 | #define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM |
---|
670 | interface, 8 cosequtive access*/ |
---|
671 | #define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM |
---|
672 | interface, 16 cosequtive access*/ |
---|
673 | #define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM |
---|
674 | interface, 32 cosequtive access*/ |
---|
675 | |
---|
676 | #define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */ |
---|
677 | #define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */ |
---|
678 | #define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM |
---|
679 | interface, 4 cosequtive access*/ |
---|
680 | #define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM |
---|
681 | interface, 8 cosequtive access*/ |
---|
682 | #define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM |
---|
683 | interface, 16 cosequtive access*/ |
---|
684 | #define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM |
---|
685 | interface, 32 cosequtive access*/ |
---|
686 | |
---|
687 | #define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */ |
---|
688 | #define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */ |
---|
689 | #define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM |
---|
690 | interface, 4 cosequtive access*/ |
---|
691 | #define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM |
---|
692 | interface, 8 cosequtive access*/ |
---|
693 | #define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM |
---|
694 | interface, 16 cosequtive access*/ |
---|
695 | #define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM |
---|
696 | interface, 32 cosequtive access*/ |
---|
697 | |
---|
698 | #define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */ |
---|
699 | #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or MPX |
---|
700 | interface. */ |
---|
701 | #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 - |
---|
702 | synchronous DRAM */ |
---|
703 | #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are synchronous |
---|
704 | DRAM interface */ |
---|
705 | #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 - |
---|
706 | DRAM interface */ |
---|
707 | #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM |
---|
708 | interface */ |
---|
709 | |
---|
710 | #define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type: |
---|
711 | 0 - SRAM interface |
---|
712 | 1 - PCMCIA interface */ |
---|
713 | |
---|
714 | /* Bus Control Register 2 (half) - BCR2 */ |
---|
715 | #define SH7750_BCR2_REGOFS 0x800004 /* offset */ |
---|
716 | #define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS) |
---|
717 | #define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS) |
---|
718 | |
---|
719 | #define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */ |
---|
720 | #define SH7750_BCR2_A0SZ_S 14 |
---|
721 | #define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */ |
---|
722 | #define SH7750_BCR2_A6SZ_S 12 |
---|
723 | #define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */ |
---|
724 | #define SH7750_BCR2_A5SZ_S 10 |
---|
725 | #define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */ |
---|
726 | #define SH7750_BCR2_A4SZ_S 8 |
---|
727 | #define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */ |
---|
728 | #define SH7750_BCR2_A3SZ_S 6 |
---|
729 | #define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */ |
---|
730 | #define SH7750_BCR2_A2SZ_S 4 |
---|
731 | #define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */ |
---|
732 | #define SH7750_BCR2_A1SZ_S 2 |
---|
733 | #define SH7750_BCR2_SZ_64 0 /* 64 bits */ |
---|
734 | #define SH7750_BCR2_SZ_8 1 /* 8 bits */ |
---|
735 | #define SH7750_BCR2_SZ_16 2 /* 16 bits */ |
---|
736 | #define SH7750_BCR2_SZ_32 3 /* 32 bits */ |
---|
737 | #define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable : |
---|
738 | 0 - D51-D32 are not used as a port |
---|
739 | 1 - D51-D32 are used as a port */ |
---|
740 | |
---|
741 | /* Wait Control Register 1 - WCR1 */ |
---|
742 | #define SH7750_WCR1_REGOFS 0x800008 /* offset */ |
---|
743 | #define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS) |
---|
744 | #define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS) |
---|
745 | #define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle |
---|
746 | specification */ |
---|
747 | #define SH7750_WCR1_DMAIW_S 28 |
---|
748 | #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */ |
---|
749 | #define SH7750_WCR1_A6IW_S 24 |
---|
750 | #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */ |
---|
751 | #define SH7750_WCR1_A5IW_S 20 |
---|
752 | #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */ |
---|
753 | #define SH7750_WCR1_A4IW_S 16 |
---|
754 | #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */ |
---|
755 | #define SH7750_WCR1_A3IW_S 12 |
---|
756 | #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */ |
---|
757 | #define SH7750_WCR1_A2IW_S 8 |
---|
758 | #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */ |
---|
759 | #define SH7750_WCR1_A1IW_S 4 |
---|
760 | #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */ |
---|
761 | #define SH7750_WCR1_A0IW_S 0 |
---|
762 | |
---|
763 | /* Wait Control Register 2 - WCR2 */ |
---|
764 | #define SH7750_WCR2_REGOFS 0x80000C /* offset */ |
---|
765 | #define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS) |
---|
766 | #define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS) |
---|
767 | |
---|
768 | #define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */ |
---|
769 | #define SH7750_WCR2_A6W_S 29 |
---|
770 | #define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */ |
---|
771 | #define SH7750_WCR2_A6B_S 26 |
---|
772 | #define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */ |
---|
773 | #define SH7750_WCR2_A5W_S 23 |
---|
774 | #define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */ |
---|
775 | #define SH7750_WCR2_A5B_S 20 |
---|
776 | #define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */ |
---|
777 | #define SH7750_WCR2_A4W_S 17 |
---|
778 | #define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */ |
---|
779 | #define SH7750_WCR2_A3W_S 13 |
---|
780 | #define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */ |
---|
781 | #define SH7750_WCR2_A2W_S 9 |
---|
782 | #define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */ |
---|
783 | #define SH7750_WCR2_A1W_S 6 |
---|
784 | #define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */ |
---|
785 | #define SH7750_WCR2_A0W_S 3 |
---|
786 | #define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */ |
---|
787 | #define SH7750_WCR2_A0B_S 0 |
---|
788 | |
---|
789 | #define SH7750_WCR2_WS0 0 /* 0 wait states inserted */ |
---|
790 | #define SH7750_WCR2_WS1 1 /* 1 wait states inserted */ |
---|
791 | #define SH7750_WCR2_WS2 2 /* 2 wait states inserted */ |
---|
792 | #define SH7750_WCR2_WS3 3 /* 3 wait states inserted */ |
---|
793 | #define SH7750_WCR2_WS6 4 /* 6 wait states inserted */ |
---|
794 | #define SH7750_WCR2_WS9 5 /* 9 wait states inserted */ |
---|
795 | #define SH7750_WCR2_WS12 6 /* 12 wait states inserted */ |
---|
796 | #define SH7750_WCR2_WS15 7 /* 15 wait states inserted */ |
---|
797 | |
---|
798 | #define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */ |
---|
799 | #define SH7750_WCR2_BPWS1 1 /* 1 wait states inserted from 2nd access */ |
---|
800 | #define SH7750_WCR2_BPWS2 2 /* 2 wait states inserted from 2nd access */ |
---|
801 | #define SH7750_WCR2_BPWS3 3 /* 3 wait states inserted from 2nd access */ |
---|
802 | #define SH7750_WCR2_BPWS4 4 /* 4 wait states inserted from 2nd access */ |
---|
803 | #define SH7750_WCR2_BPWS5 5 /* 5 wait states inserted from 2nd access */ |
---|
804 | #define SH7750_WCR2_BPWS6 6 /* 6 wait states inserted from 2nd access */ |
---|
805 | #define SH7750_WCR2_BPWS7 7 /* 7 wait states inserted from 2nd access */ |
---|
806 | |
---|
807 | /* DRAM CAS\ Assertion Delay (area 3,2) */ |
---|
808 | #define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */ |
---|
809 | #define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */ |
---|
810 | #define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */ |
---|
811 | #define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */ |
---|
812 | #define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */ |
---|
813 | #define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */ |
---|
814 | #define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */ |
---|
815 | #define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */ |
---|
816 | |
---|
817 | /* SDRAM CAS\ Latency Cycles */ |
---|
818 | #define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */ |
---|
819 | #define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */ |
---|
820 | #define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */ |
---|
821 | #define SH7750_WCR2_SDRAM_CAS_LAT4 4 /* 4 cycles */ |
---|
822 | #define SH7750_WCR2_SDRAM_CAS_LAT5 5 /* 5 cycles */ |
---|
823 | |
---|
824 | /* Wait Control Register 3 - WCR3 */ |
---|
825 | #define SH7750_WCR3_REGOFS 0x800010 /* offset */ |
---|
826 | #define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS) |
---|
827 | #define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS) |
---|
828 | |
---|
829 | #define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */ |
---|
830 | #define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */ |
---|
831 | #define SH7750_WCR3_A6H_S 24 |
---|
832 | #define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */ |
---|
833 | #define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */ |
---|
834 | #define SH7750_WCR3_A5H_S 20 |
---|
835 | #define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */ |
---|
836 | #define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */ |
---|
837 | #define SH7750_WCR3_A4H_S 16 |
---|
838 | #define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */ |
---|
839 | #define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */ |
---|
840 | #define SH7750_WCR3_A3H_S 12 |
---|
841 | #define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */ |
---|
842 | #define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */ |
---|
843 | #define SH7750_WCR3_A2H_S 8 |
---|
844 | #define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */ |
---|
845 | #define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */ |
---|
846 | #define SH7750_WCR3_A1H_S 4 |
---|
847 | #define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */ |
---|
848 | #define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */ |
---|
849 | #define SH7750_WCR3_A0H_S 0 |
---|
850 | |
---|
851 | #define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */ |
---|
852 | #define SH7750_WCR3_DHWS_1 1 /* 1 wait states data hold time */ |
---|
853 | #define SH7750_WCR3_DHWS_2 2 /* 2 wait states data hold time */ |
---|
854 | #define SH7750_WCR3_DHWS_3 3 /* 3 wait states data hold time */ |
---|
855 | |
---|
856 | #define SH7750_MCR_REGOFS 0x800014 /* offset */ |
---|
857 | #define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS) |
---|
858 | #define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS) |
---|
859 | |
---|
860 | #define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */ |
---|
861 | #define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */ |
---|
862 | #define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */ |
---|
863 | #define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of |
---|
864 | Refresh: */ |
---|
865 | #define SH7750_MCR_TRC_0 0x00000000 /* 0 */ |
---|
866 | #define SH7750_MCR_TRC_3 0x08000000 /* 3 */ |
---|
867 | #define SH7750_MCR_TRC_6 0x10000000 /* 6 */ |
---|
868 | #define SH7750_MCR_TRC_9 0x18000000 /* 9 */ |
---|
869 | #define SH7750_MCR_TRC_12 0x20000000 /* 12 */ |
---|
870 | #define SH7750_MCR_TRC_15 0x28000000 /* 15 */ |
---|
871 | #define SH7750_MCR_TRC_18 0x30000000 /* 18 */ |
---|
872 | #define SH7750_MCR_TRC_21 0x38000000 /* 21 */ |
---|
873 | |
---|
874 | #define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */ |
---|
875 | #define SH7750_MCR_TCAS_1 0x00000000 /* 1 */ |
---|
876 | #define SH7750_MCR_TCAS_2 0x00800000 /* 2 */ |
---|
877 | |
---|
878 | #define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period |
---|
879 | SDRAM: minimum number of cycles |
---|
880 | until the next bank active cmd |
---|
881 | is output after precharging */ |
---|
882 | #define SH7750_MCR_TPC_S 19 |
---|
883 | #define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */ |
---|
884 | #define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */ |
---|
885 | #define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ |
---|
886 | #define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */ |
---|
887 | #define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */ |
---|
888 | #define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */ |
---|
889 | #define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */ |
---|
890 | #define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */ |
---|
891 | |
---|
892 | #define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay time |
---|
893 | SDRAM: bank active-read/write cmd |
---|
894 | delay time */ |
---|
895 | #define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */ |
---|
896 | #define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */ |
---|
897 | #define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */ |
---|
898 | #define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */ |
---|
899 | #define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */ |
---|
900 | #define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */ |
---|
901 | #define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */ |
---|
902 | |
---|
903 | #define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */ |
---|
904 | #define SH7750_MCR_TRWL_1 0x00000000 /* 1 */ |
---|
905 | #define SH7750_MCR_TRWL_2 0x00002000 /* 2 */ |
---|
906 | #define SH7750_MCR_TRWL_3 0x00004000 /* 3 */ |
---|
907 | #define SH7750_MCR_TRWL_4 0x00006000 /* 4 */ |
---|
908 | #define SH7750_MCR_TRWL_5 0x00008000 /* 5 */ |
---|
909 | |
---|
910 | #define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS |
---|
911 | asserting period |
---|
912 | SDRAM: Command interval after |
---|
913 | synchronous DRAM refresh */ |
---|
914 | #define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */ |
---|
915 | #define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */ |
---|
916 | #define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */ |
---|
917 | #define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */ |
---|
918 | #define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */ |
---|
919 | #define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */ |
---|
920 | #define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */ |
---|
921 | #define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */ |
---|
922 | |
---|
923 | #define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */ |
---|
924 | #define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */ |
---|
925 | #define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */ |
---|
926 | #define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */ |
---|
927 | #define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */ |
---|
928 | #define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */ |
---|
929 | #define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */ |
---|
930 | #define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */ |
---|
931 | |
---|
932 | #define SH7750_MCR_BE 0x00000200 /* Burst Enable */ |
---|
933 | #define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */ |
---|
934 | #define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */ |
---|
935 | #define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */ |
---|
936 | #define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */ |
---|
937 | |
---|
938 | #define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */ |
---|
939 | #define SH7750_MCR_AMX_S 3 |
---|
940 | #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */ |
---|
941 | #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */ |
---|
942 | #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */ |
---|
943 | #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */ |
---|
944 | #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */ |
---|
945 | /* See SH7750 Hardware Manual for SDRAM address multiplexor selection */ |
---|
946 | |
---|
947 | #define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */ |
---|
948 | #define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */ |
---|
949 | #define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */ |
---|
950 | #define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */ |
---|
951 | #define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */ |
---|
952 | |
---|
953 | /* SDRAM Mode Set address */ |
---|
954 | #define SH7750_SDRAM_MODE_A2_BASE 0xFF900000 |
---|
955 | #define SH7750_SDRAM_MODE_A3_BASE 0xFF940000 |
---|
956 | #define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2)) |
---|
957 | #define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2)) |
---|
958 | #define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3)) |
---|
959 | #define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3)) |
---|
960 | |
---|
961 | |
---|
962 | /* PCMCIA Control Register (half) - PCR */ |
---|
963 | #define SH7750_PCR_REGOFS 0x800018 /* offset */ |
---|
964 | #define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS) |
---|
965 | #define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS) |
---|
966 | |
---|
967 | #define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait |
---|
968 | states to be added to the number of |
---|
969 | waits specified by WCR2 in a low-speed |
---|
970 | PCMCIA wait cycle */ |
---|
971 | #define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */ |
---|
972 | #define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */ |
---|
973 | #define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */ |
---|
974 | #define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */ |
---|
975 | |
---|
976 | #define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait |
---|
977 | states to be added to the number of |
---|
978 | waits specified by WCR2 in a low-speed |
---|
979 | PCMCIA wait cycle */ |
---|
980 | #define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */ |
---|
981 | #define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */ |
---|
982 | #define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */ |
---|
983 | #define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */ |
---|
984 | |
---|
985 | #define SH7750_PCR_A5TED 0x0E00 /* Area 5 Address-OE\/WE\ Assertion Delay, |
---|
986 | delay time from address output to |
---|
987 | OE\/WE\ assertion on the connected |
---|
988 | PCMCIA interface */ |
---|
989 | #define SH7750_PCR_A5TED_S 9 |
---|
990 | #define SH7750_PCR_A6TED 0x01C0 /* Area 6 Address-OE\/WE\ Assertion Delay*/ |
---|
991 | #define SH7750_PCR_A6TED_S 6 |
---|
992 | |
---|
993 | #define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */ |
---|
994 | #define SH7750_PCR_TED_1WS 1 /* 1 Waits inserted */ |
---|
995 | #define SH7750_PCR_TED_2WS 2 /* 2 Waits inserted */ |
---|
996 | #define SH7750_PCR_TED_3WS 3 /* 3 Waits inserted */ |
---|
997 | #define SH7750_PCR_TED_6WS 4 /* 6 Waits inserted */ |
---|
998 | #define SH7750_PCR_TED_9WS 5 /* 9 Waits inserted */ |
---|
999 | #define SH7750_PCR_TED_12WS 6 /* 12 Waits inserted */ |
---|
1000 | #define SH7750_PCR_TED_15WS 7 /* 15 Waits inserted */ |
---|
1001 | |
---|
1002 | #define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Address delay, |
---|
1003 | address hold delay time from OE\/WE\ |
---|
1004 | negation in a write on the connected |
---|
1005 | PCMCIA interface */ |
---|
1006 | #define SH7750_PCR_A5TEH_S 3 |
---|
1007 | |
---|
1008 | #define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay*/ |
---|
1009 | #define SH7750_PCR_A6TEH_S 0 |
---|
1010 | |
---|
1011 | #define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */ |
---|
1012 | #define SH7750_PCR_TEH_1WS 1 /* 1 Waits inserted */ |
---|
1013 | #define SH7750_PCR_TEH_2WS 2 /* 2 Waits inserted */ |
---|
1014 | #define SH7750_PCR_TEH_3WS 3 /* 3 Waits inserted */ |
---|
1015 | #define SH7750_PCR_TEH_6WS 4 /* 6 Waits inserted */ |
---|
1016 | #define SH7750_PCR_TEH_9WS 5 /* 9 Waits inserted */ |
---|
1017 | #define SH7750_PCR_TEH_12WS 6 /* 12 Waits inserted */ |
---|
1018 | #define SH7750_PCR_TEH_15WS 7 /* 15 Waits inserted */ |
---|
1019 | |
---|
1020 | /* Refresh Timer Control/Status Register (half) - RTSCR */ |
---|
1021 | #define SH7750_RTCSR_REGOFS 0x80001C /* offset */ |
---|
1022 | #define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS) |
---|
1023 | #define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS) |
---|
1024 | |
---|
1025 | #define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */ |
---|
1026 | #define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a |
---|
1027 | match between the refresh timer |
---|
1028 | counter and refresh time constant) */ |
---|
1029 | #define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */ |
---|
1030 | #define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */ |
---|
1031 | #define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */ |
---|
1032 | #define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */ |
---|
1033 | #define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */ |
---|
1034 | #define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */ |
---|
1035 | #define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */ |
---|
1036 | #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */ |
---|
1037 | #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */ |
---|
1038 | #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */ |
---|
1039 | |
---|
1040 | #define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */ |
---|
1041 | #define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt |
---|
1042 | Enable */ |
---|
1043 | #define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */ |
---|
1044 | #define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */ |
---|
1045 | #define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */ |
---|
1046 | |
---|
1047 | /* Refresh Timer Counter (half) - RTCNT */ |
---|
1048 | #define SH7750_RTCNT_REGOFS 0x800020 /* offset */ |
---|
1049 | #define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS) |
---|
1050 | #define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS) |
---|
1051 | |
---|
1052 | #define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */ |
---|
1053 | |
---|
1054 | /* Refresh Time Constant Register (half) - RTCOR */ |
---|
1055 | #define SH7750_RTCOR_REGOFS 0x800024 /* offset */ |
---|
1056 | #define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS) |
---|
1057 | #define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS) |
---|
1058 | |
---|
1059 | #define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */ |
---|
1060 | |
---|
1061 | /* Refresh Count Register (half) - RFCR */ |
---|
1062 | #define SH7750_RFCR_REGOFS 0x800028 /* offset */ |
---|
1063 | #define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS) |
---|
1064 | #define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS) |
---|
1065 | |
---|
1066 | #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */ |
---|
1067 | |
---|
1068 | /* |
---|
1069 | * Direct Memory Access Controller (DMAC) |
---|
1070 | */ |
---|
1071 | |
---|
1072 | /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */ |
---|
1073 | #define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */ |
---|
1074 | #define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n)) |
---|
1075 | #define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n)) |
---|
1076 | #define SH7750_SAR0 SH7750_SAR(0) |
---|
1077 | #define SH7750_SAR1 SH7750_SAR(1) |
---|
1078 | #define SH7750_SAR2 SH7750_SAR(2) |
---|
1079 | #define SH7750_SAR3 SH7750_SAR(3) |
---|
1080 | #define SH7750_SAR0_A7 SH7750_SAR_A7(0) |
---|
1081 | #define SH7750_SAR1_A7 SH7750_SAR_A7(1) |
---|
1082 | #define SH7750_SAR2_A7 SH7750_SAR_A7(2) |
---|
1083 | #define SH7750_SAR3_A7 SH7750_SAR_A7(3) |
---|
1084 | |
---|
1085 | /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */ |
---|
1086 | #define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */ |
---|
1087 | #define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n)) |
---|
1088 | #define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n)) |
---|
1089 | #define SH7750_DAR0 SH7750_DAR(0) |
---|
1090 | #define SH7750_DAR1 SH7750_DAR(1) |
---|
1091 | #define SH7750_DAR2 SH7750_DAR(2) |
---|
1092 | #define SH7750_DAR3 SH7750_DAR(3) |
---|
1093 | #define SH7750_DAR0_A7 SH7750_DAR_A7(0) |
---|
1094 | #define SH7750_DAR1_A7 SH7750_DAR_A7(1) |
---|
1095 | #define SH7750_DAR2_A7 SH7750_DAR_A7(2) |
---|
1096 | #define SH7750_DAR3_A7 SH7750_DAR_A7(3) |
---|
1097 | |
---|
1098 | /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */ |
---|
1099 | #define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */ |
---|
1100 | #define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n)) |
---|
1101 | #define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n)) |
---|
1102 | #define SH7750_DMATCR0_P4 SH7750_DMATCR(0) |
---|
1103 | #define SH7750_DMATCR1_P4 SH7750_DMATCR(1) |
---|
1104 | #define SH7750_DMATCR2_P4 SH7750_DMATCR(2) |
---|
1105 | #define SH7750_DMATCR3_P4 SH7750_DMATCR(3) |
---|
1106 | #define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0) |
---|
1107 | #define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1) |
---|
1108 | #define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2) |
---|
1109 | #define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3) |
---|
1110 | |
---|
1111 | /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */ |
---|
1112 | #define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */ |
---|
1113 | #define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n)) |
---|
1114 | #define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n)) |
---|
1115 | #define SH7750_CHCR0 SH7750_CHCR(0) |
---|
1116 | #define SH7750_CHCR1 SH7750_CHCR(1) |
---|
1117 | #define SH7750_CHCR2 SH7750_CHCR(2) |
---|
1118 | #define SH7750_CHCR3 SH7750_CHCR(3) |
---|
1119 | #define SH7750_CHCR0_A7 SH7750_CHCR_A7(0) |
---|
1120 | #define SH7750_CHCR1_A7 SH7750_CHCR_A7(1) |
---|
1121 | #define SH7750_CHCR2_A7 SH7750_CHCR_A7(2) |
---|
1122 | #define SH7750_CHCR3_A7 SH7750_CHCR_A7(3) |
---|
1123 | |
---|
1124 | #define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */ |
---|
1125 | #define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ |
---|
1126 | #define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */ |
---|
1127 | #define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */ |
---|
1128 | #define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */ |
---|
1129 | #define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */ |
---|
1130 | #define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */ |
---|
1131 | #define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */ |
---|
1132 | #define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */ |
---|
1133 | |
---|
1134 | #define SH7750_CHCR_STC 0x10000000 /* Source Address Wait Control Select, |
---|
1135 | specifies CS5 or CS6 space wait |
---|
1136 | control for PCMCIA access */ |
---|
1137 | |
---|
1138 | #define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */ |
---|
1139 | #define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ |
---|
1140 | #define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */ |
---|
1141 | #define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */ |
---|
1142 | #define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */ |
---|
1143 | #define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */ |
---|
1144 | #define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */ |
---|
1145 | #define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */ |
---|
1146 | #define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */ |
---|
1147 | |
---|
1148 | #define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control |
---|
1149 | Select, specifies CS5 or CS6 |
---|
1150 | space wait control for PCMCIA |
---|
1151 | access */ |
---|
1152 | |
---|
1153 | #define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */ |
---|
1154 | #define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */ |
---|
1155 | #define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */ |
---|
1156 | |
---|
1157 | #define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */ |
---|
1158 | #define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */ |
---|
1159 | #define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */ |
---|
1160 | |
---|
1161 | #define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */ |
---|
1162 | #define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */ |
---|
1163 | #define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle*/ |
---|
1164 | |
---|
1165 | #define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */ |
---|
1166 | #define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */ |
---|
1167 | #define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */ |
---|
1168 | |
---|
1169 | #define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */ |
---|
1170 | #define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */ |
---|
1171 | #define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */ |
---|
1172 | #define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */ |
---|
1173 | |
---|
1174 | #define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */ |
---|
1175 | #define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */ |
---|
1176 | #define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */ |
---|
1177 | #define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */ |
---|
1178 | |
---|
1179 | #define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */ |
---|
1180 | #define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Address |
---|
1181 | Mode (External Addr Space-> |
---|
1182 | External Addr Space) */ |
---|
1183 | #define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single |
---|
1184 | Address Mode (External Addr |
---|
1185 | Space -> External Device) */ |
---|
1186 | #define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single |
---|
1187 | Address Mode, (External |
---|
1188 | Device -> External Addr |
---|
1189 | Space)*/ |
---|
1190 | #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr |
---|
1191 | Space -> External Addr Space)*/ |
---|
1192 | |
---|
1193 | #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr |
---|
1194 | Space -> On-chip Peripheral |
---|
1195 | Module) */ |
---|
1196 | #define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip |
---|
1197 | Peripheral Module -> |
---|
1198 | External Addr Space */ |
---|
1199 | #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr |
---|
1200 | transfer request (external |
---|
1201 | address space -> SCTDR1) */ |
---|
1202 | #define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr |
---|
1203 | transfer request (SCRDR1 -> |
---|
1204 | External Addr Space) */ |
---|
1205 | #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr |
---|
1206 | transfer request (external |
---|
1207 | address space -> SCFTDR1) */ |
---|
1208 | #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr |
---|
1209 | transfer request (SCFRDR2 -> |
---|
1210 | External Addr Space) */ |
---|
1211 | #define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture |
---|
1212 | interrupt), (external address |
---|
1213 | space -> external address |
---|
1214 | space) */ |
---|
1215 | #define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture |
---|
1216 | interrupt), (external address |
---|
1217 | space -> on-chip peripheral |
---|
1218 | module) */ |
---|
1219 | #define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture |
---|
1220 | interrupt), (on-chip |
---|
1221 | peripheral module -> external |
---|
1222 | address space) */ |
---|
1223 | |
---|
1224 | #define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */ |
---|
1225 | #define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */ |
---|
1226 | #define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */ |
---|
1227 | |
---|
1228 | #define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */ |
---|
1229 | #define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */ |
---|
1230 | #define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */ |
---|
1231 | #define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */ |
---|
1232 | #define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */ |
---|
1233 | #define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */ |
---|
1234 | |
---|
1235 | #define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */ |
---|
1236 | #define SH7750_CHCR_TE 0x00000002 /* Transfer End */ |
---|
1237 | #define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */ |
---|
1238 | |
---|
1239 | /* DMA Operation Register - DMAOR */ |
---|
1240 | #define SH7750_DMAOR_REGOFS 0xA00040 /* offset */ |
---|
1241 | #define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS) |
---|
1242 | #define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS) |
---|
1243 | |
---|
1244 | #define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */ |
---|
1245 | |
---|
1246 | #define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */ |
---|
1247 | #define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */ |
---|
1248 | #define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */ |
---|
1249 | #define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */ |
---|
1250 | #define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */ |
---|
1251 | |
---|
1252 | #define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */ |
---|
1253 | #define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */ |
---|
1254 | #define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */ |
---|
1255 | #define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */ |
---|
1256 | |
---|
1257 | /* |
---|
1258 | * Serial Communication Interface - SCI |
---|
1259 | * Serial Communication Interface with FIFO - SCIF |
---|
1260 | */ |
---|
1261 | /* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */ |
---|
1262 | #define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014) /* offset */ |
---|
1263 | #define SH7750_SCRDR(n) SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n)) |
---|
1264 | #define SH7750_SCRDR1 SH7750_SCRDR(1) |
---|
1265 | #define SH7750_SCRDR2 SH7750_SCRDR(2) |
---|
1266 | #define SH7750_SCRDR_A7(n) SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n)) |
---|
1267 | #define SH7750_SCRDR1_A7 SH7750_SCRDR_A7(1) |
---|
1268 | #define SH7750_SCRDR2_A7 SH7750_SCRDR_A7(2) |
---|
1269 | |
---|
1270 | /* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */ |
---|
1271 | #define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C) /* offset */ |
---|
1272 | #define SH7750_SCTDR(n) SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n)) |
---|
1273 | #define SH7750_SCTDR1 SH7750_SCTDR(1) |
---|
1274 | #define SH7750_SCTDR2 SH7750_SCTDR(2) |
---|
1275 | #define SH7750_SCTDR_A7(n) SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n)) |
---|
1276 | #define SH7750_SCTDR1_A7 SH7750_SCTDR_A7(1) |
---|
1277 | #define SH7750_SCTDR2_A7 SH7750_SCTDR_A7(2) |
---|
1278 | |
---|
1279 | /* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */ |
---|
1280 | #define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000) /* offset */ |
---|
1281 | #define SH7750_SCSMR(n) SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n)) |
---|
1282 | #define SH7750_SCSMR1 SH7750_SCSMR(1) |
---|
1283 | #define SH7750_SCSMR2 SH7750_SCSMR(2) |
---|
1284 | #define SH7750_SCSMR_A7(n) SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n)) |
---|
1285 | #define SH7750_SCSMR1_A7 SH7750_SCSMR_A7(1) |
---|
1286 | #define SH7750_SCSMR2_A7 SH7750_SCSMR_A7(2) |
---|
1287 | |
---|
1288 | #define SH7750_SCSMR1_CA 0x80 /* Communication Mode (C/A\): */ |
---|
1289 | #define SH7750_SCSMR1_CA_ASYNC 0x00 /* Asynchronous Mode */ |
---|
1290 | #define SH7750_SCSMR1_CA_SYNC 0x80 /* Synchronous Mode */ |
---|
1291 | #define SH7750_SCSMR_CHR 0x40 /* Character Length: */ |
---|
1292 | #define SH7750_SCSMR_CHR_8 0x00 /* 8-bit data */ |
---|
1293 | #define SH7750_SCSMR_CHR_7 0x40 /* 7-bit data */ |
---|
1294 | #define SH7750_SCSMR_PE 0x20 /* Parity Enable */ |
---|
1295 | #define SH7750_SCSMR_PM 0x10 /* Parity Mode: */ |
---|
1296 | #define SH7750_SCSMR_PM_EVEN 0x00 /* Even Parity */ |
---|
1297 | #define SH7750_SCSMR_PM_ODD 0x10 /* Odd Parity */ |
---|
1298 | #define SH7750_SCSMR_STOP 0x08 /* Stop Bit Length: */ |
---|
1299 | #define SH7750_SCSMR_STOP_1 0x00 /* 1 stop bit */ |
---|
1300 | #define SH7750_SCSMR_STOP_2 0x08 /* 2 stop bit */ |
---|
1301 | #define SH7750_SCSMR1_MP 0x04 /* Multiprocessor Mode */ |
---|
1302 | #define SH7750_SCSMR_CKS 0x03 /* Clock Select */ |
---|
1303 | #define SH7750_SCSMR_CKS_S 0 |
---|
1304 | #define SH7750_SCSMR_CKS_DIV1 0x00 /* Periph clock */ |
---|
1305 | #define SH7750_SCSMR_CKS_DIV4 0x01 /* Periph clock / 4 */ |
---|
1306 | #define SH7750_SCSMR_CKS_DIV16 0x02 /* Periph clock / 16 */ |
---|
1307 | #define SH7750_SCSMR_CKS_DIV64 0x03 /* Periph clock / 64 */ |
---|
1308 | |
---|
1309 | /* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */ |
---|
1310 | #define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008) /* offset */ |
---|
1311 | #define SH7750_SCSCR(n) SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n)) |
---|
1312 | #define SH7750_SCSCR1 SH7750_SCSCR(1) |
---|
1313 | #define SH7750_SCSCR2 SH7750_SCSCR(2) |
---|
1314 | #define SH7750_SCSCR_A7(n) SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n)) |
---|
1315 | #define SH7750_SCSCR1_A7 SH7750_SCSCR_A7(1) |
---|
1316 | #define SH7750_SCSCR2_A7 SH7750_SCSCR_A7(2) |
---|
1317 | |
---|
1318 | #define SH7750_SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ |
---|
1319 | #define SH7750_SCSCR_RIE 0x40 /* Receive Interrupt Enable */ |
---|
1320 | #define SH7750_SCSCR_TE 0x20 /* Transmit Enable */ |
---|
1321 | #define SH7750_SCSCR_RE 0x10 /* Receive Enable */ |
---|
1322 | #define SH7750_SCSCR1_MPIE 0x08 /* Multiprocessor Interrupt Enable */ |
---|
1323 | #define SH7750_SCSCR2_REIE 0x08 /* Receive Error Interrupt Enable */ |
---|
1324 | #define SH7750_SCSCR1_TEIE 0x04 /* Transmit End Interrupt Enable */ |
---|
1325 | #define SH7750_SCSCR1_CKE 0x03 /* Clock Enable: */ |
---|
1326 | #define SH7750_SCSCR_CKE_INTCLK 0x00 /* Use Internal Clock */ |
---|
1327 | #define SH7750_SCSCR_CKE_EXTCLK 0x02 /* Use External Clock from SCK*/ |
---|
1328 | #define SH7750_SCSCR1_CKE_ASYNC_SCK_CLKOUT 0x01 /* Use SCK as a clock output |
---|
1329 | in asynchronous mode */ |
---|
1330 | |
---|
1331 | /* SCI Serial Status Register - SCSSR1(byte), SCSSR2(half) */ |
---|
1332 | #define SH7750_SCSSR_REGOFS(n) ((n) == 1 ? 0xE00010 : 0xE80010) /* offset */ |
---|
1333 | #define SH7750_SCSSR(n) SH7750_P4_REG32(SH7750_SCSSR_REGOFS(n)) |
---|
1334 | #define SH7750_SCSSR1 SH7750_SCSSR(1) |
---|
1335 | #define SH7750_SCSSR2 SH7750_SCSSR(2) |
---|
1336 | #define SH7750_SCSSR_A7(n) SH7750_A7_REG32(SH7750_SCSSR_REGOFS(n)) |
---|
1337 | #define SH7750_SCSSR1_A7 SH7750_SCSSR_A7(1) |
---|
1338 | #define SH7750_SCSSR2_A7 SH7750_SCSSR_A7(2) |
---|
1339 | |
---|
1340 | #define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */ |
---|
1341 | #define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */ |
---|
1342 | #define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */ |
---|
1343 | #define SH7750_SCSSR1_FER 0x10 /* Framing Error */ |
---|
1344 | #define SH7750_SCSSR1_PER 0x08 /* Parity Error */ |
---|
1345 | #define SH7750_SCSSR1_TEND 0x04 /* Transmit End */ |
---|
1346 | #define SH7750_SCSSR1_MPB 0x02 /* Multiprocessor Bit */ |
---|
1347 | #define SH7750_SCSSR1_MPBT 0x01 /* Multiprocessor Bit Transfer */ |
---|
1348 | |
---|
1349 | #define SH7750_SCSSR2_PERN 0xF000 /* Number of Parity Errors */ |
---|
1350 | #define SH7750_SCSSR2_PERN_S 12 |
---|
1351 | #define SH7750_SCSSR2_FERN 0x0F00 /* Number of Framing Errors */ |
---|
1352 | #define SH7750_SCSSR2_FERN_S 8 |
---|
1353 | #define SH7750_SCSSR2_ER 0x0080 /* Receive Error */ |
---|
1354 | #define SH7750_SCSSR2_TEND 0x0040 /* Transmit End */ |
---|
1355 | #define SH7750_SCSSR2_TDFE 0x0020 /* Transmit FIFO Data Empty */ |
---|
1356 | #define SH7750_SCSSR2_BRK 0x0010 /* Break Detect */ |
---|
1357 | #define SH7750_SCSSR2_FER 0x0008 /* Framing Error */ |
---|
1358 | #define SH7750_SCSSR2_PER 0x0004 /* Parity Error */ |
---|
1359 | #define SH7750_SCSSR2_RDF 0x0002 /* Receive FIFO Data Full */ |
---|
1360 | #define SH7750_SCSSR2_DR 0x0001 /* Receive Data Ready */ |
---|
1361 | |
---|
1362 | /* SCI Serial Port Register - SCSPTR1(byte) */ |
---|
1363 | #define SH7750_SCSPTR1_REGOFS 0xE0001C /* offset */ |
---|
1364 | #define SH7750_SCSPTR1 SH7750_P4_REG32(SH7750_SCSPTR1_REGOFS) |
---|
1365 | #define SH7750_SCSPTR1_A7 SH7750_A7_REG32(SH7750_SCSPTR1_REGOFS) |
---|
1366 | |
---|
1367 | #define SH7750_SCSPTR1_EIO 0x80 /* Error Interrupt Only */ |
---|
1368 | #define SH7750_SCSPTR1_SPB1IO 0x08 /* 1: Output SPB1DT bit to SCK pin */ |
---|
1369 | #define SH7750_SCSPTR1_SPB1DT 0x04 /* Serial Port Clock Port Data */ |
---|
1370 | #define SH7750_SCSPTR1_SPB0IO 0x02 /* 1: Output SPB0DT bit to TxD pin */ |
---|
1371 | #define SH7750_SCSPTR1_SPB0DT 0x01 /* Serial Port Break Data */ |
---|
1372 | |
---|
1373 | /* SCIF Serial Port Register - SCSPTR2(half) */ |
---|
1374 | #define SH7750_SCSPTR2_REGOFS 0xE80020 /* offset */ |
---|
1375 | #define SH7750_SCSPTR2 SH7750_P4_REG32(SH7750_SCSPTR2_REGOFS) |
---|
1376 | #define SH7750_SCSPTR2_A7 SH7750_A7_REG32(SH7750_SCSPTR2_REGOFS) |
---|
1377 | |
---|
1378 | #define SH7750_SCSPTR2_RTSIO 0x80 /* 1: Output RTSDT bit to RTS2\ pin */ |
---|
1379 | #define SH7750_SCSPTR2_RTSDT 0x40 /* RTS Port Data */ |
---|
1380 | #define SH7750_SCSPTR2_CTSIO 0x20 /* 1: Output CTSDT bit to CTS2\ pin */ |
---|
1381 | #define SH7750_SCSPTR2_CTSDT 0x10 /* CTS Port Data */ |
---|
1382 | #define SH7750_SCSPTR2_SPB2IO 0x02 /* 1: Output SPBDT bit to TxD2 pin */ |
---|
1383 | #define SH7750_SCSPTR2_SPB2DT 0x01 /* Serial Port Break Data */ |
---|
1384 | |
---|
1385 | /* SCI Bit Rate Register - SCBRR1(byte), SCBRR2(byte) */ |
---|
1386 | #define SH7750_SCBRR_REGOFS(n) ((n) == 1 ? 0xE00004 : 0xE80004) /* offset */ |
---|
1387 | #define SH7750_SCBRR(n) SH7750_P4_REG32(SH7750_SCBRR_REGOFS(n)) |
---|
1388 | #define SH7750_SCBRR1 SH7750_SCBRR_P4(1) |
---|
1389 | #define SH7750_SCBRR2 SH7750_SCBRR_P4(2) |
---|
1390 | #define SH7750_SCBRR_A7(n) SH7750_A7_REG32(SH7750_SCBRR_REGOFS(n)) |
---|
1391 | #define SH7750_SCBRR1_A7 SH7750_SCBRR(1) |
---|
1392 | #define SH7750_SCBRR2_A7 SH7750_SCBRR(2) |
---|
1393 | |
---|
1394 | /* SCIF FIFO Control Register - SCFCR2(half) */ |
---|
1395 | #define SH7750_SCFCR2_REGOFS 0xE80018 /* offset */ |
---|
1396 | #define SH7750_SCFCR2 SH7750_P4_REG32(SH7750_SCFCR2_REGOFS) |
---|
1397 | #define SH7750_SCFCR2_A7 SH7750_A7_REG32(SH7750_SCFCR2_REGOFS) |
---|
1398 | |
---|
1399 | #define SH7750_SCFCR2_RSTRG 0x700 /* RTS2\ Output Active Trigger; RTS2\ |
---|
1400 | signal goes to high level when the |
---|
1401 | number of received data stored in |
---|
1402 | FIFO exceeds the trigger number */ |
---|
1403 | #define SH7750_SCFCR2_RSTRG_15 0x000 /* 15 bytes */ |
---|
1404 | #define SH7750_SCFCR2_RSTRG_1 0x000 /* 1 byte */ |
---|
1405 | #define SH7750_SCFCR2_RSTRG_4 0x000 /* 4 bytes */ |
---|
1406 | #define SH7750_SCFCR2_RSTRG_6 0x000 /* 6 bytes */ |
---|
1407 | #define SH7750_SCFCR2_RSTRG_8 0x000 /* 8 bytes */ |
---|
1408 | #define SH7750_SCFCR2_RSTRG_10 0x000 /* 10 bytes */ |
---|
1409 | #define SH7750_SCFCR2_RSTRG_14 0x000 /* 14 bytes */ |
---|
1410 | |
---|
1411 | #define SH7750_SCFCR2_RTRG 0x0C0 /* Receive FIFO Data Number Trigger, |
---|
1412 | Receive Data Full (RDF) Flag sets |
---|
1413 | when number of receive data bytes is |
---|
1414 | equal or greater than the trigger |
---|
1415 | number */ |
---|
1416 | #define SH7750_SCFCR2_RTRG_1 0x000 /* 1 byte */ |
---|
1417 | #define SH7750_SCFCR2_RTRG_4 0x040 /* 4 bytes */ |
---|
1418 | #define SH7750_SCFCR2_RTRG_8 0x080 /* 8 bytes */ |
---|
1419 | #define SH7750_SCFCR2_RTRG_14 0x0C0 /* 14 bytes */ |
---|
1420 | |
---|
1421 | #define SH7750_SCFCR2_TTRG 0x030 /* Transmit FIFO Data Number Trigger, |
---|
1422 | Transmit FIFO Data Register Empty (TDFE) |
---|
1423 | flag sets when the number of remaining |
---|
1424 | transmit data bytes is equal or less |
---|
1425 | than the trigger number */ |
---|
1426 | #define SH7750_SCFCR2_TTRG_8 0x000 /* 8 bytes */ |
---|
1427 | #define SH7750_SCFCR2_TTRG_4 0x010 /* 4 bytes */ |
---|
1428 | #define SH7750_SCFCR2_TTRG_2 0x020 /* 2 bytes */ |
---|
1429 | #define SH7750_SCFCR2_TTRG_1 0x030 /* 1 byte */ |
---|
1430 | |
---|
1431 | #define SH7750_SCFCR2_MCE 0x008 /* Modem Control Enable */ |
---|
1432 | #define SH7750_SCFCR2_TFRST 0x004 /* Transmit FIFO Data Register Reset, |
---|
1433 | invalidates the transmit data in the |
---|
1434 | transmit FIFO */ |
---|
1435 | #define SH7750_SCFCR2_RFRST 0x002 /* Receive FIFO Data Register Reset, |
---|
1436 | invalidates the receive data in the |
---|
1437 | receive FIFO data register and resets |
---|
1438 | it to the empty state */ |
---|
1439 | #define SH7750_SCFCR2_LOOP 0x001 /* Loopback Test */ |
---|
1440 | |
---|
1441 | /* SCIF FIFO Data Count Register - SCFDR2(half, read-only) */ |
---|
1442 | #define SH7750_SCFDR2_REGOFS 0xE8001C /* offset */ |
---|
1443 | #define SH7750_SCFDR2 SH7750_P4_REG32(SH7750_SCFDR2_REGOFS) |
---|
1444 | #define SH7750_SCFDR2_A7 SH7750_A7_REG32(SH7750_SCFDR2_REGOFS) |
---|
1445 | |
---|
1446 | #define SH7750_SCFDR2_T 0x1F00 /* Number of untransmitted data bytes |
---|
1447 | in transmit FIFO */ |
---|
1448 | #define SH7750_SCFDR2_T_S 8 |
---|
1449 | #define SH7750_SCFDR2_R 0x001F /* Number of received data bytes in |
---|
1450 | receive FIFO */ |
---|
1451 | #define SH7750_SCFDR2_R_S 0 |
---|
1452 | |
---|
1453 | /* SCIF Line Status Register - SCLSR2(half, read-only) */ |
---|
1454 | #define SH7750_SCLSR2_REGOFS 0xE80024 /* offset */ |
---|
1455 | #define SH7750_SCLSR2 SH7750_P4_REG32(SH7750_SCLSR2_REGOFS) |
---|
1456 | #define SH7750_SCLSR2_A7 SH7750_A7_REG32(SH7750_SCLSR2_REGOFS) |
---|
1457 | |
---|
1458 | #define SH7750_SCLSR2_ORER 0x0001 /* Overrun Error */ |
---|
1459 | |
---|
1460 | /* |
---|
1461 | * SCI-based Smart Card Interface |
---|
1462 | */ |
---|
1463 | /* Smart Card Mode Register - SCSCMR1(byte) */ |
---|
1464 | #define SH7750_SCSCMR1_REGOFS 0xE00018 /* offset */ |
---|
1465 | #define SH7750_SCSCMR1 SH7750_P4_REG32(SH7750_SCSCMR1_REGOFS) |
---|
1466 | #define SH7750_SCSCMR1_A7 SH7750_A7_REG32(SH7750_SCSCMR1_REGOFS) |
---|
1467 | |
---|
1468 | #define SH7750_SCSCMR1_SDIR 0x08 /* Smart Card Data Transfer Direction: */ |
---|
1469 | #define SH7750_SCSCMR1_SDIR_LSBF 0x00 /* LSB-first */ |
---|
1470 | #define SH7750_SCSCMR1_SDIR_MSBF 0x08 /* MSB-first */ |
---|
1471 | |
---|
1472 | #define SH7750_SCSCMR1_SINV 0x04 /* Smart Card Data Inversion */ |
---|
1473 | #define SH7750_SCSCMR1_SMIF 0x01 /* Smart Card Interface Mode Select */ |
---|
1474 | |
---|
1475 | /* Smart-card specific bits in other registers */ |
---|
1476 | /* SCSMR1: */ |
---|
1477 | #define SH7750_SCSMR1_GSM 0x80 /* GSM mode select */ |
---|
1478 | |
---|
1479 | /* SCSSR1: */ |
---|
1480 | #define SH7750_SCSSR1_ERS 0x10 /* Error Signal Status */ |
---|
1481 | |
---|
1482 | /* |
---|
1483 | * I/O Ports |
---|
1484 | */ |
---|
1485 | /* Port Control Register A - PCTRA */ |
---|
1486 | #define SH7750_PCTRA_REGOFS 0x80002C /* offset */ |
---|
1487 | #define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS) |
---|
1488 | #define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS) |
---|
1489 | |
---|
1490 | #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */ |
---|
1491 | #define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */ |
---|
1492 | #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */ |
---|
1493 | #define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */ |
---|
1494 | |
---|
1495 | /* Port Data Register A - PDTRA(half) */ |
---|
1496 | #define SH7750_PDTRA_REGOFS 0x800030 /* offset */ |
---|
1497 | #define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS) |
---|
1498 | #define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS) |
---|
1499 | |
---|
1500 | #define SH7750_PDTRA_BIT(n) (1 << (n)) |
---|
1501 | |
---|
1502 | /* Port Control Register B - PCTRB */ |
---|
1503 | #define SH7750_PCTRB_REGOFS 0x800040 /* offset */ |
---|
1504 | #define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS) |
---|
1505 | #define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS) |
---|
1506 | |
---|
1507 | #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */ |
---|
1508 | #define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */ |
---|
1509 | #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */ |
---|
1510 | #define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */ |
---|
1511 | |
---|
1512 | /* Port Data Register B - PDTRB(half) */ |
---|
1513 | #define SH7750_PDTRB_REGOFS 0x800044 /* offset */ |
---|
1514 | #define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS) |
---|
1515 | #define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS) |
---|
1516 | |
---|
1517 | #define SH7750_PDTRB_BIT(n) (1 << ((n)-16)) |
---|
1518 | |
---|
1519 | /* GPIO Interrupt Control Register - GPIOIC(half) */ |
---|
1520 | #define SH7750_GPIOIC_REGOFS 0x800048 /* offset */ |
---|
1521 | #define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS) |
---|
1522 | #define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS) |
---|
1523 | |
---|
1524 | #define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */ |
---|
1525 | |
---|
1526 | /* |
---|
1527 | * Interrupt Controller - INTC |
---|
1528 | */ |
---|
1529 | /* Interrupt Control Register - ICR (half) */ |
---|
1530 | #define SH7750_ICR_REGOFS 0xD00000 /* offset */ |
---|
1531 | #define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS) |
---|
1532 | #define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS) |
---|
1533 | |
---|
1534 | #define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */ |
---|
1535 | #define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */ |
---|
1536 | |
---|
1537 | #define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */ |
---|
1538 | #define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while |
---|
1539 | SR.BL bit is set to 1 */ |
---|
1540 | #define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL bit |
---|
1541 | set to 1 */ |
---|
1542 | |
---|
1543 | #define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */ |
---|
1544 | #define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on falling |
---|
1545 | edge of NMI input */ |
---|
1546 | #define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on rising |
---|
1547 | edge of NMI input */ |
---|
1548 | |
---|
1549 | #define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */ |
---|
1550 | #define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded |
---|
1551 | interrupt requests */ |
---|
1552 | #define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four independent |
---|
1553 | interrupt requests */ |
---|
1554 | |
---|
1555 | /* Interrupt Priority Register A - IPRA (half) */ |
---|
1556 | #define SH7750_IPRA_REGOFS 0xD00004 /* offset */ |
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1557 | #define SH7750_IPRA SH7750_P4_REG32(SH7750_IPRA_REGOFS) |
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1558 | #define SH7750_IPRA_A7 SH7750_A7_REG32(SH7750_IPRA_REGOFS) |
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1559 | |
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1560 | #define SH7750_IPRA_TMU0 0xF000 /* TMU0 interrupt priority */ |
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1561 | #define SH7750_IPRA_TMU0_S 12 |
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1562 | #define SH7750_IPRA_TMU1 0x0F00 /* TMU1 interrupt priority */ |
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1563 | #define SH7750_IPRA_TMU1_S 8 |
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1564 | #define SH7750_IPRA_TMU2 0x00F0 /* TMU2 interrupt priority */ |
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1565 | #define SH7750_IPRA_TMU2_S 4 |
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1566 | #define SH7750_IPRA_RTC 0x000F /* RTC interrupt priority */ |
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1567 | #define SH7750_IPRA_RTC_S 0 |
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1568 | |
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1569 | /* Interrupt Priority Register B - IPRB (half) */ |
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1570 | #define SH7750_IPRB_REGOFS 0xD00008 /* offset */ |
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1571 | #define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS) |
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1572 | #define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS) |
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1573 | |
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1574 | #define SH7750_IPRB_WDT 0xF000 /* WDT interrupt priority */ |
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1575 | #define SH7750_IPRB_WDT_S 12 |
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1576 | #define SH7750_IPRB_REF 0x0F00 /* Memory Refresh unit interrupt |
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1577 | priority */ |
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1578 | #define SH7750_IPRB_REF_S 8 |
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1579 | #define SH7750_IPRB_SCI1 0x00F0 /* SCI1 interrupt priority */ |
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1580 | #define SH7750_IPRB_SCI1_S 4 |
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1581 | |
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1582 | /* Interrupt Priority Register C - IPRC (half) */ |
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1583 | #define SH7750_IPRC_REGOFS 0xD00004 /* offset */ |
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1584 | #define SH7750_IPRC SH7750_P4_REG32(SH7750_IPRC_REGOFS) |
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1585 | #define SH7750_IPRC_A7 SH7750_A7_REG32(SH7750_IPRC_REGOFS) |
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1586 | |
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1587 | #define SH7750_IPRC_GPIO 0xF000 /* GPIO interrupt priority */ |
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1588 | #define SH7750_IPRC_GPIO_S 12 |
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1589 | #define SH7750_IPRC_DMAC 0x0F00 /* DMAC interrupt priority */ |
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1590 | #define SH7750_IPRC_DMAC_S 8 |
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1591 | #define SH7750_IPRC_SCIF 0x00F0 /* SCIF interrupt priority */ |
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1592 | #define SH7750_IPRC_SCIF_S 4 |
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1593 | #define SH7750_IPRC_HUDI 0x000F /* H-UDI interrupt priority */ |
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1594 | #define SH7750_IPRC_HUDI_S 0 |
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1595 | |
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1596 | |
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1597 | /* |
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1598 | * User Break Controller registers |
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1599 | */ |
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1600 | #define SH7750_BARA 0x200000 /* Break address regiser A */ |
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1601 | #define SH7750_BAMRA 0x200004 /* Break address mask regiser A */ |
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1602 | #define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */ |
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1603 | #define SH7750_BARB 0x20000c /* Break address regiser B */ |
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1604 | #define SH7750_BAMRB 0x200010 /* Break address mask regiser B */ |
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1605 | #define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */ |
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1606 | #define SH7750_BASRB 0x000018 /* Break ASID regiser B */ |
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1607 | #define SH7750_BDRB 0x200018 /* Break data regiser B */ |
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1608 | #define SH7750_BDMRB 0x20001c /* Break data mask regiser B */ |
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1609 | #define SH7750_BRCR 0x200020 /* Break control register */ |
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1610 | |
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1611 | #define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */ |
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1612 | |
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1613 | #endif |
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