source: rtems/bsps/sh/gensh2/include/sh/sh7_sci.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 2.7 KB
Line 
1/*
2 * Bit values for the serial control registers of the Hitachi SH704X
3 *
4 * From Hitachi tutorials
5 *
6 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7 *           Bernd Becker (becker@faw.uni-ulm.de)
8 *
9 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.rtems.org/license/LICENSE.
22 */
23
24#ifndef _sh7_sci_h
25#define _sh7_sci_h
26
27#include <rtems/score/iosh7045.h>
28
29/*
30 * Serial mode register bits
31 */
32
33#define SCI_SYNC_MODE               0x80
34#define SCI_SEVEN_BIT_DATA          0x40
35#define SCI_PARITY_ON               0x20
36#define SCI_ODD_PARITY              0x10
37#define SCI_STOP_BITS_2             0x08
38#define SCI_ENABLE_MULTIP           0x04
39#define SCI_PHI_64                  0x03
40#define SCI_PHI_16                  0x02
41#define SCI_PHI_4                   0x01
42#define SCI_PHI_0                   0x00
43
44/*
45 * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
46 */
47
48#define SCI_SMR                 0x00
49#define SCI_BRR                 0x01
50#define SCI_SCR                 0x02
51#define SCI_TDR                 0x03
52#define SCI_SSR                 0x04
53#define SCI_RDR                 0x05
54
55/*
56 * Serial control register bits
57 */
58#define SCI_TIE                 0x80    /* Transmit interrupt enable */
59#define SCI_RIE                 0x40    /* Receive interrupt enable */
60#define SCI_TE                  0x20    /* Transmit enable */
61#define SCI_RE                  0x10    /* Receive enable */
62#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
63#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
64#define SCI_CKE1                0x02    /* Clock enable 1 */
65#define SCI_CKE0                0x01    /* Clock enable 0 */
66
67/*
68 * Serial status register bits
69 */
70#define SCI_TDRE                0x80    /* Transmit data register empty */
71#define SCI_RDRF                0x40    /* Receive data register full */
72#define SCI_ORER                0x20    /* Overrun error */
73#define SCI_FER                 0x10    /* Framing error */
74#define SCI_PER                 0x08    /* Parity error */
75#define SCI_TEND                0x04    /* Transmit end */
76#define SCI_MPB                 0x02    /* Multiprocessor bit */
77#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
78
79/*
80 * INTC Priority Settings
81 */
82
83#define SCI0_IPMSK      0x00F0
84#define SCI0_LOWIP      0x0010
85#define SCI1_IPMSK      0x000F
86#define SCI1_LOWIP      0x0001
87
88#endif /* _sh7_sci_h */
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