source: rtems/bsps/sh/gensh2/include/rtems/score/ispsh7045.h @ 0706581

5
Last change on this file since 0706581 was 0706581, checked in by Joel Sherrill <joel@…>, on Mar 7, 2018 at 8:31:31 PM

misc sh: Remove includes of rtems/score/types.h

  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.org/license/LICENSE.
21 *
22 *  Modified to reflect isp entries for sh7045 processor:
23 *  John M. Mills (jmills@tga.com)
24 *  TGA Technologies, Inc.
25 *  100 Pinnacle Way, Suite 140
26 *  Norcross, GA 30071 U.S.A.
27 *
28 *
29 *  This modified file may be copied and distributed in accordance
30 *  the above-referenced license. It is provided for critique and
31 *  developmental purposes without any warranty nor representation
32 *  by the authors or by TGA Technologies.
33 */
34
35#ifndef __CPU_ISPS_H
36#define __CPU_ISPS_H
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42extern void __ISR_Handler( uint32_t   vector );
43
44
45/*
46 * interrupt vector table offsets
47 */
48#define NMI_ISP_V 11
49#define USB_ISP_V 12
50#define IRQ0_ISP_V 64
51#define IRQ1_ISP_V 65
52#define IRQ2_ISP_V 66
53#define IRQ3_ISP_V 67
54#define IRQ4_ISP_V 68
55#define IRQ5_ISP_V 69
56#define IRQ6_ISP_V 70
57#define IRQ7_ISP_V 71
58#define DMA0_ISP_V 72
59#define DMA1_ISP_V 76
60#define DMA2_ISP_V 80
61#define DMA3_ISP_V 84
62
63#define MTUA0_ISP_V 88
64#define MTUB0_ISP_V 89
65#define MTUC0_ISP_V 90
66#define MTUD0_ISP_V 91
67#define MTUV0_ISP_V 92
68
69#define MTUA1_ISP_V 96
70#define MTUB1_ISP_V 97
71#define MTUV1_ISP_V 100
72#define MTUU1_ISP_V 101
73
74#define MTUA2_ISP_V 104
75#define MTUB2_ISP_V 105
76#define MTUV2_ISP_V 108
77#define MTUU2_ISP_V 109
78
79#define MTUA3_ISP_V 112
80#define MTUB3_ISP_V 113
81#define MTUC3_ISP_V 114
82#define MTUD3_ISP_V 115
83#define MTUV3_ISP_V 116
84
85#define MTUA4_ISP_V 120
86#define MTUB4_ISP_V 121
87#define MTUC4_ISP_V 122
88#define MTUD4_ISP_V 123
89#define MTUV4_ISP_V 124
90
91#define ERI0_ISP_V 128
92#define RXI0_ISP_V 129
93#define TXI0_ISP_V 130
94#define TEI0_ISP_V 131
95
96#define ERI1_ISP_V 132
97#define RXI1_ISP_V 133
98#define TXI1_ISP_V 134
99#define TEI1_ISP_V 135
100
101#define ADI0_ISP_V 136
102#define ADI1_ISP_V 137
103#define DTC_ISP_V 140  /* Data Transfer Controller */
104#define CMT0_ISP_V 144 /* Compare Match Timer */
105#define CMT1_ISP_V 148
106#define WDT_ISP_V 152  /* Wtachdog Timer */
107#define CMI_ISP_V 153  /* BSC RAS interrupt */
108#define OEI_ISP_V 156  /* I/O Port */
109#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
110#if 0
111#define PRT_ISP_V /* parity error - no equivalent */
112#endif
113
114/* dummy ISP */
115extern void _dummy_isp( void );
116
117/* Non Maskable Interrupt */
118extern void _nmi_isp( void );
119
120/* User Break Controller */
121extern void _usb_isp( void );
122
123/* External interrupts 0-7 */
124extern void _irq0_isp( void );
125extern void _irq1_isp( void );
126extern void _irq2_isp( void );
127extern void _irq3_isp( void );
128extern void _irq4_isp( void );
129extern void _irq5_isp( void );
130extern void _irq6_isp( void );
131extern void _irq7_isp( void );
132
133/* DMA - Controller */
134extern void _dma0_isp( void );
135extern void _dma1_isp( void );
136extern void _dma2_isp( void );
137extern void _dma3_isp( void );
138
139/* Interrupt Timer Unit */
140/* Timer 0 */
141extern void _mtua0_isp( void );
142extern void _mtub0_isp( void );
143extern void _mtuc0_isp( void );
144extern void _mtud0_isp( void );
145extern void _mtuv0_isp( void );
146/* Timer 1 */
147extern void _mtua1_isp( void );
148extern void _mtub1_isp( void );
149extern void _mtuv1_isp( void );
150extern void _mtuu1_isp( void );
151/* Timer 2 */
152extern void _mtua2_isp( void );
153extern void _mtub2_isp( void );
154extern void _mtuv2_isp( void );
155extern void _mtuu2_isp( void );
156/* Timer 3 */
157extern void _mtua3_isp( void );
158extern void _mtub3_isp( void );
159extern void _mtuc3_isp( void );
160extern void _mtud3_isp( void );
161extern void _mtuv3_isp( void );
162/* Timer 4 */
163extern void _mtua4_isp( void );
164extern void _mtub4_isp( void );
165extern void _mtuc4_isp( void );
166extern void _mtud4_isp( void );
167extern void _mtuv4_isp( void );
168
169/* serial interfaces */
170extern void _eri0_isp( void );
171extern void _rxi0_isp( void );
172extern void _txi0_isp( void );
173extern void _tei0_isp( void );
174extern void _eri1_isp( void );
175extern void _rxi1_isp( void );
176extern void _txi1_isp( void );
177extern void _tei1_isp( void );
178
179/* ADC */
180extern void _adi0_isp( void );
181extern void _adi1_isp( void );
182
183/* Data Transfer Controller */
184extern void _dtci_isp( void );
185
186/* Compare Match Timer */
187extern void _cmt0_isp( void );
188extern void _cmt1_isp( void );
189
190/* Watchdog Timer */
191extern void _wdt_isp( void );
192
193/* DRAM refresh control unit of bus state controller */
194extern void _bsc_isp( void );
195
196/* I/O Port */
197extern void _oei_isp( void );
198
199/* Parity Control Unit of the Bus State Controllers */
200/* extern void _prt_isp( void ); */
201
202#ifdef __cplusplus
203}
204#endif
205
206#endif
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