1 | /* |
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2 | * This file contains the clock driver the Hitachi SH 704X |
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3 | */ |
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4 | |
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5 | /* |
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6 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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7 | * Bernd Becker (becker@faw.uni-ulm.de) |
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8 | * |
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9 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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10 | * |
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11 | * This program is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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14 | * |
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15 | * COPYRIGHT (c) 1998. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * Modified to reflect registers of sh7045 processor: |
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19 | * John M. Mills (jmills@tga.com) |
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20 | * TGA Technologies, Inc. |
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21 | * 100 Pinnacle Way, Suite 140 |
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22 | * Norcross, GA 30071 U.S.A. |
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23 | * August, 1999 |
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24 | * |
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25 | * This modified file may be copied and distributed in accordance |
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26 | * the above-referenced license. It is provided for critique and |
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27 | * developmental purposes without any warranty nor representation |
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28 | * by the authors or by TGA Technologies. |
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29 | * |
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30 | * The license and distribution terms for this file may be |
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31 | * found in the file LICENSE in this distribution or at |
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32 | * http://www.rtems.org/license/LICENSE. |
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33 | */ |
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34 | |
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35 | #include <rtems.h> |
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36 | |
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37 | #include <stdlib.h> |
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38 | |
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39 | #include <rtems/clockdrv.h> |
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40 | #include <rtems/score/sh_io.h> |
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41 | #include <rtems/score/sh.h> |
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42 | #include <rtems/score/ispsh7045.h> |
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43 | #include <rtems/score/iosh7045.h> |
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44 | |
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45 | static void Clock_exit( void ); |
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46 | |
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47 | extern uint32_t bsp_clicks_per_second; |
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48 | |
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49 | #define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16) |
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50 | |
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51 | #ifndef CLOCKPRIO |
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52 | #define CLOCKPRIO 10 |
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53 | #endif |
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54 | |
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55 | #define MTU0_STARTMASK 0xfe |
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56 | #define MTU0_SYNCMASK 0xfe |
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57 | #define MTU0_MODEMASK 0xc0 |
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58 | #define MTU0_TCRMASK 0x22 /* bit 7 also used, vs 703x */ |
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59 | #define MTU0_STAT_MASK 0xc0 |
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60 | #define MTU0_IRQMASK 0xfe |
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61 | #define MTU0_TIERMASK 0x01 |
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62 | #define IPRC_MTU0_MASK 0xff0f |
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63 | #define MTU0_TIORVAL 0x08 |
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64 | |
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65 | /* |
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66 | * The interrupt vector number associated with the clock tick device |
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67 | * driver. |
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68 | */ |
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69 | |
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70 | #define CLOCK_VECTOR MTUA0_ISP_V |
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71 | |
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72 | /* |
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73 | * Clock_driver_ticks is a monotonically increasing counter of the |
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74 | * number of clock ticks since the driver was initialized. |
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75 | */ |
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76 | volatile uint32_t Clock_driver_ticks; |
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77 | |
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78 | static rtems_isr Clock_isr( rtems_vector_number vector ); |
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79 | static uint32_t Clock_MHZ ; |
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80 | |
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81 | /* |
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82 | * Clock_isrs is the number of clock ISRs until the next invocation of |
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83 | * the RTEMS clock tick routine. The clock tick device driver |
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84 | * gets an interrupt once a millisecond and counts down until the |
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85 | * length of time between the user configured microseconds per tick |
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86 | * has passed. |
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87 | */ |
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88 | uint32_t Clock_isrs; /* ISRs until next tick */ |
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89 | static uint32_t Clock_isrs_const; /* only calculated once */ |
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90 | |
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91 | /* |
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92 | * The previous ISR on this clock tick interrupt vector. |
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93 | */ |
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94 | rtems_isr_entry Old_ticker; |
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95 | |
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96 | /* |
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97 | * Isr Handler |
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98 | */ |
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99 | static rtems_isr Clock_isr( |
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100 | rtems_vector_number vector |
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101 | ) |
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102 | { |
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103 | /* |
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104 | * bump the number of clock driver ticks since initialization |
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105 | * |
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106 | |
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107 | * determine if it is time to announce the passing of tick as configured |
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108 | * to RTEMS through the rtems_clock_tick directive |
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109 | * |
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110 | * perform any timer dependent tasks |
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111 | */ |
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112 | uint8_t temp; |
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113 | |
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114 | /* reset the flags of the status register */ |
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115 | temp = read8( MTU_TSR0) & MTU0_STAT_MASK; |
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116 | write8( temp, MTU_TSR0); |
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117 | |
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118 | Clock_driver_ticks++ ; |
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119 | |
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120 | if( Clock_isrs == 1) |
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121 | { |
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122 | rtems_clock_tick(); |
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123 | Clock_isrs = Clock_isrs_const; |
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124 | } |
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125 | else |
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126 | { |
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127 | Clock_isrs-- ; |
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128 | } |
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129 | } |
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130 | |
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131 | /* |
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132 | * Install_clock |
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133 | * |
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134 | * Install a clock tick handler and reprograms the chip. This |
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135 | * is used to initially establish the clock tick. |
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136 | */ |
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137 | static void Install_clock( |
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138 | rtems_isr_entry clock_isr |
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139 | ) |
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140 | { |
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141 | uint8_t temp8 = 0; |
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142 | uint32_t factor = 1000000; |
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143 | |
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144 | /* |
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145 | * Initialize the clock tick device driver variables |
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146 | */ |
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147 | |
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148 | Clock_driver_ticks = 0; |
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149 | Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000; |
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150 | Clock_isrs = Clock_isrs_const; |
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151 | |
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152 | factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */ |
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153 | Clock_MHZ = bsp_clicks_per_second / factor ; |
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154 | |
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155 | rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); |
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156 | |
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157 | /* |
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158 | * Hardware specific initialize goes here |
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159 | */ |
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160 | |
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161 | /* stop Timer 0 */ |
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162 | temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; |
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163 | write8( temp8, MTU_TSTR); |
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164 | |
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165 | /* set initial counter value to 0 */ |
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166 | write16( 0, MTU_TCNT0); |
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167 | |
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168 | /* Timer 0 runs independent */ |
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169 | temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK; |
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170 | write8( temp8, MTU_TSYR); |
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171 | |
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172 | /* Timer 0 normal mode */ |
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173 | temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK; |
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174 | write8( temp8, MTU_TMDR0); |
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175 | |
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176 | /* TCNT is cleared by GRA ; internal clock /16 */ |
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177 | write8( MTU0_TCRMASK , MTU_TCR0); |
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178 | |
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179 | /* use GRA without I/O - pins */ |
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180 | write8( MTU0_TIORVAL, MTU_TIORL0); |
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181 | |
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182 | /* reset flags of the status register */ |
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183 | temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK; |
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184 | write8( temp8, MTU_TSR0); |
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185 | |
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186 | /* Irq if is equal GRA */ |
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187 | temp8 = read8( MTU_TIER0) | MTU0_TIERMASK; |
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188 | write8( temp8, MTU_TIER0); |
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189 | |
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190 | /* set interrupt priority */ |
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191 | if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL) |
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192 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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193 | |
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194 | /* set counter limits */ |
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195 | write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A); |
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196 | |
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197 | /* start counter */ |
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198 | temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK; |
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199 | write8( temp8, MTU_TSTR); |
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200 | |
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201 | /* |
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202 | * Schedule the clock cleanup routine to execute if the application exits. |
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203 | */ |
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204 | atexit( Clock_exit ); |
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205 | } |
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206 | |
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207 | /* |
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208 | * Clean up before the application exits |
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209 | */ |
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210 | void Clock_exit( void ) |
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211 | { |
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212 | uint8_t temp8 = 0; |
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213 | |
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214 | /* turn off the timer interrupts */ |
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215 | /* set interrupt priority to 0 */ |
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216 | if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL) |
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217 | rtems_fatal_error_occurred( RTEMS_UNSATISFIED); |
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218 | |
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219 | /* |
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220 | * temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK; |
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221 | * write16( temp16, MTU_TIER0); |
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222 | */ |
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223 | |
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224 | /* stop counter */ |
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225 | temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; |
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226 | write8( temp8, MTU_TSTR); |
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227 | |
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228 | /* old vector shall not be installed */ |
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229 | } |
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230 | |
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231 | void _Clock_Initialize( void ) |
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232 | { |
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233 | Install_clock( Clock_isr ); |
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234 | } |
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