1 | /* |
---|
2 | * This file contains the basic algorithms for all assembly code used |
---|
3 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
---|
4 | * in assembly language |
---|
5 | * |
---|
6 | * NOTE: This port uses a C file with inline assembler instructions |
---|
7 | * |
---|
8 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
---|
9 | * Bernd Becker (becker@faw.uni-ulm.de) |
---|
10 | * |
---|
11 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
---|
12 | * |
---|
13 | * This program is distributed in the hope that it will be useful, |
---|
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
---|
16 | * |
---|
17 | * |
---|
18 | * COPYRIGHT (c) 1998. |
---|
19 | * On-Line Applications Research Corporation (OAR). |
---|
20 | * |
---|
21 | * The license and distribution terms for this file may be |
---|
22 | * found in the file LICENSE in this distribution or at |
---|
23 | * http://www.rtems.org/license/LICENSE. |
---|
24 | * |
---|
25 | */ |
---|
26 | |
---|
27 | /* |
---|
28 | * This is supposed to be an assembly file. This means that system.h |
---|
29 | * and cpu.h should not be included in a "real" cpu_asm file. An |
---|
30 | * implementation in assembly should include "cpu_asm.h" |
---|
31 | */ |
---|
32 | |
---|
33 | #include <rtems/system.h> |
---|
34 | #include <rtems/score/percpu.h> |
---|
35 | #include <rtems/score/isr.h> |
---|
36 | #include <rtems/score/threaddispatch.h> |
---|
37 | #include <rtems/score/sh.h> |
---|
38 | #include <rtems/score/ispsh7032.h> |
---|
39 | |
---|
40 | #include <rtems/score/ispsh7032.h> |
---|
41 | #include <rtems/score/iosh7032.h> |
---|
42 | #include <rtems/score/sh_io.h> |
---|
43 | |
---|
44 | unsigned long *_old_stack_ptr; |
---|
45 | |
---|
46 | register unsigned long *stack_ptr __asm__ ("r15"); |
---|
47 | |
---|
48 | /* |
---|
49 | * sh_set_irq_priority |
---|
50 | * |
---|
51 | * this function sets the interrupt level of the specified interrupt |
---|
52 | * |
---|
53 | * parameters: |
---|
54 | * - irq : interrupt number |
---|
55 | * - prio: priority to set for this interrupt number |
---|
56 | * |
---|
57 | * returns: 0 if ok |
---|
58 | * -1 on error |
---|
59 | */ |
---|
60 | |
---|
61 | unsigned int sh_set_irq_priority( |
---|
62 | unsigned int irq, |
---|
63 | unsigned int prio ) |
---|
64 | { |
---|
65 | uint32_t shiftcount; |
---|
66 | uint32_t prioreg; |
---|
67 | uint16_t temp16; |
---|
68 | ISR_Level level; |
---|
69 | |
---|
70 | /* |
---|
71 | * first check for valid interrupt |
---|
72 | */ |
---|
73 | if (( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) |
---|
74 | return -1; |
---|
75 | /* |
---|
76 | * check for valid irq priority |
---|
77 | */ |
---|
78 | if ( prio > 15 ) |
---|
79 | return -1; |
---|
80 | |
---|
81 | /* |
---|
82 | * look up appropriate interrupt priority register |
---|
83 | */ |
---|
84 | if ( irq > 71) |
---|
85 | { |
---|
86 | irq = irq - 72; |
---|
87 | shiftcount = 12 - ((irq & ~0x03) % 16); |
---|
88 | |
---|
89 | switch( irq / 16) |
---|
90 | { |
---|
91 | case 0: { prioreg = INTC_IPRC; break;} |
---|
92 | case 1: { prioreg = INTC_IPRD; break;} |
---|
93 | case 2: { prioreg = INTC_IPRE; break;} |
---|
94 | default: return -1; |
---|
95 | } |
---|
96 | } |
---|
97 | else |
---|
98 | { |
---|
99 | shiftcount = 12 - 4 * ( irq % 4); |
---|
100 | if ( irq > 67) |
---|
101 | prioreg = INTC_IPRB; |
---|
102 | else |
---|
103 | prioreg = INTC_IPRA; |
---|
104 | } |
---|
105 | |
---|
106 | /* |
---|
107 | * Set the interrupt priority register |
---|
108 | */ |
---|
109 | _ISR_Local_disable( level ); |
---|
110 | |
---|
111 | temp16 = read16( prioreg); |
---|
112 | temp16 &= ~( 15 << shiftcount); |
---|
113 | temp16 |= prio << shiftcount; |
---|
114 | write16( temp16, prioreg); |
---|
115 | |
---|
116 | _ISR_Local_enable( level ); |
---|
117 | |
---|
118 | return 0; |
---|
119 | } |
---|
120 | |
---|
121 | /* |
---|
122 | * This routine provides the RTEMS interrupt management. |
---|
123 | */ |
---|
124 | |
---|
125 | void __ISR_Handler( uint32_t vector) |
---|
126 | { |
---|
127 | ISR_Level level; |
---|
128 | |
---|
129 | _ISR_Local_disable( level ); |
---|
130 | |
---|
131 | _Thread_Dispatch_disable(); |
---|
132 | |
---|
133 | if ( _ISR_Nest_level == 0 ) |
---|
134 | { |
---|
135 | /* Install irq stack */ |
---|
136 | _old_stack_ptr = stack_ptr; |
---|
137 | stack_ptr = _CPU_Interrupt_stack_high; |
---|
138 | } |
---|
139 | |
---|
140 | _ISR_Nest_level++; |
---|
141 | |
---|
142 | _ISR_Local_enable( level ); |
---|
143 | |
---|
144 | /* call isp */ |
---|
145 | if ( _ISR_Vector_table[ vector]) |
---|
146 | (*_ISR_Vector_table[ vector ])( vector ); |
---|
147 | |
---|
148 | _ISR_Local_disable( level ); |
---|
149 | |
---|
150 | _Thread_Dispatch_unnest( _Per_CPU_Get() ); |
---|
151 | |
---|
152 | _ISR_Nest_level--; |
---|
153 | |
---|
154 | if ( _ISR_Nest_level == 0 ) |
---|
155 | /* restore old stack pointer */ |
---|
156 | stack_ptr = _old_stack_ptr; |
---|
157 | |
---|
158 | _ISR_Local_enable( level ); |
---|
159 | |
---|
160 | if ( _ISR_Nest_level ) |
---|
161 | return; |
---|
162 | |
---|
163 | if ( !_Thread_Dispatch_is_enabled() ) { |
---|
164 | return; |
---|
165 | } |
---|
166 | |
---|
167 | if ( _Thread_Dispatch_necessary ) { |
---|
168 | _Thread_Dispatch(); |
---|
169 | } |
---|
170 | } |
---|